Re: [myhdl-list] Slicing an unsigned intbv to a signed one

[Jan D. <ja...@ja...>]

Günter Dannoritzer wrote:

> For example in Verilog you can do:
> 
>    reg signed  [3:0] a;
>    reg         [3:0] b;
> 
>    a[3] = 1'b1;
>    b[3] = 1'b1;
>    $display("a: %d b: %d", a,b);
> 
> a: -8 b:  8
> 
> Setting the msb is setting the sign bit. However, that does not work in 
> MyHDL, as the underlying data type is an integer and despite the value 
> restriction the sign bit is not bit 3 in this case. MyHDL will just 
> complain that the value exceeds the range.

Right, as in Python there is an "indefinite" number sign
bits to the left.

An implication is that there is no way to make an intbv
negative by setting some indivitual bit. To make it
negative, you'd first have to do:

a[:] = -1

and after that, it would stay negative whatever you
do to indivual bits.

Jan

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