Re: [myhdl-list] Slicing an unsigned intbv to a signed one

[Günter D. <dan...@we...>]

Christopher L. Felton wrote:
> I don't believe there is an easy way to do this in MyHDL.  I have found 
> is some cases that the Verilog way of doing thing isn't always a good 
> way in MyHDL.  In most cases Verilog doesn't really care about the 
> number that the bits represent.  And MyHDL is different (at least the 
> case when using min and max)  that it is concerned with the actual value 
> that the bits represent.

Well, I think the core difference is that Verilog really only considers 
the bits as specified whereas in MyHDL there is still an integer data 
type underneath.

For example in Verilog you can do:

   reg signed  [3:0] a;
   reg         [3:0] b;

   a[3] = 1'b1;
   b[3] = 1'b1;
   $display("a: %d b: %d", a,b);

a: -8 b:  8

Setting the msb is setting the sign bit. However, that does not work in 
MyHDL, as the underlying data type is an integer and despite the value 
restriction the sign bit is not bit 3 in this case. MyHDL will just 
complain that the value exceeds the range.

...
> 
> I have not mixed the "signed" (limits set) and the generic bit-vector in 
> the past with MyHDL, I usually have to approach the design from a MyHDL 
> perspective.

I think that is my deficit. I am getting comfortable with Verilog and 
having a hard time getting rid of the low level bit twiddling and 
looking at a problem form a higher level with MyHDL.

> 
> Below is a version that worked, I don't think it is an approach that you 
> would want to take though.  It synthesizes correctly, if you look at the 
> Verilog netlist for the Xilinx XST synthesis tool.  You are relying a 
> lot on the synthesis tool to determine that you are doing nothing but 
> relocating bits.

Thanks for the code. Interesting to see how it could work.

Cheers,

Guenter