Re: [myhdl-list] Slicing an unsigned intbv to a signed one

[Christopher L. F. <cf...@uc...>]

I don't believe there is an easy way to do this in MyHDL.  I have  
found is some cases that the Verilog way of doing thing isn't always a  
good way in MyHDL.  In most cases Verilog doesn't really care about  
the number that the bits represent.  And MyHDL is different (at least  
the case when using min and max)  that it is concerned with the actual  
value that the bits represent.

As you mentioned you are looking for a way to start out representing  
the value as a generic collection of bits and then convert slices of  
the bit-vector to a signed version.  Also as you pointed out, in  
Verilog if you need the language to know that the value is signed (for  
signed extension or other built in operators that the sign would  
affect) you can essentially cast with  the $signed or by using signed  
types.

I have not mixed the "signed" (limits set) and the generic bit-vector  
in the past with MyHDL, I usually have to approach the design from a  
MyHDL perspective.

Below is a version that worked, I don't think it is an approach that  
you would want to take though.  It synthesizes correctly, if you look  
at the Verilog netlist for the Xilinx XST synthesis tool.  You are  
relying a lot on the synthesis tool to determine that you are doing  
nothing but relocating bits.