[myhdl-list] blocking and non-blocking assignments in toVerilog code.

[Günter D. <dan...@we...>]

Maybe I am not up to date and this got actually already fixed. I justed 
noticed that in the Verilog generated code of the stopwatch example:

   http://myhdl.jandecaluwe.com/doku.php/cookbook:stopwatch

there are blocking and non-blocking assignments in the same always block.

Is that intended or would it be better to have only non-blocking 
assignments used?

Guenter