Re: [myhdl-list] Strange problem, VALUES instead of symbols being toVerilog'ed

[Christopher L. F. <cf...@uc...>]

>
> To solve the problem fundamentally, there are some options. MyHDL  
> could give
> an error if a sequence of generators contains other things. Probably  
> we should
> limit this to special kinds of hardware-oriented generators, the  
> ones created
> by MyHDL decorators. Or MyHDL could "filter" return values and throw  
> out
> what it doesn't like. I think I prefer the first option.


I would agree, the first solution (MyHDL checks the returned  
generators) makes more sense than filter.  During simulation and  
conversion the other outputs would be useless in any case.