Re: [myhdl-list] Strange problem, VALUES instead of symbols being toVerilog'ed

[Jan D. <ja...@ja...>]

Oystein Homelien wrote:
> On Wed, 7 May 2008, Jan Decaluwe wrote:
> 
> 
>>I'm trying to understand your example:
> 
> 
> Thanks for the quick reply!  I really appreciate it.  Was a little scared 
> since there has been little activity on the list..
> 
> 
>>- I see that wb is passed as a parameter, but also returned by the
>>module. Why is that necessary?
> 
> 
> I return wb to avoid an extra line in the main module, "powersoc";
> 
>      i_uart, wb_uart = uart.uart(wb.slave(0xC), baudclk, rxd, txd) # moving 
> this up fixed stuff

Ok, this is the problem. When, in the uart, you say:

     return (registers, transmitter), wb

the result is no longer a "sequence of generators". MyHDL uses this to decide whether
or not the function represents hardware or not. The problem is that the uart is
silently ignored during hierarchy extraction.

Workaround:

in uart.py:
     return (registers, transmitter)

in powersoc:
     wb_uart = wb.slave(0xC)
     i_uart  = uart.uart(wb_uart, baudclk, rxd, txd) # moving this up fixed stuff

To solve the problem fundamentally, there are some options. MyHDL could give
an error if a sequence of generators contains other things. Probably we should
limit this to special kinds of hardware-oriented generators, the ones created
by MyHDL decorators. Or MyHDL could "filter" return values and throw out
what it doesn't like. I think I prefer the first option.

Jan



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