Re: [myhdl-list] Strange problem, VALUES instead of symbols being toVerilog'ed

[Oystein H. <oy...@ho...>]

On Wed, 7 May 2008, Jan Decaluwe wrote:

> I'm trying to understand your example:

Thanks for the quick reply!  I really appreciate it.  Was a little scared 
since there has been little activity on the list..

> - I see that wb is passed as a parameter, but also returned by the
> module. Why is that necessary?

I return wb to avoid an extra line in the main module, "powersoc";

     i_uart, wb_uart = uart.uart(wb.slave(0xC), baudclk, rxd, txd) # moving 
this up fixed stuff

wb.slave() is supposed to set up a slave wishbone instance with chip 
select for the given major nibble, and for all modules I return the 
wishbone bus as well as the instance itself so I can avoid typing:

 	wb_uart = wb.slave(0x0C)
 	iuart = uart.uart(wb_uart, ...)

It just seems clearer to me, but opinions may differ.  Could this be the 
problem, if I just skip returning it then it will work?  Then why does it 
work for all the other slaves:

     i_rom, wb_rom = zpu.rom(wb.slave(0x0))
     i_bram, wb_bram = hw.sram(wb.slave(0xF), sram)
     i_debugreg, wb_debugreg = hw.debugreg(wb.slave(0xE), debugreg);

.. as expected (i think)?  The design, prior to adding the uart, converts 
and synthesizes.

> - what is wb? if it's a class instance, as suggested by the code, I don't
> understand how you get to converted code at all. I tried it, and toVerilog
> chokes on return values that are not generators or sequences of generators.
> Did you perhaps modify some of the code in _extractHierarchy.py?

It's a class instance so that I can avoid typing all the signal names 
every time I change parts of the bus (see hw.py in my example).  I find it 
gives much clearer code to be able to pass class instances like this, the 
only annoyance is that myhdl barfs on them during conversion so I have to 
"explode" the buses in the top of the instance functions:

     wb_rst_i, wb_clk_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i
  =  wb.rst_i, wb.clk_i, wb.adr_i, wb.dat_o, wb.dat_i, wb.we_i, wb.sel_i, wb.stb_i, wb.ack_o, wb.cyc_i

I basically replace "." by "_".  Is it possible MyHDL (convertible) might 
support this usage pattern (without having to "explode" the buses) in the 
future?  I tried having a look at the code but it made little sense to me.
It is just for grouping of signals.

Regarding whether I modified myhdl, Yes I did try to remove an assertion 
but nothing more.  If you try my design ("python powersoc") on various 
versions of myhdl you will see that it usually converts, but some versions 
barf with an assertion on curlevel < -1 or something like that.

Sorry for not being more presice, I will look further into this when I get 
home, just wanted to get your reactions on my thoughts above.

And thank you _very much_ for making MyHDL.  I simply love it!


Oystein Homelien, CVO             |  oy...@po...
PowerTech Information Systems AS  |  http://www.powertech.no/
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