Re: [myhdl-list] Strange problem, VALUES instead of symbols being toVerilog'ed

[Jan D. <ja...@ja...>]

I'm trying to understand your example:

- I see that wb is passed as a parameter, but also returned by the
module. Why is that necessary?

- what is wb? if it's a class instance, as suggested by the code, I don't
understand how you get to converted code at all. I tried it, and toVerilog
chokes on return values that are not generators or sequences of generators.
Did you perhaps modify some of the code in _extractHierarchy.py?

Jan

Oystein Homelien wrote:
> Hello, this is my first post although I have lurked for some time.  First 
> of all let me say that I simply love the idea of MyHDL.  The simplicity 
> and power of python, direct to synthesizable verilog code..  yummie!
> 
> Second I must admit that I am a newbie, so be nice with me.  I have done 
> some stuff with MyHDL and stumbled upon some of its (or verilog's?) 
> limitations wrt verilog conversion.  So far I have been able to work 
> around all of them, but now I am stuck.
> 
> I am adding a myhdl "uart" module to my project.  The instance is in the 
> file uart.py, def uart().  Here's the start of it:
> 
> def uart(wb, baudclk, rxd, txd):
>      wb_rst_i, wb_clk_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i
>   =  wb.rst_i, wb.clk_i, wb.adr_i, wb.dat_o, wb.dat_i, wb.we_i, wb.sel_i, wb.stb_i, wb.ack_o, wb.cyc_i
> ;
>      char = Signal(bool(0));
>      send = Signal(bool(0));
>      sending = Signal(bool(0));
>      send_done = Signal(bool(0));
> 
>      @always(wb_clk_i.posedge)
>      def registers():
>          wb_ack_o.next = False
>          if wb_cyc_i:
>              if wb_we_i:
>                  char.next = wb_dat_i
>                  send.next = True
>              else:
>                  wb_dat_o.next = concat(intbv(0x11)[5:], rxd, send, sending)
>              wb_ack_o.next = True
> 
> .. as you can see I am "exploding" a wishbone bus in the beginning, and 
> then declaring some internal registers (at least this is what I am trying 
> to do).  But, registers() is converted into the following verilog:
> 
> always @(posedge wb_clk_i) begin: POWERSOC_I_UART_0
>      uart_ack_o <= 0;
>      if (uart_cyc_i) begin
>          if (wb_we_o) begin
>              False <= wb_dat_o;     <-- LOOK HERE
>              False <= 1;            <-- AND HERE
>          end
>          else begin
>              uart_dat_o <= {5'h11, rxd, False, False};  <-- AND HERE
>          end
>          uart_ack_o <= 1;
>      end
> end
> 
> .. it seems as though the _values_ of my vars are being written to verilog 
> instead of the symbol names.  What am I doing wrong?  It only happens with 
> the uart, and I have tried all kinds of strange things to make it work. Of 
> course this does not synthesize (i use Xilinx' tools).  :-)
> 
> I have put a zip file with design files for you to try yourself 
> (./powersoc), at http://home.powertech.no/oystein/myhdl-bug1.zip .
> 
> For the record, I have tried it with the following myhdl versions:
> 
> drwxr-xr-x 8 oystein oystein   4096 2008-05-07 12:51 myhdl-0.5.1dev1
> -rw-r--r-- 1 oystein oystein 768032 2008-05-07 12:50 myhdl-0.5.1dev1.tar.gz
> drwxr-xr-x 7 oystein oystein   4096 2008-05-07 12:48 myhdl-0.5c1
> -rw-r--r-- 1 oystein oystein 760268 2008-05-07 12:47 myhdl-0.5c1.tar.gz
> drwxr-xr-x 6 oystein oystein   4096 2008-05-07 12:47 myhdl-0.6dev6
> -rw-r--r-- 1 oystein oystein 156404 2008-05-07 12:46 myhdl-0.6dev6.tar.gz
> drwxr-xr-x 6 oystein oystein   4096 2008-05-07 10:24 myhdl-0.6dev8
> -rw-r--r-- 1 oystein oystein 181734 2008-05-07 10:23 myhdl-0.6dev8.tar.gz
> 
> .. i could not get it working.  Hope to get some input on how to work 
> around this.
> 
> yours,
> oystein
> 
> 
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