Re: [myhdl-list] Calling VHDL modules within MyHDL?

[Jan D. <ja...@ja...>]

Tom Dillon wrote:
> Jan,
> 
> Could he not use User-defined Verilog code to make a connection to the Verilog module then use a 
> Verilog simulator for simulation?
> 
> http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-conv-user.html
> 
> Could even just use regular float numbers and simulate with MyHDL and only use the User-defined 
> Verilog when converting to Verilog.

Correct, this is an interesting solution. One would still have to write
a MyHDL model "manually" for MyHDL simulation, but it can be a high
level model that is much simpler than the (synthesizable) equivalent
that may be available in Verilog/VHDL.

This is definitely one of the target applications of user-defined
Verilog/VHDL code.

Thanks,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com