Re: [myhdl-list] Calling VHDL modules within MyHDL?

[Blubaugh, D. A. <dbl...@be...>]

Tom and Jan,


The logic behind this is to use MyHDL and ultimately python as a
platform to QUICKLY develop simulation as to how the algorithm, with the
assistance of the floating-point verilog modules, is truly behaving.  I
ultimately believe that MyHDL with the integration of the ability to
develop, simulate, test, and finally generate floating-point-based
algorithms within Verilog or VHDL would make a unique development
platform.  Also there are legacy VHDL modules that could be imported by
MyHDL for simulation and testing purposes.  In final words, please do
not refer to me in the third person.  

Thanks,

David Blubaugh
 

-----Original Message-----
From: myh...@li...
[mailto:myh...@li...] On Behalf Of Tom
Dillon
Sent: Tuesday, April 08, 2008 2:26 PM
To: General discussions on MyHDL
Subject: Re: [myhdl-list] Calling VHDL modules within MyHDL?

Jan,

Could he not use User-defined Verilog code to make a connection to the
Verilog module then use a Verilog simulator for simulation?

http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-conv-user.html

Could even just use regular float numbers and simulate with MyHDL and
only use the User-defined Verilog when converting to Verilog.

On the other hand, it would not be very difficult to implement the
floating point modules in MyHDL.

Tom


On Tuesday 08 April 2008 10:31:17 am Jan Decaluwe wrote:
> Blubaugh, David A. wrote:
> > Chris,
> >
> >
> > Is there a way to call or import modules in VHDL or Verilog into
MyHDL?
>
> Not currently.
>
> > If that can be done, I believe, I can call or import a VHDL module 
> > from OPENCORES.org which handles the necessary floating-point 
> > multiplication, subtraction, addition, and especially division.  
> > Does anyone believe that this is feasible??
>
> Probably yes.
>
> However, I think it will be difficult to find a MyHDL-lover to 
> implement such a capabibility. It would be a lot of work that would 
> promote keeping VHDL or Verilog as a front-end language.
>
> Here's an alternative. If you find a useful open-source IP block, why 
> not rewrite it in MyHDL? Look at the advantages:
>
> * for a write-once, use-many IP block, rewriting makes sense
> * rewriting may be straightforward or easy, given the existing code
> * verification is likely much easier/elegant using Python and a unit 
> test framework * you would jumpstart a MyHDL IP library
> * with the MyHDL convertors, you would now have an equivalent block 
> available in 3 languages: MyHDL, Verilog and VHDL. This capability is 
> unique, and makes this approach even interesting to those who prefer 
> to stick with Verilog an VHDL.
>
> Jan



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