Re: [myhdl-list] Bit-wise inversion issue

[Jan D. <ja...@ja...>]

Christopher L. Felton wrote:
> Jan,
> 
> First, thanks for the changes in the latest development release, 
> incredible effort on your end with the timely changes!
> 
> But (there is always a but) the VHDL conversion with the development 
> build fails (at least for my example)?  I have not looked into the 
> details why it is failing, but I attached the files that I am using and 
> below is the error.
> 
> The Verilog conversion works fine, by inspection and cosimulation it is 
> valid (haven't synthesized).

Thanks, I'm able to reproduce the error. Unfortunately the fix is
not as obvious as I thought at first - apparently some special
care is needed to deal with the conversion of bit inversions used
in expresssions. (And next week I'm on holiday so it may take
some time.)

Jan

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