Re: [myhdl-list] Bit-wise inversion issue

[Christopher L. F. <cf...@uc...>]

Jan,

First, thanks for the changes in the latest development release,  
incredible effort on your end with the timely changes!

But (there is always a but) the VHDL conversion with the development  
build fails (at least for my example)?  I have not looked into the  
details why it is failing, but I attached the files that I am using  
and below is the error.

The Verilog conversion works fine, by inspection and cosimulation it  
is valid (haven't synthesized).

*** Error ?? ****
     def inferBinaryOpType(self, node, left, right, op=None):
E       if isinstance(left.vhd, (vhd_boolean, vhd_std_logic)):
 >       AttributeError: Invert instance has no attribute 'vhd'
**** ****

Thanks



On Mar 9, 2008, at 10:44 AM, Jan Decaluwe wrote:

> Jan Decaluwe wrote:
>
>> Conclusion
>> ----------
>>
>> The drawback of the "Pure Python" solution is probably fatal
>> for practical purposes. Therefore, I propose to keep the
>> "Practical Hardware" solution.
>
> I have implemented this, including conversion support for
> Verilog and VHDL.
>
> This will be included in the upcoming development release 0.6dev7.
>
> Jan
>
> -- 
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Kaboutermansstraat 97, B-3000 Leuven, Belgium
>     From Python to silicon:
>     http://myhdl.jandecaluwe.com
>
>
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