Re: [myhdl-list] FW: Floating-point support

[Jan D. <ja...@ja...>]

Blubaugh, David A. wrote:
> Thank you very much for your response.  
> 
> 
> 
> The commercial packages that I am referring to is the ImpulseC complier.
> This compiler can extract c source code, which has been written with
> floats and doubles.  Where upon it then converts most of the C- source
> code, including the float and double mathematical processing, and
> converts it directly into VHDL or verilog.  This is done for high
> precision and numerical applications research, like the Fast Fourier
> Transform.

If I understand this correctly, the tool starts from an untimed c description
and generates RTL code. It contains features such as scheduling and resource
allocation and can therefore be qualified as a "behavioral synthesis tool".

I believe that the analogy in the Python world would be a behavioral synthesis
tool that takes a generic Python description as input and generates RTL code,
perhaps using a Python package such as MyHDL. MyHDL adds an event-driven
paradigm to Python, to you need something like it for "timed" hardware
descriptions.

Therefore, MyHDL is of little help for the input part of a similar Python-based
tool, and it has nothing that can help with the behavioral synthesis part.
Developing a behavioral synthesis tool is a truly large effort. If I would
consider such an effort, I would start a separate project.

Best regards,

Jan

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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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