Re: [myhdl-list] MyHDL usable for Transaction Level Modeling ?

[Jan D. <ja...@ja...>]

hma...@fr... wrote:
> Hi,
> 
> I'm wondering if/how MyHDL could be used as an ESL language for system
> simulations "a la" SystemC but without the burden of C++ ?

I'm pretty sure beautiful things can be accomplished here.

> I'd like to make simulations of a system on chip (simulate traffic on an
> interconnection micronetwork from several initiators like CPU, DSP, DMA, etc...
> and dimension accordingly memory bit width, latencies, FIFO sizes, etc...).
> 
> I'm aware speed might be an issue depending on teh level of modeling used, but
> for a high-level TLM I'm not scared a priori.

Right attitude.

> It strikes me that Python should be used for ESL, andif MyHDL for some reason is
> not suitable, at least the same generator mechanism could be reused.

Yes. Note that MyHDL in terms of modeling is intended to be fairly general
though.

(The limitations imposed by conversion to Verilog/VHDL are just that - limitations
of convertibility. Pure MyHDL modeling is way more powerful.)

> Obviously, the Verilog converter is of lesser interest in this case. May be a
> SystemC converter .. ?

Mm, even a system on chip needs to implemented at some time, right? :-)

Jan

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