[myhdl-list] MyHDL usable for Transaction Level Modeling ?

[<hma...@fr...>]

Hi,

I'm wondering if/how MyHDL could be used as an ESL language for system
simulations "a la" SystemC but without the burden of C++ ?

I'd like to make simulations of a system on chip (simulate traffic on an
interconnection micronetwork from several initiators like CPU, DSP, DMA, etc...
and dimension accordingly memory bit width, latencies, FIFO sizes, etc...).

I'm aware speed might be an issue depending on teh level of modeling used, but
for a high-level TLM I'm not scared a priori.

It strikes me that Python should be used for ESL, andif MyHDL for some reason is
not suitable, at least the same generator mechanism could be reused.

Obviously, the Verilog converter is of lesser interest in this case. May be a
SystemC converter .. ?

Any comment ?

Regards,
Hervé