[myhdl-list] Issue with namespaces after conversion
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jandecaluwe
From: Jan D. <ja...@ja...> - 2008-03-17 20:16:29
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For the next development release I want to address all outstanding bug requests. I have implemented a satisfactory fix for all of them except one, and I'd like to make everyone aware of this. The problem is that conversion flattens hierarchy, and signals get renamed to have a "global" name that is non-conflicting among themselves. However, those new names may conflict with "local" names from variables within generators/processes/always blocks. This issue is not detected in current releases. The way to solve this would be to change local names if necessary. However, this is not so trivial. Moreover, there are other naming issues (e.g. VHDL and Verilog keywords are not detected at this moment) so this calls for a general solution that solves all naming issues at once. But there's no time to do that now. So what I have implemented is simply to detect the situation and flag it as an "error". This is not satisfactory, but at least you'll get an early warning. The bug report in question lives here: http://sourceforge.net/tracker/index.php?func=detail&aid=1837003&group_id=91207&atid=596332 Regards, Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Kaboutermansstraat 97, B-3000 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com |