Re: [myhdl-list] Bit-wise inversion issue

[Jan D. <ja...@ja...>]

Tom Dillon wrote:
> I don't think the sliced result gets ._nrbits .min or .max set. 
> 
> I think it should, at least for clarification.

Actually a slice returns a new intbv with _nrbits, min and max set.
(this is the idiomatic way to create an "unsigned", hardware-oriented
intbv).

But it is the only operator that does this. All others currently
return unsized intbv's or even int's.

This is usually not an issue, because the idiomiatic MyHDL usage
for updates is:

for intbv's:
    a[m:n] = <expression>
in particular, to set a new value:
    a[:] = <expression>
and for signals:
    s.next = <expression>

Therefore, I don't need to look at the right-hand expression to derive
a bit width. In this way, all issues with this as in VHDL and especially
Verilog are simply avoided. And of course I can optimize a little
(and keep it simple) by not worrying about setting bit widths on operator
results. Last but not least, I don't think that conversion to VHDL or
Verilog would otherwise be feasible.

Jan

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