Re: [myhdl-list] Bit-wise inversion issue
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jandecaluwe
From: Christopher L. F. <cf...@uc...> - 2008-02-28 14:49:10
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Here is a possible enhancement, from _intbv.py around line 407 <<code>> def __invert__(self): if self._nrbits: if self._min < 0: return intbv(~self._val, min=self._min, max=self._max) else: return intbv(~self._val & (1L << self._nrbits)-1) else: return intbv(~self._val) <<>> I ran the test scripts, it didn't break anything. Also the sequential mult that I sent works with the 2's comp flip. On Feb 28, 2008, at 7:00 AM, Christopher L. Felton wrote: > Is the following expected behavior? > > >>> y = intbv(15)[4:] > >>> ~y > intbv(0L) > >>> z = ~y > >>> z._nrbits > 0 > >>> > > The new number of bits is 0? I think in normal case this is fine > because usually it would be Signal.next, and the Signal type > wouldn't be overridden only the value? > > > On Feb 27, 2008, at 2:41 PM, Tom Dillon wrote: > >> Jan, >> >> On Wednesday 27 February 2008 02:33:57 pm Jan Decaluwe wrote: >> >>>> >>>> intbv(5)[3:] is unsigned, so I think 2L is the right answer. >>> >>> That's not how I think about it. (Warning: this may get subtle.) >>> To me, intbv(5)[3:] is simply intbv(5) with constraints on the >>> allowed >>> values. If the constraints are such that the value must be positive, >>> then we can choose to represent such an intbv as an unsigned in >>> another language such as Verilog or VHDL. An optimization really. >> >> yes, I agree with you thinking there. I was thinking the slice >> would produce an unsigned intbv, but >> of course that is wrong. >> >> I think it has to make sense and be as simple as possible in MyHDL >> and force the translation to >> Verilog or VHDL to produce the same results. >> >>> >>> On the other hand, I see your point of course. We should be >>> practical. I have to think further, there may be compromise >>> solutions. >>> >>> In any case, there really is something wrong. Consider: >>>>>> ~intbv(5, min=-6, max=6) >>> >>> intbv(10L) >> >> What about ~intbv(5,min=0, max=15)? >> >> intbv(10L) >> >> I think that is correct. >> >> Tom >> >> ------------------------------------------------------------------------- >> This SF.net email is sponsored by: Microsoft >> Defy all challenges. Microsoft(R) Visual Studio 2008. >> http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/ >> _______________________________________________ >> myhdl-list mailing list >> myh...@li... >> https://lists.sourceforge.net/lists/listinfo/myhdl-list > > ------------------------------------------------------------------------- > This SF.net email is sponsored by: Microsoft > Defy all challenges. Microsoft(R) Visual Studio 2008. > http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/_______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |