Re: [myhdl-list] Bit-wise inversion issue

[Christopher L. F. <cf...@uc...>]

Does this make sense, and is it possible (easily possible)

intbv(5)                     -> signed, because this is consistent with
                                 default python as you showed
                                 default min=-??, default max=??

intbv(5)[4:]                 ->  unsigned, has the feel of
                                  Verilog/VHDL bit-vectors
                                  default min=0, default max=16

intbv(5, min=0, max=15)      -> unsigned because explicitly defined no  
min

intbv(5, min=-8, max=7)      -> signed because explicitly defined min

intbv(5, min=-8, max=7)[4:]  -> ??

 >>> x = intbv(5, min=-8, max=7)[4:]
 >>> x
intbv(5L)
 >>> dir(x)
 >>> x._nrbits
4
 >>> x._val
5L
 >>> x.max
16
 >>> x.min
0
 >>>

Think the above would be somewhat straight forward, since the last  
example shows that the [4:] syntax overrides the min.

Chris

On Feb 27, 2008, at 1:33 PM, Jan Decaluwe wrote:

>
>>>> ~intbv(5, min=-6, max=6)
> intbv(10L)
>
> This intbv would have to be represented by a signed in a target
> language, yet bitwise inversion still returns a positive number
> with the current implementation. As a miminum, this should be
> fixed - if someone disagrees, let me know.
>
> Jan
>
> -- 
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Kaboutermansstraat 97, B-3000 Leuven, Belgium
>     From Python to silicon:
>     http://myhdl.jandecaluwe.com
>
>
> -------------------------------------------------------------------------
> This SF.net email is sponsored by: Microsoft
> Defy all challenges. Microsoft(R) Visual Studio 2008.
> http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list