Re: [myhdl-list] Bit-wise inversion issue

[Christopher F. <cf...@uc...>]

> In any case, there really is something wrong. Consider:
> 
> >>> ~intbv(5, min=-6, max=6)
> intbv(10L)
>
> This intbv would have to be represented by a signed in a target
> language, yet bitwise inversion still returns a positive number
> with the current implementation. As a miminum, this should be
> fixed - if someone disagrees, let me know.

I agree, we are representing 2 types (at least in Verilog speak) with
intbv.  Unsigned bit vectors and signed bit vectors.  As you pointed
out we need to determine what is the correct usage given the context.

As Tom pointed out for the bit vector that would be the expected value
but for a signed bit vector value you will run into the problem above.

Thanks!