Re: [myhdl-list] Bit-wise inversion issue

[Jan D. <ja...@ja...>]

Tom Dillon wrote:

> I'm not sure there is anything wrong, although I may not fully understand...
> 
> On Wednesday 27 February 2008 10:06:33 am Jan Decaluwe wrote:
> 
>>Chris Felton has recently signalled an issue with bit-wise
>>inversion. Hereby an analysis.
>>
>>Consider the following interpreter log:
>> >>> from myhdl import *
>> >>> ~5
>>-6
> 
> That is because a python int is signed, right?
> 
>> >>> ~intbv(5)
>>intbv(-6)
> 
> default intbv must be signed as well.
> 
>> >>> ~intbv(5)[3:]
>>intbv(2L)
> 
> intbv(5)[3:] is unsigned, so I think 2L is the right answer.

That's not how I think about it. (Warning: this may get subtle.)
To me, intbv(5)[3:] is simply intbv(5) with constraints on the allowed
values. If the constraints are such that the value must be positive,
then we can choose to represent such an intbv as an unsigned in
another language such as Verilog or VHDL. An optimization really.

On the other hand, I see your point of course. We should be
practical. I have to think further, there may be compromise solutions.

In any case, there really is something wrong. Consider:

 >>> ~intbv(5, min=-6, max=6)
intbv(10L)

This intbv would have to be represented by a signed in a target
language, yet bitwise inversion still returns a positive number
with the current implementation. As a miminum, this should be
fixed - if someone disagrees, let me know.

Jan

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