Re: [myhdl-list] Bit-wise inversion issue

[Tom D. <TD...@di...>]

Hi,

I'm not sure there is anything wrong, although I may not fully understand...

On Wednesday 27 February 2008 10:06:33 am Jan Decaluwe wrote:
> Chris Felton has recently signalled an issue with bit-wise
> inversion. Hereby an analysis.
>
> Consider the following interpreter log:
>  >>> from myhdl import *
>  >>> ~5
> -6

That is because a python int is signed, right?
>
>  >>> ~intbv(5)
> intbv(-6)

default intbv must be signed as well.

>
>  >>> ~intbv(5)[3:]
>intbv(2L)

intbv(5)[3:] is unsigned, so I think 2L is the right answer. 

I would not expect a unsigned to get changed to signed with the ~ operator.

So I think the only question is should intbv(5)[3:] result in a signed or unsigned result?

I don't know if I would use Verilog as the guideline for how anything signed should work, as the 
Verilog rules are fairly complicated (overly I think).

Tom