[myhdl-list] Bit-wise inversion issue

[Jan D. <ja...@ja...>]

Chris Felton has recently signalled an issue with bit-wise
inversion. Hereby an analysis.

Consider the following interpreter log:

 >>> from myhdl import *
 >>> ~5
-6
 >>> ~intbv(5)
intbv(-6)
 >>> ~intbv(5)[3:]
intbv(2L)

You can see that an "unsized" intbv behaves like an int,
but a "sized" intbv behaves differently. Obviously confusing.

Why is this? The answer is in the original support for
conversion to Verilog and VHDL. Originally, only unsigned
values were supported. But in Verilog and VHDL those
don't behave like a Python int: bit-wise inversion of
an unsigned (and therefore positive) number still returns
a positive number. In contrast, the sign of an int
is always changed upon bit-wise inversion.

I modified the behavior of sized intbv's to mimic Verilog
behavior. In this way the original convertor could support
bit-wise inversion without signed/unsigned machinery. This
behavior has not been changed since.

Looking at this now, I think it is wrong. A sized intbv
should also behave like a Python int. So I think the current
behavior should be changed.

The convertor should cast unsigned arguments to signed,
to get the desired result (hopefully, to be checked).

This would imply a backward-incompatible change of intbv
behavior (but it could be viewed as a bug fix). So please
review this carefully and give feedback if necessary.

Jan

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