Re: [myhdl-list] Array ports in verilog conversion

[Jan D. <ja...@ja...>]

Leonardo Laguna Ruiz wrote:
> Hi!
> 
> I'm trying to make a block with an undefined number of inputs and outputs.
> An example is shown below. This in simulation works fine, and in the verilog
> conversion the only thing that does not work is that the 'us' and 'ds' ports
> are not defined.
> 
> Is there any way to explicitly declare that a module has the ports 'us' and
> 'ds', and these are arrays of bool signals ?????  

Unfortunately no, the problem is how to map these to Verilog ports.

However, this restriction only applies to the very top-level - for internal
modules you can use list of signals and convert to Verilog.

You may want to read the following cookbook design report; it deals with
these issues (and other ones) explicitly:

    http://myhdl.jandecaluwe.com/doku.php/cookbook:bitonic

Jan

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