[myhdl-list] Array ports in verilog conversion

[Leonardo L. R. <leo...@up...>]

Hi!

I'm trying to make a block with an undefined number of inputs and outputs.
An example is shown below. This in simulation works fine, and in the verilog
conversion the only thing that does not work is that the 'us' and 'ds' ports
are not defined.

Is there any way to explicitly declare that a module has the ports 'us' and
'ds', and these are arrays of bool signals ?????  


--------------------------------------------
def my_block (clk,us,ds):
    
    my_block_array =[ my_sub_block(clk,us[i],ds[i]) for i in range(4) ]

    return my_block_array

---------------------------------------------
us =  [ Signal(bool(0)) for i in range(4) ] 
ds =  [ Signal(bool(0)) for i in range(4) ]

my_block_instance = my_block(clk,us,ds)
--------------------------------------------


generated verilog:
--------------------
module my_block (
    clk
);



Thanks



Leonardo Laguna Ruiz
PhD. Student
 
Centro de Electrónica Industrial
E.T.S.I. Industriales
Universidad Politécnica de Madrid (UPM)

leo...@up...