[myhdl-list] Time discrepancy

[Kanchan D. <kan...@gm...>]

Hi,

I am a PhD student and do Verilog design as part of my research work. In
order to perform benchmarking, I have been using cosimulation to test my
Verilog code. I have three designs described below that essentially do
the *same
*thing:

- Design A is completely written in Python
- Design B has a Python framework, but the core functionality is written in
myhdl (with the clock )
- Design C has the Verilog module performing the core function, and the
framework is in Python (as in the above two cases). I use the $from_myhdl()
and $to_myhdl() task calls to pass the stimuli between the Verilog module
and the Python module.

When I provide similar stimuli to all the three designs and use time.clock()
to measure the simulation time,  Design A is the fastest and Design B takes
the longest to run.  My questions are the following:


1. How come Design C is faster than Design B? The set-up seems more complex
( at least,intuitively) in the former case, since multiple task calls are
involved.

2.What may be the reason for one being faster than the other?

Thanks
 KD