Re: [myhdl-list] List of Signals == Memory

[Jan D. <ja...@ja...>]

Christopher L. Felton wrote:
> In this newsgroup a "List of Signals" appears to be a common theme or 
> misunderstanding.  I think it is a "natural" Pythonic usage of lists as 
> general containers, to group items, build structures, etc.
> 
> With the current implementation there are some limitations to using a 
> list of signals.  Example the "list syntax" cannot be used in the 
> generator code.  This seems to break a very natural way of writing HDL 
> in python.

Thanks for the analysis. However, I'm not sure we all understand where this
is coming from. I'll try to clarify that first.

It should be obvious (but perhaps useful to stress to newbies) that the
limitations have nothing to do with MyHDL modelling. Instead, the - admittedly
confusing - complexities are intended to avoid limitations of Verilog or
Verilog synthesis tools.

I refer to the thread "RAM inference from toVerilog output" dated 08/09/2005.
This announces the first release with RAM inteference support. You will note
that memories were given "priority" in that release, meaning that any list
of signals was simply declared as a memory. Clean and simple, so I thought.
But note the implication: memory syntax would potentially be introduced in always
blocks, even if not present in the original MyHDL generator. (This is a
consequence of the fact that the convertor flattens hierarchy.)

Tom Dillon spotted potential problems with cosimulation and synthesis. Let's
leave cosimulation aside for the moment. He indicated that synthesis tools
and/or Verilog would have problems with memory syntax, for example if a
memory member would be indexed or sliced.

I realized that he was right, so I backed off and did the "cleverer" thing
that you're now all struggling with :-)

Before doing anything else, I believe we should now review the assumptions.
Synthesis tools have evolved and so has Verilog in the mean time. Based on
that info, we may be able to do something sensible - otherwise we are
walking in the dark.

Specifically, I'd like to know how memory syntax (including member slicing
and indexing) is currently supported in (System)Verilog, and in mainstream
synthesis tools. Anyone with useful info on this - please let us know.

Jan

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