Re: [myhdl-list] List of Signals

[Jan D. <ja...@ja...>]

Vanheesbeke Stefaan wrote:
> Terrific, this is what I looked for, and indeed as you siggest the solution was already ion other posts...

Why not avoid combinatorial assignments alltogether, like so:

def TestSigs(Clk, Reset, Enable, DataIn, DataOut, Size=3):

     sigs = [Signal(bool(0)) for i in range(Size+1)]
     # aliases
     sigs[0] = DataIn
     sigs[Size] = DataOut

     blocks = []
     for i in range(Size):
         blocks.append(TestFunc(Clk, Reset, Enable, sigs[i], sigs[i+1]))

     return blocks

Jan

> 
> For a reference to others I send my little sample application, modified.
> 
> Thanks
> 
> <code>
> from myhdl import *
> 
> def TestFunc(Clk, Reset, Enable, DataIn, DataOut):
>    
>     @always(Clk.posedge, Reset.posedge)
>     def functionality():
>         if Reset:
>             DataOut.next = 0
>         elif Enable:
>             DataOut.next = DataIn
> 
>     return functionality
> 
> def TestFixed(Clk, Reset, Enable, DataIn, DataOut, Size=3):
>     #Size not used in fixed implementation (fixed to 3)
> 
>     Out0 = Signal(bool(0))
>     Out1 = Signal(bool(0))
>     Out2 = Signal(bool(0))
>     In0 = Signal(bool(0))
>     In1 = Signal(bool(0))
>     In2 = Signal(bool(0))
> 
>     @always_comb
>     def Connect():
>         In0.next = DataIn
>         In1.next = Out0
>         In2.next = Out1
>         DataOut.next = Out2
> 
>     blocks = []
>     blocks.append(TestFunc(Clk, Reset, Enable, In0, Out0))
>     blocks.append(TestFunc(Clk, Reset, Enable, In1, Out1))
>     blocks.append(TestFunc(Clk, Reset, Enable, In2, Out2))
>    
>     return Connect, blocks
> 
> def Connect(In, Out):
>     @always_comb
>     def connect():
>         Out.next = In
>     return connect
> 
> def TestGeneric(Clk, Reset, Enable, DataIn, DataOut, Size=3):
> 
>     Out = [Signal(bool(0)) for i in range(Size)]
>     In  = [Signal(bool(0)) for i in range(Size)]
>         
>     connect = []
>     connect.append(Connect(DataIn, In[0]))
>     for k in range(1,Size):
>         connect.append(Connect(Out[k-1], In[k]))
>     connect.append(Connect(Out[Size-1], DataOut))
>   
>     blocks = []
>     for i in range(Size):
>         blocks.append(TestFunc(Clk, Reset, Enable, In[i], Out[i]))
> 
>     return connect, blocks
> 
> 
> def convert_TestFunc():
>     """Verify testfunc conversion"""
>     Clk     = Signal(bool(0))        
>     Reset   = Signal(bool(0))        
>     Enable  = Signal(bool(0))        
>     DataIn  = Signal(bool(0))
>     DataOut = Signal(bool(0))
>     toVerilog(TestFunc, Clk, Reset, Enable, DataIn, DataOut)
> 
> def convert_TestFixed():
>     Clk     = Signal(bool(0))        
>     Reset   = Signal(bool(0))        
>     Enable  = Signal(bool(0))        
>     DataIn  = Signal(bool(0))
>     DataOut = Signal(bool(0))
>     toVerilog(TestFixed, Clk, Reset, Enable, DataIn, DataOut)
> 
> def convert_TestGeneric():
>     Clk     = Signal(bool(0))        
>     Reset   = Signal(bool(0))        
>     Enable  = Signal(bool(0))        
>     DataIn  = Signal(bool(0))
>     DataOut = Signal(bool(0))
>     toVerilog(TestGeneric, Clk, Reset, Enable, DataIn, DataOut)
> 
> 
> if __name__ == '__main__':
>     convert_TestFunc()
>     convert_TestFixed()
>     convert_TestGeneric()
> 
> </code>
> 
> 
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