Re: [myhdl-list] List of Signals

[Christopher L. F. <cf...@uc...>]

As a rule for MyHDL you can't use the list syntax inside the behavior  
descriptions, if it is going to be converted to Verilog/VHDL.

>
>    @always_comb
>    def Connect():
>        In[0].next = DataIn
>        for k in range(1,Size):
>            In[k].next=Out[k-1]
>        DataOut.next=Out[Size-1]

The easiest most straight forward way to change it would be to change  
the above always_comb to a separate module that does the combinatorial  
logic for the assignments within the for loop, then make another list  
of instances for that logic, as such.

	def shiftOne(In, Out):
		@always_comb
		def Connect():
			Out.next = In
		return Connect

In TestGeneric, something like follows.
	
	....
	shift_inst = [None for i in range(N)]

	# This will create one shift register
	for i in range(1, Size):
		shift_inst[i] = shiftOne(In[i], Out[i-1])

	...

 From the above hopefully that is enough of an example (example is  
incomplete) to get the idea.

There are other posts in this mail group and solutions as well.  May  
also want to look at the manual, array of instances, the syntax in the  
manual probably safer for generating Verilog.

Hope that helps

On Feb 18, 2008, at 3:36 AM, sv...@te... wrote:

> I want to create a verilog module with a configurable number of  
> instances connected output to intput of the next (like registers in  
> a shift register).
>
> I ran in the "List contains Signals that are not unique to it: In"  
> error, because I defined a list of signals for the inputs and  
> outputs of the instances.
>
> Does someone has an idea how I can solve this?
>
> Included a trivial test module that (indeed) should generate a shift  
> register.
>
> Remark, I know how to do shift registers, this is only to show the  
> problem.
>
> <code>
> from myhdl import *
> from svhb_utils import *
>
> from numpy import *
>
> def TestFunc(Clk, Reset, Enable, DataIn, DataOut):
>
>    @always(Clk.posedge, Reset.posedge)
>    def functionality():
>        if Reset:
>            DataOut.next = 0
>        elif Enable:
>            DataOut.next = DataIn
>
>    return functionality
>
> def TestFixed(Clk, Reset, Enable, DataIn, DataOut, Size=3):
>    #Size not used in fixed implementation (fixed to 3)
>
>    Out0 = Signal(bool(0))
>    Out1 = Signal(bool(0))
>    Out2 = Signal(bool(0))
>    In0 = Signal(bool(0))
>    In1 = Signal(bool(0))
>    In2 = Signal(bool(0))
>
>    @always_comb
>    def Connect():
>        In0.next = DataIn
>        In1.next = Out0
>        In2.next = Out1
>        DataOut.next = Out2
>
>    blocks = []
>    blocks.append(TestFunc(Clk, Reset, Enable, In0, Out0))
>    blocks.append(TestFunc(Clk, Reset, Enable, In1, Out1))
>    blocks.append(TestFunc(Clk, Reset, Enable, In2, Out2))
>
>    return Connect, blocks
>
> def TestGeneric(Clk, Reset, Enable, DataIn, DataOut, Size=3):
>
>    Out = [Signal(bool(0)) for i in range(Size)]
>    In  = [Signal(bool(0)) for i in range(Size)]
>
>    @always_comb
>    def Connect():
>        In[0].next = DataIn
>        for k in range(1,Size):
>            In[k].next=Out[k-1]
>        DataOut.next=Out[Size-1]
>
>    blocks = []
>    for i in range(Size):
>        blocks.append(TestFunc(Clk, Reset, Enable, In[i], Out[i]))
>
>    return Connect, blocks
>
>
> def convert_TestFunc():
>    """Verify testfunc conversion"""
>    Clk     = Signal(bool(0))
>    Reset   = Signal(bool(0))
>    Enable  = Signal(bool(0))
>    DataIn  = Signal(bool(0))
>    DataOut = Signal(bool(0))
>    toVerilog(TestFunc, Clk, Reset, Enable, DataIn, DataOut)
>
> def convert_TestFixed():
>    Clk     = Signal(bool(0))
>    Reset   = Signal(bool(0))
>    Enable  = Signal(bool(0))
>    DataIn  = Signal(bool(0))
>    DataOut = Signal(bool(0))
>    toVerilog(TestFixed, Clk, Reset, Enable, DataIn, DataOut)
>
> def convert_TestGeneric():
>    Clk     = Signal(bool(0))
>    Reset   = Signal(bool(0))
>    Enable  = Signal(bool(0))
>    DataIn  = Signal(bool(0))
>    DataOut = Signal(bool(0))
>    toVerilog(TestGeneric, Clk, Reset, Enable, DataIn, DataOut)
>
>
> if __name__ == '__main__':
>    convert_TestFunc()
>    convert_TestFixed()
>    convert_TestGeneric()
>
> </code>
>
> Stefaan
>
>
>
>
>
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