Re: [myhdl-list] newb question

[Jan D. <ja...@ja...>]

Christopher L. Felton wrote:

> For this test, most people would not simulate this design this way.   
> The design has a simple state machine
> that controls the inputs to a bank of pwm's (controls the duty  
> cycle).  But the state machine goes to the next
> state on the order of 100ms real-time.  But since the simulation has  
> little logic and the logic switches minimally
> it seemed like a good test to profile the MyHDL simulation execution
> (most the time spent in the simulation code and not the logic code).

This seems to imply that more "typical" code (e.g. with more logic
inside generators) could have a relatively larger intbv overhead,
and therefore more to gain from intbv optimization.

I'll see if I can do a profiling check on my recent designs.

Jan

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