Re: [myhdl-list] newb question

[Jan D. <ja...@ja...>]

Thomas Heller wrote:

> IIUC, this means that modelsim is (only) a factor of ~5 faster?

I have some relevant data from a recent project. With the newest
MyHDL (development version) I can convert a test plan suited
to run under py.test to an equivalent test plan in VHDL and
in Verilog (significant coding restrictions apply, as always).

So it becomes easy to compare run times. The result for the
project were as follows:

MyHDL                        281s
modelsim VHDL RTL             21s
modelsim Verilog, gate level  41s

So VHDL RTL ran 13.4 times faster, Verilog gate level 6.9 times
faster for this project.

Jan

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