Re: [myhdl-list] newb question

[Thomas H. <th...@ct...>]

Christopher L. Felton schrieb:
> I don't have an exact number because Modelsim doesn't dump the time  
> running when it is complete.
> This particular simulation was setup to run for 4 seconds simulation  
> time with a 100ns simulation step.
> My guesstimate was that Modelsim took between 2hrs - 3hrs because  
> Modeslsim took 15-20 minutes
> to simulate 500ms.

IIUC, this means that modelsim is (only) a factor of ~5 faster?

> For this test, most people would not simulate this design this way.   
> The design has a simple state machine
> that controls the inputs to a bank of pwm's (controls the duty  
> cycle).  But the state machine goes to the next
> state on the order of 100ms real-time.  But since the simulation has  
> little logic and the logic switches minimally
> it seemed like a good test to profile the MyHDL simulation execution
> (most the time spent in the simulation code and not the logic code).
> 
> Also, I should be a little careful because I have not verified the  
> generated Verilog is 100% logically equivalent to
> the MyHDL logic.  I have only spot checked this with the waveform  
> outputs.

Well, we all know what benchmakrs tell us ;-)

Thomas