Re: [myhdl-list] newb question

[Christopher L. F. <cf...@uc...>]

I don't have an exact number because Modelsim doesn't dump the time  
running when it is complete.
This particular simulation was setup to run for 4 seconds simulation  
time with a 100ns simulation step.
My guesstimate was that Modelsim took between 2hrs - 3hrs because  
Modeslsim took 15-20 minutes
to simulate 500ms.

For this test, most people would not simulate this design this way.   
The design has a simple state machine
that controls the inputs to a bank of pwm's (controls the duty  
cycle).  But the state machine goes to the next
state on the order of 100ms real-time.  But since the simulation has  
little logic and the logic switches minimally
it seemed like a good test to profile the MyHDL simulation execution
(most the time spent in the simulation code and not the logic code).

Also, I should be a little careful because I have not verified the  
generated Verilog is 100% logically equivalent to
the MyHDL logic.  I have only spot checked this with the waveform  
outputs.

On Feb 8, 2008, at 11:24 AM, Thomas Heller wrote:

> Christopher L. Felton schrieb:
>> Couple more comments on this topic.
>>
>> One issue if the simulation were to be enhanced by C functions (no
>> need for C++) the build and distribution would become much more work
>> to build and build for the various platforms.
>>
>> But with that said, there have been posts that the simulation speed
>> in some cases seem a bit slow.  I used the python tool cProfile to
>> capture some information on a simulation.
>>
>> The following was a simulation that wasn't horribly efficient as
>> simulations go. The logic included some pwm's and other slowly
>> changing signals.  There were many clock cycles per event (many
>> simulation steps).  But to keep everything relative I had to keep the
>> ratio high (many clk/sim step per event).  The good thing is that
>> because it was a long simulation most of the cProfile errors should
>> of averaged out (this is my first experience with the python profile
>> tools).
>>
>> The MyHDL simulation took 50078.309 CPU seconds (~13 hours) where the
>> converted Verilog with same testbench (same timescale, etc) ran on
>> Modelsim was much shorter.
>>
>
> How long did it take in Modelsim?  Just curious;-)
>
> Thomas
>
>
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