Re: [myhdl-list] newb question

[Thomas H. <th...@ct...>]

Christopher L. Felton schrieb:
> Couple more comments on this topic.
> 
> One issue if the simulation were to be enhanced by C functions (no
> need for C++) the build and distribution would become much more work
> to build and build for the various platforms.
> 
> But with that said, there have been posts that the simulation speed
> in some cases seem a bit slow.  I used the python tool cProfile to
> capture some information on a simulation.
> 
> The following was a simulation that wasn't horribly efficient as
> simulations go. The logic included some pwm's and other slowly
> changing signals.  There were many clock cycles per event (many
> simulation steps).  But to keep everything relative I had to keep the
> ratio high (many clk/sim step per event).  The good thing is that
> because it was a long simulation most of the cProfile errors should
> of averaged out (this is my first experience with the python profile
> tools).
> 
> The MyHDL simulation took 50078.309 CPU seconds (~13 hours) where the
> converted Verilog with same testbench (same timescale, etc) ran on
> Modelsim was much shorter.
> 

How long did it take in Modelsim?  Just curious;-)

Thomas