[myhdl-list] Test bench conversion methodology

[Jan D. <ja...@ja...>]

Hi:

In a recent design project, verification was done as follows.

* I used py.test instead of unittest. In this way I can write
testbenches simply using 'assert' statements.

* When the design was verified, I converted it to VHDL for
synthesis.

* The synthesis result is a Verilog net list.

* For regression test purposes, I picked a few relevant test
benches and converted them to Verilog and VHDL.


So in the end I have a regression test plan in MyHDL, an
equivalent one in VHDL (to check the convertor) and an
equivalent one in Verilog (to check synthesis and backend
transformation such as atpg and layout).

This works like a charm, and I can do this all without relying
on cosimulation - just standalone simulators in MyHDL, Verilog
and VHDL.

Some details:

* I had to enhance the convertor, e.g. to convert assert statements.

* The top-level design has __vhdl__ and __verilog__ directives that
can be enabled under parameter control, and that hold a top-level
instantiation. This is used to prevent the convertor from converting
the design during test bench conversion. In this way, the conversion
of the design and the test benches are decoupled, as desired.

* The regression tests have to be written in a way to enable conversion.
I had to rewrite some of the original models to make this possible.


If you compare the above with what I have been announcing for
MyHDL 0.6, my conclusion is that I have on the wrong track:

* I emphasized print statements and support for all kinds of
format conversions.

* I introduced "conversion.verify" as a wrapper to check converted
code.

I now think I was trying to be way too clever. For example, I was
trying to emulate format width specifiers, while a language like
Verilog doesn't even have these natively. Also, the "conversion.verify"
wrapper is useful for me to debug the convertor, but it would be
useless in the real-life methodology outlined above.

So I want to back-track as follows for 0.6:

* emphasize assert statement conversion over print conversion
* stop worrying about format width specifier support - support
"%s" and "%d" and that's it
* remove "conversion.verify" from the documentation. It won't be
useful for a broad public - instead people will find out ways
to do their verification based on their needs and what MyHDL
supports, as I did.

So, unless someone gives good arguments to the contrary, that
is the path I'd like to follow.

Jan

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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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