Re: [myhdl-list] bit slicing

[Jon C. <jo...@ho...>]

Fundamentally, I agree that you should keep myhdl as minimal as possible an=
d leverage pure Python as much as possible.  As far as a converter is conce=
rned, I=0A=
suppose that people can do what I'm attempting which is to write a=0A=
crude script to convert Verilog to myhdl. I think in the future I will=0A=
probably have to put some comments in my Verilog code to make the=0A=
process easier.=20
=0A=
=0A=
As far as co-simulation is concerned, I would prefer not to go down that ro=
ute as I want as much of the simulation in Python as possible to give me mo=
re flexibility for analysis, etc.


> To: myh...@li...
> From: ja...@ja...
> Date: Sat, 26 Jan 2008 22:08:03 +0100
> Subject: Re: [myhdl-list] bit slicing
>=20
> Jon Choy wrote:
> > =20
> >  Jan,
> > =20
> >   I apologize for submitting to the bug tracker instead of discussion=20
> > list and I missed some details in the bit slicing. It does make=20
> > conversion of Verilog to myhdl a little bit cumbersome.
>=20
> Ok. MyHDL slicing is done like that to stay in line with the Python
> convention that the high index is excluded. (However, unlike typical
> Python slices, the high index is the *left* index in MyHDL, to stay
> in line with common hardware conventions.)
>=20
> It may sometimes be confusing, I agree. On the other hand, you may
> appreciate the fact that [m:] indicates an m-bit bus, and that
> slice [m:n] has m-n bits.
>=20
>  > Is it true that
> > you plan to support bidirectional conversion? What I mean by=20
> > bidirectional conversion means converting myhdl to Verilog and vice=20
> > versa.
>=20
> No, I have no plans in that direction. Seems like a daunting and frustrat=
ing
> task. Note that when I start from MyHDL, I start from a minimalistic
> language with all tools at hand (the Python compiler package). In the
> opposite direction it would be the opposite ...
>=20
>  > This would enable me to use legacy code and/or old Verilog
> > behavioral models.  I assume that others would be interested in trying=
=20
> > to import their old code to myhdl.
>=20
> Perhaps a more general co-simulation approach could address this where
> you embed an arbitrary number of Verilog simulators in a MyHDL design.
> (Currently cosimulation is limited to a single cosimulation object).
> No idea how feasible that is, though.
>=20
> Jan
>=20
> --=20
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Kaboutermansstraat 97, B-3000 Leuven, Belgium
>      From Python to silicon:
>      http://myhdl.jandecaluwe.com
>=20
>=20
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