Re: [myhdl-list] bit slicing

[Jan D. <ja...@ja...>]

Jon Choy wrote:
>  
>  Jan,
>  
>   I apologize for submitting to the bug tracker instead of discussion 
> list and I missed some details in the bit slicing. It does make 
> conversion of Verilog to myhdl a little bit cumbersome.

Ok. MyHDL slicing is done like that to stay in line with the Python
convention that the high index is excluded. (However, unlike typical
Python slices, the high index is the *left* index in MyHDL, to stay
in line with common hardware conventions.)

It may sometimes be confusing, I agree. On the other hand, you may
appreciate the fact that [m:] indicates an m-bit bus, and that
slice [m:n] has m-n bits.

 > Is it true that
> you plan to support bidirectional conversion? What I mean by 
> bidirectional conversion means converting myhdl to Verilog and vice 
> versa.

No, I have no plans in that direction. Seems like a daunting and frustrating
task. Note that when I start from MyHDL, I start from a minimalistic
language with all tools at hand (the Python compiler package). In the
opposite direction it would be the opposite ...

 > This would enable me to use legacy code and/or old Verilog
> behavioral models.  I assume that others would be interested in trying 
> to import their old code to myhdl.

Perhaps a more general co-simulation approach could address this where
you embed an arbitrary number of Verilog simulators in a MyHDL design.
(Currently cosimulation is limited to a single cosimulation object).
No idea how feasible that is, though.

Jan

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