[myhdl-list] bit slicing

[Jon C. <jo...@ho...>]

  Jan,
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  I apologize for submitting to the bug tracker instead of discussion list =
and I missed some details in the bit slicing. It does make conversion of Ve=
rilog to myhdl a little bit cumbersome. Is it true that you plan to support=
 bidirectional conversion? What I mean by bidirectional conversion means co=
nverting myhdl to Verilog and vice versa.  This would enable me to use lega=
cy code and/or old Verilog behavioral models.  I assume that others would b=
e interested in trying to import their old code to myhdl.
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  Jon
  =20
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---------------------------------------------------------------------->Comm=
ent By: Jan Decaluwe (jandecaluwe)Date: 2008-01-24 14:04Message:Logged In: =
YES user_id=3D144795Originator: NOI think you're confused about how slicing=
 works in MyHDL (and Python).Have you read this:   http://www.jandecaluwe.c=
om/Tools/MyHDL/manual/intro-slicing.htmlIssues like this are better discuss=
ed on the mailing list/newsgroup first.------------------------------------=
----------------------------------   Submitted By: h2opolo (h2opolo)Assigne=
d to: Nobody/Anonymous (nobody)Summary: concat and intbvInitial Comment:I'm=
 fairly new to myhdl; but I've been using many mixed signal design tools fo=
r years. I use tools like ncverilog, vcs, etc. Myhdl looks very promising f=
or mixed signal design. Anyway, I noticed that when I try to specify a bit =
width and assign it a value it seems like I have to use an additional bit. =
For example, if I try to do the following:  a =3D intbv(2)[2:]  It does not=
 like it and I end up having to add additional bit (e.g. a =3D intbv(2)[3:]=
 ). When converting Verilog code to Python, there are occasions where I hav=
e to concatenate signals like the following example:    b =3D {4'b1011,a[1:=
0]} and in this case I would create a 6 bit bus. It seems like I have to ad=
d a bit or I don't get the correct value. It almost seems like the upper bi=
t gets chopped off. It doesn't look like this was fixed for the 0.6 develop=
ment version. Is there a reason for this? Like dealing with signed integers=
 or something. It makes conversion to and from Verilog a little cumbersome.=
  JonYou can respond by visiting: https://sourceforge.net/tracker/?func=3Dd=
etail&atid=3D596332&aid=3D1878630&group_id=3D91207
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