[myhdl-list] 0.6dev6

[Jan D. <ja...@ja...>]

Hello all - happy new year!

I have put development version 0.6dev6 on the web site:

    http://myhdl.jandecaluwe.com/doku.php/dev:snapshots#snapshots

This should be quite a strong release, because it is the version
that I have just used for a "real" design project as a consultant,
targetting both Verilog and VHDL.

There are many improvements, both in simulation and conversion to
Verilog. Moreover, conversion to VHDL should now be as strong as
conversion to Verilog. The improvements were all triggered by
real-life usage in the project. Backward compatibility should
be close to perfect.

What is lacking is documentation, and of course fixing of some
open ends.

I have documented some fixed bugs on SourceForge (opened and closed again),
but I have many more things to document about features and methodology.
I hope to do that here and on the site in the weeks ahead - I will
not take new consultancy projects until March (but from then on,
feel free to consider me ;-)).

Best regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com