#8 verilog-ams compile error

[Anonymous]

I have tried adms, but found it compiles
dac.va error.

[Nobody/Anonymous]

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my email is fxsjx@yahoo.com

Thanks,

Regards,

Charlie Sun

[Laurent Lemaitre]

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user_id=809289

Hi Charlie,

I need more info. Did you try to compile
a file called dac.va? Can I get a copy of the file - if possible?
Note that adms does not support all the va constructs
as described by file SYNTAX-SUPPORTED
(see http://sourceforge.net/project/showfiles.php?
group_id=84289&package_id=126769.)

Laurent

[Charly Sun]

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user_id=1051669

Hi, Laurent I am sorry that I have forgotten.
Then I paste the file here:

`define dac_size 4
`define adc_size 4

`ifdef insideADMS
`else
`include "constants.h"
`include "discipline.h"
`endif // insideADMS

module ideal_dac(in,out);
input [0:`dac_size-1] in;
output out;
voltage in,out;
parameter vth = 2.5;
parameter real trise = 0 from [0:inf);
parameter real tfall = 0 from [0:inf);

real code;
integer pow2 [0:`dac_size];
real c0,c1,c2,c3;
integer j;
genvar i;

analog begin

@(initial_step) begin
for (j=0;j<=`dac_size;j=j+1)
pow2[j] = pow(2,j);
end

code = 0;
for (i=0;i<`dac_size;i=i+1)
code = code + ((V(in[i]) > vth) ?
pow2[i] : 0);

V(out) <+
transition(code/pow2[`dac_size],0,trise,tfall);

end
endmodule

module ideal_adc(in,clk,out);
input in,clk;
output [0:`adc_size-1] out;
voltage in,clk,out;

parameter real fullscale = 1.0;
parameter real delay_ = 0, trise = 10n,
tfall = 10n;
parameter real clk_vth = 2.5;
parameter real out_high = 1, out_low = 0
from (-inf:out_high);

real sample,thresh;
real result[0:`adc_size-1];
genvar i;

analog begin

@(cross(V(clk)-clk_vth, +1)) begin
sample = V(in);
thresh = fullscale/2;
for(i=`adc_size-1;i>=0;i=i-1)
begin
if (sample > thresh) begin
result[i] = out_high;
sample = sample - thresh;
end
else
result[i] = out_low;
sample = 2*sample;
end
end

for(i=`adc_size-1;i>=0;i=i-1)
V(out[i]) <+
transition(result[i],delay_,trise,tfall);

end
endmodule

[Charly Sun]

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user_id=1051669

`define dac_size 4
`define adc_size 4

`ifdef insideADMS
`else
`include "constants.h"
`include "discipline.h"
`endif // insideADMS

module ideal_dac(in,out);
input [0:`dac_size-1] in;
output out;
voltage in,out;
parameter vth = 2.5;
parameter real trise = 0 from [0:inf);
parameter real tfall = 0 from [0:inf);

real code;
integer pow2 [0:`dac_size];
real c0,c1,c2,c3;
integer j;
genvar i;

analog begin

@(initial_step) begin
for (j=0;j<=`dac_size;j=j+1)
pow2[j] = pow(2,j);
end

code = 0;
for (i=0;i<`dac_size;i=i+1)
code = code + ((V(in[i]) > vth) ?
pow2[i] : 0);

V(out) <+
transition(code/pow2[`dac_size],0,trise,tfall);

end
endmodule

module ideal_adc(in,clk,out);
input in,clk;
output [0:`adc_size-1] out;
voltage in,clk,out;

parameter real fullscale = 1.0;
parameter real delay_ = 0, trise = 10n,
tfall = 10n;
parameter real clk_vth = 2.5;
parameter real out_high = 1, out_low = 0
from (-inf:out_high);

real sample,thresh;
real result[0:`adc_size-1];
genvar i;

analog begin

@(cross(V(clk)-clk_vth, +1)) begin
sample = V(in);
thresh = fullscale/2;
for(i=`adc_size-1;i>=0;i=i-1)
begin
if (sample > thresh) begin
result[i] = out_high;
sample = sample - thresh;
end
else
result[i] = out_low;
sample = 2*sample;
end
end

for(i=`adc_size-1;i>=0;i=i-1)
V(out[i]) <+
transition(result[i],delay_,trise,tfall);

end
endmodule

[Laurent Lemaitre]

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user_id=809289

Hi Charlie,
The syntax used by your model is not currently supported
by adms (see SYNTAX-SUPPORTED file).
adms has been built to implement primarily
compact device models.
However I will add your example to the target list of examples
that should be covered by future releases of adms.
I will warn you when adms
will be able to handle your example. (possibly mid-August).
Laurent

[Nobody/Anonymous]

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Thanks :)

Regards,

Charlie Sun