[LTP] [PATCH 2/3] 64-bit rdtscll macro for powerpc64

[Gilles C. <gil...@bu...>]

From: gilles.carry <gilles.carry>

This macro reads atomically the 64-bit TSC register.
Reading the 64-bit register using two 32-bit instructions sometimes
causes wrapping when a clock update appears in between.
A single 64-bit read fixes this.

Signed-off-by: Gilles Carry <gil...@bu...>
Cc: Tim Chavez <ti...@us...>

---
 testcases/realtime/include/librttest.h |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/testcases/realtime/include/librttest.h b/testcases/realtime/include/librttest.h
index 8f1b362..b56f81e 100644
--- a/testcases/realtime/include/librttest.h
+++ b/testcases/realtime/include/librttest.h
@@ -107,7 +107,13 @@ typedef struct { volatile int counter; } atomic_t;
 		__asm__ __volatile__ ("rdtsc" : "=a" (low), "=d" (high)); \
 		val = (uint64_t)high << 32 | low;	\
 	} while(0)
-#elif defined(__powerpc__)	/* 32bit version */
+#elif defined(__powerpc__)
+#if defined(__powerpc64__)	/* 64bit version */
+#define rdtscll(val)					\
+	do {								\
+		__asm__ __volatile__ ("mfspr %0, 268" : "=r" (val));	\
+	} while(0)
+#else	/*__powerpc__ 32bit version */
 #define rdtscll(val)							\
 	 do {								\
 		uint32_t tbhi, tblo ;					\
@@ -115,6 +121,7 @@ typedef struct { volatile int counter; } atomic_t;
 		__asm__ __volatile__ ("mftbl %0" : "=r" (tblo));	\
 		val = 1000 * ((uint64_t) tbhi << 32) | tblo;		\
 	} while(0)
+#endif
 #else
 #error
 #endif
-- 
1.5.5.GIT