Re: [Lse-tech] Dbench scalability results on 2.4.0

[<ma...@ve...>]

On Wed, 4 Jul 2001, Ingo Molnar wrote:
> a perhaps better solution on x86 is to make the TLB IPI handler an NMI
> interrupt. This solution is ideal: the only overhead would be the IPI
> latency, no waiting on the target CPU.

Ingo,

  Is that race free?

  John was reporting scalability problems with flush_tlb_range(), which
uses (on IA32 - John was IA64) "flush_mm" and the tlbstate_lock.  Doesn't
feel safe if using the NMI...

Mark