[linuxsh-dev] Re: [linux-sh:01494] SH7751 Solutions Engine

[NIIBE Y. <gn...@m1...>]

yos...@hi... wrote:
 > Here is the register map for MS7751SE01. / yoshii
 > 
 > /*
 > Address	Name	Initial-val
 > 	[bit]	Signal
 > 	...
 > */
 > 
 > h'1b000000	ILCRA	h'FEBA
 > 	[15:12]	~SLOT_IRQ8
 > 	[11:8]	~SLOT_IRQ7
 > 	[7:4]	~SLOT_IRQ6
 > 	[3:0]	~SLOT_IRQ5

I have to say that this is bad design.  It seems that hardware
designer just thinks that "supporting interrupt priority".  This works
well on limited use, but doesn't scale (in terms of number of kinds of
interrupts) well, and not general enough.  Think about the case: we
have more than fifteen kinds of interrupt sources.

Supporting interrupt priority in hardware is not important.  Most
important thing is to distinguish the souce of interrupts and the
feature of masking the interrupt souce independently.  The design
would be:
   Supports up to 32 interrupt sources

	Interrupt source register
		31..0

	Interrupt mask register
		31..0

   Output:
    INT_OUT = (INT_31 & INT_MASK_31) | (INT_30 & INT_MASK_30)
	        | ... | (INT_0 & INT_MASK_0)

If we have this mechanism, we easily can emulate the "interrupt
priority" scheme.  For example, if we need to stop handling INT3..INT0
while handling INT4, just mask INT4..INT0 while getting INT4.  And
it's more, we can implement other scheme.

In short:
	Supporting interrupt priority in hardware is useless.
	Do support generic one in hardware, software is more
	suitable to implement good scheme.
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