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From: Toshiharu N. <no...@hi...> - 2000-06-07 06:47:06
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I made enabler of the ATA card which I used the PC card
slot on Solution Engine for.
IDE through SuperI/O becomes a storage usable immediately
when I select Solution Engine in Sytem type.
However, I was able to use an ATA card as a storage
because it was not the person who had extension connector.
It works with Solution Engine of SH4.
I want please to hear an opinion of all.
diff -ruN linux-2.4.0-test1/arch/sh/config.in linux-sh/arch/sh/config.in
--- linux-2.4.0-test1/arch/sh/config.in Sun May 21 04:05:29 2000
+++ linux-sh/arch/sh/config.in Wed Jun 7 01:13:01 2000
@@ -61,9 +61,9 @@
bool 'Networking support' CONFIG_NET
-if [ "$CONFIG_SH_SOLUTION_ENGINE" != "y" ]; then
+#if [ "$CONFIG_SH_SOLUTION_ENGINE" != "y" ]; then
bool 'Directly Connected Compact Flash support' CONFIG_CF_ENABLER
-fi
+#fi
bool 'PCI support' CONFIG_PCI
if [ "$CONFIG_PCI" = "y" ]; then
diff -ruN linux-2.4.0-test1/arch/sh/kernel/cf-enabler.c
linux-sh/arch/sh/kernel/cf-enabler.c
--- linux-2.4.0-test1/arch/sh/kernel/cf-enabler.c Mon Mar 6 02:33:55
2000
+++ linux-sh/arch/sh/kernel/cf-enabler.c Wed Jun 7 12:22:14 2000
@@ -12,13 +12,62 @@
#include <asm/io.h>
#include <asm/irq.h>
+#ifdef CONFIG_SH_SOLUTION_ENGINE
+#include <asm/hitachi_se.h>
+/*
+ * 0xB8400000 : Common Memory
+ * 0xB8500000 : Attribute
+ * 0xB8600000 : I/O
+ */
+int __init cf_init(void)
+{
+ if((ctrl_inw(MRSHPC_CSR) & 0x000c) == 0){/* if card detect is true */
+ if((ctrl_inw(MRSHPC_CSR) & 0x0080) == 0){
+ ctrl_outw(0x0674, MRSHPC_CPWCR);/* Card Vcc is 3.3v? */
+ }
+ else{
+ ctrl_outw(0x0678, MRSHPC_CPWCR);/* Card Vcc is 5V */
+ }
+ /*wait(10000);*//* 10ms wait */
+ }
+ else{
+ return 0;
+ }
+/*
+ PC-Card window open
+ flag == COMMON/ATTRIBUTE/IO
+*/
+ /* common window open */
+ ctrl_outw(0x8a84, MRSHPC_MW0CR1);/* window 0xb8400000 */
+ if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
+ ctrl_outw(0x0b00, MRSHPC_MW0CR2);/* common mode & bus width 16bit
SWAP = 1*/
+ else
+ ctrl_outw(0x0300, MRSHPC_MW0CR2);/* common mode & bus width 16bit
SWAP = 0*/
+ /* attribute window open */
+ ctrl_outw(0x8a85, MRSHPC_MW1CR1);/* window 0xb8500000 */
+ if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
+ ctrl_outw(0x0a00, MRSHPC_MW1CR2);/* attribute mode & bus width 16bit
SWAP = 1*/
+ else
+ ctrl_outw(0x0200, MRSHPC_MW1CR2);/* attribute mode & bus width 16bit
SWAP = 0*/
+ /* I/O window open */
+ ctrl_outw(0x8a86, MRSHPC_IOWCR1);/* I/O window 0xb8600000 */
+ ctrl_outw(0x0008, MRSHPC_CDCR); /* I/O card mode */
+ if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
+ ctrl_outw(0x0a00, MRSHPC_IOWCR2);/* bus width 16bit SWAP = 1*/
+ else
+ ctrl_outw(0x0200, MRSHPC_IOWCR2);/* bus width 16bit SWAP = 0*/
+ ctrl_outw(0x2000, MRSHPC_ICR);
+ ctrl_outb(0x00, PA_MRSHPC_MW2 + 0x206);
+ ctrl_outb(0x42, PA_MRSHPC_MW2 + 0x200);
+ return 0;
+}
+#else /* then generic system type */
#define CF_CIS_BASE 0xb8000000
/*
* 0xB8000000 : Attribute
* 0xB8001000 : Common Memory
* 0xBA000000 : I/O
*/
-
int __init cf_init(void)
{
outw(0x0042, CF_CIS_BASE+0x0200);
@@ -26,5 +75,5 @@
disable_irq(14);
return 0;
}
-
+#endif
__initcall (cf_init);
diff -ruN linux-2.4.0-test1/arch/sh/kernel/io_se.c
linux-sh/arch/sh/kernel/io_se.c
--- linux-2.4.0-test1/arch/sh/kernel/io_se.c Mon May 22 12:55:06 2000
+++ linux-sh/arch/sh/kernel/io_se.c Wed Jun 7 12:55:33 2000
@@ -13,15 +13,16 @@
#include <asm/hitachi_se.h>
/* SH pcmcia io window base, start and end. */
-int sh_pcic_io_wbase = 0xb8400000;
-int sh_pcic_io_start;
-int sh_pcic_io_stop;
+int sh_pcic_io_wbase = 0xb8600000;
+int sh_pcic_io_start = 0x3000;
+int sh_pcic_io_stop = 0x3fff;
int sh_pcic_io_type;
int sh_pcic_io_dummy;
static inline void delay(void)
{
ctrl_inw(0xa0000000);
+ ctrl_inw(0xa0000000);
}
/* MS7750 requires special versions of in*, out* routines, since
@@ -31,12 +32,12 @@
static inline volatile __u16 *
port2adr(unsigned int port)
{
- if (port >= 0x2000)
+ if (port >= 0x3000)
+ return (volatile __u16 *) (PA_MRSHPC_IO + (port - 0x3000));
+ else if (port >= 0x2000)
return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
else if (port >= 0x1000)
return (volatile __u16 *) (PA_83902 + (port << 1));
- else if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
- return (volatile __u16 *) (sh_pcic_io_wbase + (port &~ 1));
else
return (volatile __u16 *) (PA_SUPERIO + (port << 1));
}
@@ -58,9 +59,9 @@
unsigned long inb(unsigned int port)
{
if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
- return *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port);
+ return *(__u8 *) port2adr(port);
else if (shifted_port(port))
- return (*port2adr(port) >> 8);
+ return (*port2adr(port) >> 8)&0xff;
else
return (*port2adr(port))&0xff;
}
@@ -70,9 +71,9 @@
unsigned long v;
if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
- v = *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port);
+ v = *(__u8 *) port2adr(port);
else if (shifted_port(port))
- v = (*port2adr(port) >> 8);
+ v = (*port2adr(port) >> 8)&0xff;
else
v = (*port2adr(port))&0xff;
delay();
@@ -98,7 +99,7 @@
void outb(unsigned long value, unsigned int port)
{
if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
- *(__u8 *)(sh_pcic_io_wbase + port) = value;
+ *(__u8 *)port2adr(port) = (__u8)value;
else if (shifted_port(port))
*(port2adr(port)) = value << 8;
else
@@ -108,7 +109,7 @@
void outb_p(unsigned long value, unsigned int port)
{
if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
- *(__u8 *)(sh_pcic_io_wbase + port) = value;
+ *(__u8 *)port2adr(port) = (__u8)value;
else if (shifted_port(port))
*(port2adr(port)) = value << 8;
else
@@ -135,14 +136,14 @@
volatile __u16 *p = port2adr(port);
if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) {
- volatile __u8 *bp = (__u8 *) (sh_pcic_io_wbase + 0x40000 + port);
+ volatile __u8 *bp = (__u8 *) port2adr(port);
while (count--)
*((__u8 *) addr)++ = *bp;
} else if (shifted_port(port)) {
- while (count--)
- *((__u8 *) addr)++ = *p >> 8;
+ while (count--)
+ *((__u8 *) addr)++ = (*p >> 8)&0xff;
} else {
- while (count--)
+ while (count--)
*((__u8 *) addr)++ = *p;
}
}
@@ -164,14 +165,14 @@
volatile __u16 *p = port2adr(port);
if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) {
- volatile __u8 *bp = (__u8 *) (sh_pcic_io_wbase + port);
+ volatile __u8 *bp = (__u8 *) port2adr(port);
while (count--)
*bp = *((__u8 *) addr)++;
} else if (shifted_port(port)) {
- while (count--)
+ while (count--)
*p = *((__u8 *) addr)++ << 8;
} else {
- while (count--)
+ while (count--)
*p = *((__u8 *) addr)++;
}
}
@@ -187,7 +188,7 @@
{
maybebadio(outsw, port);
}
-
+
/* Map ISA bus address to the real address. Only for PCMCIA. */
/* ISA page descriptor. */
diff -ruN linux-2.4.0-test1/include/asm-sh/hitachi_se.h
linux-sh/include/asm-sh/hitachi_se.h
--- linux-2.4.0-test1/include/asm-sh/hitachi_se.h Sun May 21 04:05:30
2000
+++ linux-sh/include/asm-sh/hitachi_se.h Wed Jun 7 12:11:43 2000
@@ -39,6 +39,22 @@
#define PA_BCR 0xb1400000 /* FPGA */
#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */
+#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
#define BCR_ILCRA (PA_BCR + 0)
#define BCR_ILCRB (PA_BCR + 2)
--
// Toshiharu Nozawa <no...@hi...> //
// HITACHI ULSI Systems Application Engneering Dept.//
|
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From: NIIBE Y. <gn...@ch...> - 2000-06-07 07:19:17
|
Toshiharu Nozawa wrote: > I made enabler of the ATA card which I used the PC card > slot on Solution Engine for. Nice work. Questions: (1) Does it work on other SolutionEngin(s)? SH7709? SH7709A? Here's comments. > --- linux-2.4.0-test1/arch/sh/config.in Sun May 21 04:05:29 2000 > +++ linux-sh/arch/sh/config.in Wed Jun 7 01:13:01 2000 > @@ -61,9 +61,9 @@ > > bool 'Networking support' CONFIG_NET > > -if [ "$CONFIG_SH_SOLUTION_ENGINE" != "y" ]; then > +#if [ "$CONFIG_SH_SOLUTION_ENGINE" != "y" ]; then > bool 'Directly Connected Compact Flash support' CONFIG_CF_ENABLER > -fi > +#fi > > bool 'PCI support' CONFIG_PCI > if [ "$CONFIG_PCI" = "y" ]; then We should change the explanation. For solution engine, it's nof "Directly Connected Compact Flash Support". I'd just use: "Compact Flash Enabler". > --- linux-2.4.0-test1/arch/sh/kernel/cf-enabler.c Mon Mar 6 02:33:55 > 2000 > +++ linux-sh/arch/sh/kernel/cf-enabler.c Wed Jun 7 12:22:14 2000 Will applied. > --- linux-2.4.0-test1/include/asm-sh/hitachi_se.h Sun May 21 04:05:30 > 2000 > +++ linux-sh/include/asm-sh/hitachi_se.h Wed Jun 7 12:11:43 2000 Ditto. These two are no problem. For the changes of following file: > --- linux-2.4.0-test1/arch/sh/kernel/io_se.c Mon May 22 12:55:06 2000 > +++ linux-sh/arch/sh/kernel/io_se.c Wed Jun 7 12:55:33 2000 I'd like to listen comment from Kaz. It seems there's some conflict on usage of sh_pcic_XXX semantics. -- |
|
From: kaz K. <kk...@rr...> - 2000-06-07 08:17:12
|
NIIBE Yutaka wrote:
>> --- linux-2.4.0-test1/arch/sh/kernel/io_se.c Mon May 22 12:55:06 2000
>> +++ linux-sh/arch/sh/kernel/io_se.c Wed Jun 7 12:55:33 2000
>
> I'd like to listen comment from Kaz. It seems there's some conflict
> on usage of sh_pcic_XXX semantics.
I think all changes by Nozawa-san are fine except
> unsigned long inb(unsigned int port)
> {
> if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
>- return *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port);
>+ return *(__u8 *) port2adr(port);
> else if (shifted_port(port))
MR-SHPC-01 chip has 1MB window which is constructed as the set of
four 256KB spaces. First 256KB space is "real word" space and the
second is "real byte" space. So the above change makes byte input
from the "real word" space. It seems not good in the i/o window
case since the access to this area has 16-bit sizing which will
cause problems on some PCMCIA cards. Of course, it might not cause
any problem on CF(ATA) cards, but I'd like to be defensive for such
chip :-)
kaz
|
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From: NIIBE Y. <gn...@ch...> - 2000-06-07 08:25:28
|
kaz Kojima writes:
> MR-SHPC-01 chip has 1MB window which is constructed as the set of
> four 256KB spaces. First 256KB space is "real word" space and the
> second is "real byte" space. So the above change makes byte input
> from the "real word" space. It seems not good in the i/o window
> case since the access to this area has 16-bit sizing which will
> cause problems on some PCMCIA cards. Of course, it might not cause
> any problem on CF(ATA) cards, but I'd like to be defensive for such
> chip :-)
Let's clarify things.
#1:
Is this correct?
> /* SH pcmcia io window base, start and end. */
> -int sh_pcic_io_wbase = 0xb8400000;
> -int sh_pcic_io_start;
> -int sh_pcic_io_stop;
> +int sh_pcic_io_wbase = 0xb8600000;
> +int sh_pcic_io_start = 0x3000;
> +int sh_pcic_io_stop = 0x3fff;
Specifically, io_wbase has been changed. Does not cause any problem?
#2:
> unsigned long inb(unsigned int port)
> {
> if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
>- return *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port);
>+ return *(__u8 *) port2adr(port);
> else if (shifted_port(port))
It seems that your comments above means we need this "0x400000" for
byte access of "read" (in). Is there any reason why we don't need
this "0x40000" for "write" (out)?
--
|
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From: kaz K. <kk...@rr...> - 2000-06-07 08:58:53
|
NIIBE Yutaka writes:
> Let's clarify things.
>
> #1:
> Is this correct?
>
> > /* SH pcmcia io window base, start and end. */
> > -int sh_pcic_io_wbase = 0xb8400000;
> > -int sh_pcic_io_start;
> > -int sh_pcic_io_stop;
> > +int sh_pcic_io_wbase = 0xb8600000;
> > +int sh_pcic_io_start = 0x3000;
> > +int sh_pcic_io_stop = 0x3fff;
>
> Specifically, io_wbase has been changed. Does not cause any problem?
The windows of MR-SHPC can be mapped every 1MB-aligned position
in area 6 (0xb8000000-0xbc000000). I'm not sure why Nozawa-san makes
this change, but anyway, it doesn't cause any problem.
I missed one point. Perhaps
> port2adr(unsigned int port)
> {
>- if (port >= 0x2000)
>+ if (port >= 0x3000)
>+ return (volatile __u16 *) (PA_MRSHPC_IO + (port - 0x3000));
causes problem by the magic number 0x3000. It's not bad to initialize
sh_pcic_io_start and sh_pcic_io_stop but they will cheaged by PCMCIA
driver like pcmcia-cs. Nozawa-san, you can't handle these variable
as constants.
> #2:
> > unsigned long inb(unsigned int port)
> > {
> > if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
> >- return *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port);
> >+ return *(__u8 *) port2adr(port);
> > else if (shifted_port(port))
>
> It seems that your comments above means we need this "0x400000" for
> byte access of "read" (in). Is there any reason why we don't need
> this "0x40000" for "write" (out)?
This chip is odd enough. These four 256KB spaces are exactly same in
write access.
kaz
|
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From: NIIBE Y. <gn...@ch...> - 2000-06-07 09:53:14
|
OK. I'll leave the changes of io_se.c to confirm the intention of
changes. At this stage, it seems for me that setting sh_pcic_XXX
variables would be better placed in cf-enabler.c.
Since he doesn't have CVS access, I'll commit following changes.
2000-06-07 Toshiharu Nozawa <no...@hi...>
Compact Flash Support for SolutionEngine.
* arch/sh/kernel/cf-enabler.c (cf_init): Implemented for
SolutionEngine.
* include/asm-sh/hitachi_se.h (PA_MRSHPC_*, MRSHPC_*): Added.
* arch/sh/config.in: SolutionEngine may use enabler.
2000-06-02 NIIBE Yutaka <gn...@m1...>
* arch/sh/kernel/entry.S (Throughout): Use ".align 2" instead
Index: arch/sh/config.in
===================================================================
RCS file: /cvsroot/linuxsh/kernel/arch/sh/config.in,v
retrieving revision 1.5
diff -u -r1.5 config.in
--- arch/sh/config.in 2000/05/04 06:32:44 1.5
+++ arch/sh/config.in 2000/06/07 09:41:53
@@ -61,8 +61,8 @@
bool 'Networking support' CONFIG_NET
-if [ "$CONFIG_SH_SOLUTION_ENGINE" != "y" ]; then
- bool 'Directly Connected Compact Flash support' CONFIG_CF_ENABLER
+if [ "$CONFIG_SH_GENERIC" = "y" -o "$CONFIG_SH_SOLUTION_ENGINE" = "y" ]; then
+ bool 'Compact Flash Enabler support' CONFIG_CF_ENABLER
fi
bool 'PCI support' CONFIG_PCI
Index: arch/sh/kernel/cf-enabler.c
===================================================================
RCS file: /cvsroot/linuxsh/kernel/arch/sh/kernel/cf-enabler.c,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 cf-enabler.c
--- arch/sh/kernel/cf-enabler.c 2000/04/14 16:49:01 1.1.1.1
+++ arch/sh/kernel/cf-enabler.c 2000/06/07 09:41:53
@@ -3,17 +3,79 @@
* linux/drivers/block/cf-enabler.c
*
* Copyright (C) 1999 Niibe Yutaka
+ * Copyright (C) 2000 Toshiharu Nozawa
*
* Enable the CF configuration.
*/
+#include <linux/config.h>
#include <linux/init.h>
#include <asm/io.h>
#include <asm/irq.h>
+#ifdef CONFIG_SH_SOLUTION_ENGINE
+#include <asm/hitachi_se.h>
+/*
+ * 0xB8400000 : Common Memory
+ * 0xB8500000 : Attribute
+ * 0xB8600000 : I/O
+ */
+
+int __init cf_init(void)
+{
+ if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0)
+ return 0; /* Not detected */
+
+ if ((ctrl_inw(MRSHPC_CSR) & 0x0080) == 0) {
+ ctrl_outw(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
+ } else {
+ ctrl_outw(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */
+ }
+
+ /*
+ * PC-Card window open
+ * flag == COMMON/ATTRIBUTE/IO
+ */
+ /* common window open */
+ ctrl_outw(0x8a84, MRSHPC_MW0CR1);/* window 0xb8400000 */
+ if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
+ /* common mode & bus width 16bit SWAP = 1*/
+ ctrl_outw(0x0b00, MRSHPC_MW0CR2);
+ else
+ /* common mode & bus width 16bit SWAP = 0*/
+ ctrl_outw(0x0300, MRSHPC_MW0CR2);
+
+ /* attribute window open */
+ ctrl_outw(0x8a85, MRSHPC_MW1CR1);/* window 0xb8500000 */
+ if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
+ /* attribute mode & bus width 16bit SWAP = 1*/
+ ctrl_outw(0x0a00, MRSHPC_MW1CR2);
+ else
+ /* attribute mode & bus width 16bit SWAP = 0*/
+ ctrl_outw(0x0200, MRSHPC_MW1CR2);
+
+ /* I/O window open */
+ ctrl_outw(0x8a86, MRSHPC_IOWCR1);/* I/O window 0xb8600000 */
+ ctrl_outw(0x0008, MRSHPC_CDCR); /* I/O card mode */
+ if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
+ ctrl_outw(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/
+ else
+ ctrl_outw(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/
+
+ ctrl_outw(0x2000, MRSHPC_ICR);
+ ctrl_outb(0x00, PA_MRSHPC_MW2 + 0x206);
+ ctrl_outb(0x42, PA_MRSHPC_MW2 + 0x200);
+ return 0;
+}
+#else /* then generic system type */
#define CF_CIS_BASE 0xb8000000
/*
+ * You can connect Compact Flash directly to the bus of SuperH.
+ * This is the enabler for that.
+ */
+
+/*
* 0xB8000000 : Attribute
* 0xB8001000 : Common Memory
* 0xBA000000 : I/O
@@ -21,10 +83,12 @@
int __init cf_init(void)
{
+ /* Enable the card, and set the level interrupt */
outw(0x0042, CF_CIS_BASE+0x0200);
make_imask_irq(14);
disable_irq(14);
return 0;
}
+#endif
__initcall (cf_init);
Index: arch/sh/kernel/io_se.c
===================================================================
RCS file: /cvsroot/linuxsh/kernel/arch/sh/kernel/io_se.c,v
retrieving revision 1.4
diff -u -r1.4 io_se.c
--- arch/sh/kernel/io_se.c 2000/05/07 23:31:58 1.4
+++ arch/sh/kernel/io_se.c 2000/06/07 09:41:53
@@ -7,7 +7,6 @@
* I/O routine for Hitachi SolutionEngine.
*
*/
-#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/types.h>
Index: arch/sh/kernel/irq.c
===================================================================
RCS file: /cvsroot/linuxsh/kernel/arch/sh/kernel/irq.c,v
retrieving revision 1.8
diff -u -r1.8 irq.c
--- arch/sh/kernel/irq.c 2000/05/14 08:41:25 1.8
+++ arch/sh/kernel/irq.c 2000/06/07 09:41:54
@@ -13,6 +13,7 @@
* Naturally it's not a 1:1 relation, but there are similarities.
*/
+#include <linux/config.h>
#include <linux/ptrace.h>
#include <linux/errno.h>
#include <linux/kernel_stat.h>
Index: include/asm-sh/hitachi_se.h
===================================================================
RCS file: /cvsroot/linuxsh/kernel/include/asm-sh/hitachi_se.h,v
retrieving revision 1.2
diff -u -r1.2 hitachi_se.h
--- include/asm-sh/hitachi_se.h 2000/05/09 00:14:00 1.2
+++ include/asm-sh/hitachi_se.h 2000/06/07 09:42:00
@@ -39,6 +39,22 @@
#define PA_BCR 0xb1400000 /* FPGA */
#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */
+#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION (PA_MRSHPC + 6)
+#define MRSHPC_CSR (PA_MRSHPC + 8)
+#define MRSHPC_ISR (PA_MRSHPC + 10)
+#define MRSHPC_ICR (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
+#define MRSHPC_CDCR (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
#define BCR_ILCRA (PA_BCR + 0)
#define BCR_ILCRB (PA_BCR + 2)
|
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From: Toshiharu N. <no...@hi...> - 2000-06-07 10:17:43
|
Thank you for an opinion. I confirmed whether other Solution Engine worked. Solution Engine of SH3(09A) worked. but, it will work only with my boot environment. there was still a lot of problems. kaz Kojima wrote: > causes problem by the magic number 0x3000. It's not bad to initialize > sh_pcic_io_start and sh_pcic_io_stop but they will cheaged by PCMCIA > driver like pcmcia-cs. Nozawa-san, you can't handle these variable > as constants. OK. I understand. Probably, I thought so. I will revise this. > > It seems that your comments above means we need this "0x400000" for > > byte access of "read" (in). Is there any reason why we don't need > > this "0x40000" for "write" (out)? > > This chip is odd enough. These four 256KB spaces are exactly same in > write access. According to the manual of MRSHPC, there was resize to PCMCIA bus. On this account byte/word space every 256KByte thinks that there is not semantics. Then, I have decided to do every access to real-word space. Is this wrong? (However, this is the cause of confusion.) -- |
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From: kaz K. <kk...@rr...> - 2000-06-07 10:58:42
|
Toshiharu Nozawa writes: > According to the manual of MRSHPC, there was resize to PCMCIA bus. > On this account byte/word space every 256KByte thinks that > there is not semantics. > Then, I have decided to do every access to real-word space. > Is this wrong? (However, this is the cause of confusion.) I can't say it's wrong. But I've troubled with this bus sizing in porting pcmcia-cs, though I forgot its detail. This is the reason why I used the word defensive. kaz |
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From: Toshiharu N. <no...@kt...> - 2000-06-07 14:33:15
|
kaz Kojima wrote: > I can't say it's wrong. But I've troubled with this bus sizing > in porting pcmcia-cs, though I forgot its detail. This is the > reason why I used the word defensive. I had the same troubles, too. I memorize it that the cause was endian conversion of MRSHPC. meaning of SWAP flag on manual was contrary. My enabler is used with some software, then seems to work well all. but, Because it become the cause of confusion, I intend to revise it. Thnaks kaz |
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From: kaz K. <kk...@rr...> - 2000-06-08 00:44:20
|
Toshiharu Nozawa wrote: > I had the same troubles, too. I memorize it that the cause was > endian conversion of MRSHPC. meaning of SWAP flag on manual was > contrary. My enabler is used with some software, then seems to > work well all. but, Because it become the cause of confusion, > I intend to revise it. Ah! I see. Thank you for the clarification. kaz |
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