linuxsh-dev

Re: [1/1] trivial cleanups.

[Paul M. <pau...@re...>]

On Mon, May 28, 2007 at 08:16:17PM +0400, Evgeniy Polyakov wrote:
> Several errors were spotted during building for custom config (SMP
> included). Although SMP still does not compile (no ipi and
> __smp_call_function) and does not work, this looks a bit cleaner.
> Some other errors obtained via gcc-4.1.0 build.
> 
Yeah, the SMP stuff is aimed at 2.6.23 (there's also some rework to get
randconfigs and allmodconfigs working).

> Signed-off-by: Evgeniy Polyakov <jo...@2k...>
> 
Thanks, applied.

Re: Platform drivers vs device drivers

[Kristoffer E. <kri...@gm...>]

Thanks for explaining, will take the time to look through the documentation
you suggested. I see your point.

2007/5/30, Paul Mundt <le...@li...>:
>
> On Tue, May 29, 2007 at 12:32:02AM -0700, Kristoffer Ericson wrote:
> > From what I gather platform devices are devices that are expected to
> > exist on a specific hardware. For example all hp jornada 680 devices
> > contain an onboard keyboard which usually is a good thing to have.
> >
> This sentence is fairly vague, so I'm not entirely sure what you're
> confused about. The driver model supports busses with drivers that attach
> to that bus, and then 'devices' that attach to that driver. The platform
> bus itself is just a stupid bus for devices that are generally directly
> connected and have a minimal level of intelligence associated with them.
> ie, if it doesn't hang off of any other bus (or it's directly on SH-bus),
> it's a platform device.
>
> A board or CPU will simply register 'devices' for everything that it
> has which have matching platform drivers. The platform device data itself
> is __initdata, and will be freed up once we've booted and the drivers
> have had a chance to claim the resources they're interested in. Whether
> the driver manages to 'find' the device or not, depends on whether you
> have that driver enabled or not (unclaimed devices are discarded, so it's
> always safe to just register the entire set).
>
> There are some documents on lwn.net regarding the basics of the driver
> model, perhaps that would be a good place to start reading.
>
> > If this is correct then my next question is, wouldn't it be desirable
> > for the hp680 keyboard to be hardcoded in any kernel targetting a hp680
> > (instead of being an optional kernel config)?
> >
> Why on earth would you want to hardcode anything? The very idea behind
> the driver model is so we do not have to do stupid things like that.
> There's absolutely _nothing_ special about the hp680 keyboard, and there
> are other boards which can use it as well (with a bit of reasonable
> abstraction). Restricting a driver to a board is nonsensical, this isn't
> 2.4 any more.
>
> > I can't see any benefit of being able to compile a kernel for that
> > platform without keyboard support.
>
> Then enable it in the defconfig. However, do not give in to this 'select'
> brain-damage either, turning on subsystems unconditionally is evil.
> People will configure what they want, the defconfig is simply a pointer
> to what should result in a functional system out of the box.
>

What compiler version to use for the kernel

[EXTERNAL B. M. (P. ST-FIR/Eng) <ext...@de...>]

Hi all,

I have problems using newer versions of gcc with my old 2.4.22 kernel.=20
GCC 3.2.3 with binutils 2.15 is the latest compiler I can use. Newer
ones result in a "Unable to handle kernel paging request" error most of
the time.

Does anybody still use 2.4 kernels? What compiler version do you use?

Unfortunatelly 2.4.22 is the only kernel runnig on that board so far,
but I will port the latest 2.4 kernel to the board soon.=20
It's a sh3-dsp (7720) based board, are there any hints for porting?=20
I've seen that there is dsp support in 2.4.34, but no 7720 in the cpu
type to select.=20
Is that sufficient for my 7720, or will I need to migrate the patches
from my current kernel?

Thanks,

Markus

Re: Platform drivers vs device drivers

[Paul M. <le...@li...>]

On Tue, May 29, 2007 at 12:32:02AM -0700, Kristoffer Ericson wrote:
> From what I gather platform devices are devices that are expected to
> exist on a specific hardware. For example all hp jornada 680 devices
> contain an onboard keyboard which usually is a good thing to have.
> 
This sentence is fairly vague, so I'm not entirely sure what you're
confused about. The driver model supports busses with drivers that attach
to that bus, and then 'devices' that attach to that driver. The platform
bus itself is just a stupid bus for devices that are generally directly
connected and have a minimal level of intelligence associated with them.
ie, if it doesn't hang off of any other bus (or it's directly on SH-bus),
it's a platform device.

A board or CPU will simply register 'devices' for everything that it
has which have matching platform drivers. The platform device data itself
is __initdata, and will be freed up once we've booted and the drivers
have had a chance to claim the resources they're interested in. Whether
the driver manages to 'find' the device or not, depends on whether you
have that driver enabled or not (unclaimed devices are discarded, so it's
always safe to just register the entire set).

There are some documents on lwn.net regarding the basics of the driver
model, perhaps that would be a good place to start reading.

> If this is correct then my next question is, wouldn't it be desirable
> for the hp680 keyboard to be hardcoded in any kernel targetting a hp680
> (instead of being an optional kernel config)?
> 
Why on earth would you want to hardcode anything? The very idea behind
the driver model is so we do not have to do stupid things like that.
There's absolutely _nothing_ special about the hp680 keyboard, and there
are other boards which can use it as well (with a bit of reasonable
abstraction). Restricting a driver to a board is nonsensical, this isn't
2.4 any more.

> I can't see any benefit of being able to compile a kernel for that
> platform without keyboard support.

Then enable it in the defconfig. However, do not give in to this 'select'
brain-damage either, turning on subsystems unconditionally is evil.
People will configure what they want, the defconfig is simply a pointer
to what should result in a functional system out of the box.

Platform drivers vs device drivers

[Kristoffer E. <kri...@gm...>]

Greetings,

>From what I gather platform devices are devices that are expected to exist on a specific hardware. For example all hp jornada 680 devices contain an onboard keyboard which usually is a good thing to have.

If this is correct then my next question is, wouldn't it be desirable for the hp680 keyboard to be hardcoded in any kernel targetting a hp680 (instead of being an optional kernel config)?

I can't see any benefit of being able to compile a kernel for that platform without keyboard support.
Some hardware has a point in being optional as for example the sounddriver. I rarely use it and dont want it to take up space in between.

Best wishes
Kristoffer Ericson

[1/1] trivial cleanups.

[Evgeniy P. <jo...@2k...>]

Hi.

Several errors were spotted during building for custom config (SMP
included). Although SMP still does not compile (no ipi and
__smp_call_function) and does not work, this looks a bit cleaner.
Some other errors obtained via gcc-4.1.0 build.

Signed-off-by: Evgeniy Polyakov <jo...@2k...>

diff --git a/arch/sh/kernel/cf-enabler.c b/arch/sh/kernel/cf-enabler.c
index 849a9e1..ebc73b8 100644
--- a/arch/sh/kernel/cf-enabler.c
+++ b/arch/sh/kernel/cf-enabler.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
+#include <linux/interrupt.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
@@ -149,6 +150,11 @@ static int __init cf_init_se(void)
 	ctrl_outb(0x42, PA_MRSHPC_MW2 + 0x200);
 	return 0;
 }
+#else
+static int __init cf_init_se(void)
+{
+	return -1;
+}
 #endif
 
 int __init cf_init(void)
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 8cd0490..fab2eb0 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -12,6 +12,7 @@
  */
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/smp.h>
 #include <asm/processor.h>
 #include <asm/cache.h>
 
diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c
index dbebadd..283e142 100644
--- a/arch/sh/kernel/smp.c
+++ b/arch/sh/kernel/smp.c
@@ -10,6 +10,8 @@
  * Free Software Foundation; either version 2 of the License, or (at your
  * option) any later version.
  */
+
+#include <linux/err.h>
 #include <linux/cache.h>
 #include <linux/cpumask.h>
 #include <linux/delay.h>
diff --git a/arch/sh/kernel/vsyscall/vsyscall.c b/arch/sh/kernel/vsyscall/vsyscall.c
index e146baf..2aa9438 100644
--- a/arch/sh/kernel/vsyscall/vsyscall.c
+++ b/arch/sh/kernel/vsyscall/vsyscall.c
@@ -17,6 +17,7 @@
 #include <linux/gfp.h>
 #include <linux/module.h>
 #include <linux/elf.h>
+#include <linux/sched.h>
 
 /*
  * Should the kernel map a VDSO page into processes and pass its
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
index 86564e7..39f41fc 100644
--- a/include/asm-sh/cpu-sh4/freq.h
+++ b/include/asm-sh/cpu-sh4/freq.h
@@ -24,6 +24,9 @@
 #define FRQMR1			0xffc80014
 #else
 #define FRQCR			0xffc00000
+#define FRQCR_PSTBY		0x0200
+#define FRQCR_PLLEN		0x0400
+#define FRQCR_CKOEN		0x0800
 #endif
 #define MIN_DIVISOR_NR		0
 #define MAX_DIVISOR_NR		3
diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h
index faf3051..6034d4a 100644
--- a/include/asm-sh/dma.h
+++ b/include/asm-sh/dma.h
@@ -13,6 +13,7 @@
 
 #include <linux/spinlock.h>
 #include <linux/wait.h>
+#include <linux/sched.h>
 #include <linux/sysdev.h>
 #include <asm/cpu/dma.h>
 
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
index a0e55b0..aa80930 100644
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@@ -116,13 +116,13 @@ void __raw_readsl(unsigned long addr, void *data, int longlen);
  * redefined by userlevel programs.
  */
 #ifdef __readb
-# define readb(a)	({ unsigned long r_ = __raw_readb(a); mb(); r_; })
+# define readb(a)	({ unsigned int r_ = __raw_readb(a); mb(); r_; })
 #endif
 #ifdef __raw_readw
-# define readw(a)	({ unsigned long r_ = __raw_readw(a); mb(); r_; })
+# define readw(a)	({ unsigned int r_ = __raw_readw(a); mb(); r_; })
 #endif
 #ifdef __raw_readl
-# define readl(a)	({ unsigned long r_ = __raw_readl(a); mb(); r_; })
+# define readl(a)	({ unsigned int r_ = __raw_readl(a); mb(); r_; })
 #endif
 
 #ifdef __raw_writeb
diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h
index 71ecddf..caa7b93 100644
--- a/include/asm-sh/smp.h
+++ b/include/asm-sh/smp.h
@@ -15,7 +15,7 @@
 
 #ifdef CONFIG_SMP
 
-#include <asm/spinlock.h>
+#include <linux/spinlock.h>
 #include <asm/atomic.h>
 #include <asm/current.h>
 
diff --git a/include/asm-sh/spinlock.h b/include/asm-sh/spinlock.h
index 2586eef..92f6e20 100644
--- a/include/asm-sh/spinlock.h
+++ b/include/asm-sh/spinlock.h
@@ -11,6 +11,7 @@
 #define __ASM_SH_SPINLOCK_H
 
 #include <asm/atomic.h>
+#include <asm/spinlock_types.h>
 
 /*
  * Your basic SMP spinlocks, allowing only a single CPU anywhere
@@ -42,7 +43,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
 
 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 {
-	assert_spin_locked(lock);
+	//assert_spin_locked(lock);
 
 	lock->lock = 0;
 }
@@ -88,6 +89,11 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
 	__raw_spin_unlock(&rw->lock);
 }
 
+static inline int __raw_write_can_lock(raw_rwlock_t *rw)
+{
+	return (atomic_read(&rw->counter) == RW_LOCK_BIAS);
+}
+
 static inline int __raw_read_trylock(raw_rwlock_t *lock)
 {
 	atomic_t *count = (atomic_t*)lock;
diff --git a/include/asm-sh/spinlock_types.h b/include/asm-sh/spinlock_types.h
index 8c41b6c..5c58134 100644
--- a/include/asm-sh/spinlock_types.h
+++ b/include/asm-sh/spinlock_types.h
@@ -9,7 +9,9 @@ typedef struct {
 	volatile unsigned long lock;
 } raw_spinlock_t;
 
-#define __SPIN_LOCK_UNLOCKED		{ 0 }
+#define __RAW_SPIN_LOCK_UNLOCKED	{ 1 }
+
+#include <asm/atomic.h>
 
 typedef struct {
 	raw_spinlock_t lock;

-- 
	Evgeniy Polyakov

[PATCH 2.6.22-rc3] sh: fix vsyscall build error

[Manuel L. <ma...@ro...>]

Fix sh vsyscall build failure

  CC      arch/sh/kernel/vsyscall/vsyscall.o
a/arch/sh/kernel/vsyscall/vsyscall.c: In function 'arch_setup_additional_pages':
a/arch/sh/kernel/vsyscall/vsyscall.c:63: error: dereferencing pointer to incomplete type
a/arch/sh/kernel/vsyscall/vsyscall.c:67: error: dereferencing pointer to incomplete type
a/arch/sh/kernel/vsyscall/vsyscall.c:82: error: dereferencing pointer to incomplete type
a/arch/sh/kernel/vsyscall/vsyscall.c:85: error: dereferencing pointer to incomplete type
a/arch/sh/kernel/vsyscall/vsyscall.c: In function 'arch_vma_name':
a/arch/sh/kernel/vsyscall/vsyscall.c:91: error: dereferencing pointer to incomplete type

Signed-off-by: Manuel Lauss <ma...@ro...>

--- a/arch/sh/kernel/vsyscall/vsyscall.c	2007-05-27 13:17:05.000000000 +0200
+++ d/arch/sh/kernel/vsyscall/vsyscall.c	2007-05-28 15:55:54.000000000 +0200
@@ -17,6 +17,7 @@
 #include <linux/gfp.h>
 #include <linux/module.h>
 #include <linux/elf.h>
+#include <linux/sched.h>
 
 /*
  * Should the kernel map a VDSO page into processes and pass its

[PATCH 2.6.22-rc3] sh: dma-api.c compile fix

[Manuel L. <ma...@ro...>]

Trivial fix for arch/sh/drivers/dma/dma-api.c compile failure:

  CC      arch/sh/drivers/dma/dma-api.o
a/arch/sh/drivers/dma/dma-api.c: In function 'dma_wait_for_completion':
a/arch/sh/drivers/dma/dma-api.c:233: error: 'TASK_UNINTERRUPTIBLE' undeclared (first use in this function)
a/arch/sh/drivers/dma/dma-api.c:233: error: (Each undeclared identifier is reported only once
a/arch/sh/drivers/dma/dma-api.c:233: error: for each function it appears in.)
a/arch/sh/drivers/dma/dma-api.c:233: warning: implicit declaration of function 'schedule'

Signed-off-by: Manuel Lauss <ma...@ro...>

--- a/arch/sh/drivers/dma/dma-api.c	2007-05-27 13:17:03.000000000 +0200
+++ c/arch/sh/drivers/dma/dma-api.c	2007-05-28 15:42:36.000000000 +0200
@@ -16,6 +16,7 @@
 #include <linux/list.h>
 #include <linux/platform_device.h>
 #include <linux/mm.h>
+#include <linux/sched.h>
 #include <asm/dma.h>
 
 DEFINE_SPINLOCK(dma_spin_lock);

Re: Build errors on Dreamcast with 2.6.22-rc3

[Manuel L. <ma...@ro...>]

Adrian McMenamin wrote:
> There used to be a lot of these sort of errors for -rc2, but most have
> now gone, but still getting these...
> 
> WARNING: arch/sh/kernel/built-in.o(.text+0x87b4): Section mismatch:
> reference to .init.data: (between 'get_sys_timer' and 'tmu_timer_start')
> WARNING: arch/sh/kernel/built-in.o(.text+0x87b8): Section mismatch:
> reference to .init.data: (between 'get_sys_timer' and 'tmu_timer_start')

These two can be removed by adding "__init" to 'get_sys_timer()',

> WARNING: arch/sh/boards/dreamcast/built-in.o(.data+0x0): Section
> mismatch: reference to .init.text: (between 'mv_dreamcast' and
> 'systemasic_int')

and this one by removing the "__init" from all functions which are referenced
by the machvec.

I think these warnings are bogus in general because both get_sys_timer and
sh_mv.mv_init_irq() are called only once: during kernel init.

> WARNING: drivers/built-in.o(.text+0x168e0): Section mismatch: reference
> to .init.data: (between 'pvr2fb_check_var' and 'pvr2fb_interrupt')
> WARNING: drivers/built-in.o(.text+0x1701c): Section mismatch: reference
> to .init.data: (between 'pvr2fb_pci_probe' and 'read_mem')
> WARNING: drivers/built-in.o(.text+0x17024): Section mismatch: reference
> to .init.text: (between 'pvr2fb_pci_probe' and 'read_mem')
> WARNING: drivers/built-in.o(.data+0x738): Section mismatch: reference
> to .init.text: (between 'board_list' and 'pvr2fb_pci_driver')
> WARNING: drivers/built-in.o(.data+0x750): Section mismatch: reference
> to .init.text: (between 'board_list' and 'pvr2fb_pci_driver')

Can't help with those, sorry.

Thanks,

	Manuel Lauss

Build errors on Dreamcast with 2.6.22-rc3

[Adrian M. <ad...@ne...>]

There used to be a lot of these sort of errors for -rc2, but most have
now gone, but still getting these...

WARNING: arch/sh/kernel/built-in.o(.text+0x87b4): Section mismatch:
reference to .init.data: (between 'get_sys_timer' and 'tmu_timer_start')
WARNING: arch/sh/kernel/built-in.o(.text+0x87b8): Section mismatch:
reference to .init.data: (between 'get_sys_timer' and 'tmu_timer_start')
WARNING: arch/sh/boards/dreamcast/built-in.o(.data+0x0): Section
mismatch: reference to .init.text: (between 'mv_dreamcast' and
'systemasic_int')
WARNING: drivers/built-in.o(.text+0x168e0): Section mismatch: reference
to .init.data: (between 'pvr2fb_check_var' and 'pvr2fb_interrupt')
WARNING: drivers/built-in.o(.text+0x1701c): Section mismatch: reference
to .init.data: (between 'pvr2fb_pci_probe' and 'read_mem')
WARNING: drivers/built-in.o(.text+0x17024): Section mismatch: reference
to .init.text: (between 'pvr2fb_pci_probe' and 'read_mem')
WARNING: drivers/built-in.o(.data+0x738): Section mismatch: reference
to .init.text: (between 'board_list' and 'pvr2fb_pci_driver')
WARNING: drivers/built-in.o(.data+0x750): Section mismatch: reference
to .init.text: (between 'board_list' and 'pvr2fb_pci_driver')

Re: [PATCH] Add lost in_nmi definition to solve pcrel too far.

[Paul M. <le...@li...>]

On Fri, May 25, 2007 at 12:48:52AM +0900, tak...@op... wrote:
> BTW, Which tree should we check hard during rc time?
>  1. sh-2.6
>  2. sh-2.6.x
>  3. archived -rc tree
>  4. linus's tree
> 
> This time I checked 1,2 and 3.
> Presicely, I found in 1, then check 2 if it is solved, and confirmd in 3.
> Are there any extra work to do(perhaps 4)? (or easyer way?)
> 
The general scheme is that sh-2.6.git is only a temporary staging tree
where Linus pulls for the next -rc. I usually aim for about one pull for
every -rc, but occasionally one gets missed. After -rc2, it's simply bug
fixes. It's good to test on as many configurations as possible simply to
make sure that the -final ends up working, too.

Once -rc2 rolls around, I usually open up the next sh-2.6.x.git and start
queueing up the development work for the next merge window there. It is
helpful to have this tested and to have patches go in, but it's in a much
greater state of flux, so it really depends on what sort of testing and
bug fixing you're comfortable with. Once we're later in the -rc stages,
sh-2.6.x.git should settle down in preparation for the merge window. You
may want to do testing before or after that point, it really depends what
sort of patches you have that you want to aim for the merge window.
You'll have to use your judgment on that.

In general, I would suggest just using Linus's tree. If there's a problem
there, it may have already been fixed in sh-2.6.git, in which case, it
will trickle down naturally within a few days (and you can simply pull
that down if it's already been resolved, too). In general, it's good to
know what sort of regressions we have to handle for whatever the next -rc
is.

> Add lost in_nmi definition to solve pcrel too far.
> 
> Signed-off-by: Takashi YOSHII <tak...@op...>
> 
> diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
> index 832c0b4..659cc08 100644
> --- a/arch/sh/kernel/cpu/sh3/entry.S
> +++ b/arch/sh/kernel/cpu/sh3/entry.S
> @@ -320,6 +320,7 @@ skip_restore:
>  
>  	.align	2
>  5:	.long	0x00001000	! DSP
> +6:	.long	in_nmi
>  7:	.long	0x30000000
>  
>  ! common exception handler
> 
Thanks, I'll queue it up.

[PATCH] Add lost in_nmi definition to solve pcrel too far.

[<tak...@op...>]

22-rc2 results following error when KGDB and KGDB_NMI are selected.
| ...
| AS      arch/sh/kernel/cpu/sh3/entry.o
| arch/sh/kernel/cpu/sh3/entry.S: Assembler messages:
| arch/sh/kernel/cpu/sh3/entry.S:312: Error: pcrel too far

BTW, Which tree should we check hard during rc time?
 1. sh-2.6
 2. sh-2.6.x
 3. archived -rc tree
 4. linus's tree

This time I checked 1,2 and 3.
Presicely, I found in 1, then check 2 if it is solved, and confirmd in 3.
Are there any extra work to do(perhaps 4)? (or easyer way?)

Regards,
/yoshii

Add lost in_nmi definition to solve pcrel too far.

Signed-off-by: Takashi YOSHII <tak...@op...>

diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
index 832c0b4..659cc08 100644
--- a/arch/sh/kernel/cpu/sh3/entry.S
+++ b/arch/sh/kernel/cpu/sh3/entry.S
@@ -320,6 +320,7 @@ skip_restore:
 
 	.align	2
 5:	.long	0x00001000	! DSP
+6:	.long	in_nmi
 7:	.long	0x30000000
 
 ! common exception handler

Re: booting problem

[Paul M. <le...@li...>]

On Thu, May 24, 2007 at 09:05:13AM +0200, Martin Zwickel wrote:
> On Thu, 24 May 2007 14:34:48 +0900
> Paul Mundt <le...@li...> bubbled:
> 
> > On Thu, May 24, 2007 at 06:08:23AM +0100, driver init wrote:
> > >           I am new to STLinux which is based on SH , I was working
> > > on the ST EVAL board where i came cross this boot problem,
> > >           can some one please point where i went wrong,
> > >           below is there error message.
> > 
> > http://article.gmane.org/gmane.linux.ports.sh.devel/1654
> 
> There is nothing about STAPI. Just the kernel log. So the report is ok.
> 
> But I can't see the error...  only an IP-Config and st-coproc warning,
> but that could be intentional.
> 
No, the report is not ok, because this is on a heavily modified kernel
where the results are completely undefined. If you use a vendor kernel,
you get to use vendor support. Period.

Re: booting problem

[Martin Z. <mar...@te...>]

On Thu, 24 May 2007 14:34:48 +0900
Paul Mundt <le...@li...> bubbled:

> On Thu, May 24, 2007 at 06:08:23AM +0100, driver init wrote:
> >           I am new to STLinux which is based on SH , I was working
> > on the ST EVAL board where i came cross this boot problem,
> >           can some one please point where i went wrong,
> >           below is there error message.
>=20
> http://article.gmane.org/gmane.linux.ports.sh.devel/1654

There is nothing about STAPI. Just the kernel log. So the report is ok.

But I can't see the error...  only an IP-Config and st-coproc warning,
but that could be intentional.

--=20
MyExcuse:
We are Microsoft.  What you are experiencing is not a problem; it is an
undocumented feature.

Martin Zwickel <mar...@te...>
Research & Development

Re: booting problem

[Paul M. <le...@li...>]

On Thu, May 24, 2007 at 06:08:23AM +0100, driver init wrote:
>           I am new to STLinux which is based on SH , I was working on the
>           ST EVAL board where i came cross this boot problem,
>           can some one please point where i went wrong,
>           below is there error message.

http://article.gmane.org/gmane.linux.ports.sh.devel/1654

booting problem

[driver i. <mod...@ya...>]

Hi All,

       I am new to STLinux which is based on SH , I was working on the
       ST EVAL board where i came cross this boot problem,
       can some one please point where i went wrong,
       below is there error message.

set bootargs console=ttyAS0,115200 ide0=noprobe mem=36m 
bigphysarea=1512 initrd=initrd.bin init=/sbin/init root=/dev/ram0 ramdisk_size=262144
STEVAL-BOARD> bootm a0040000 a05a0000
## Booting image at a0040000 ...
   Image Name:   Linux-2.6.17.14_stm22_0037
   Image Type:   SuperH Linux Kernel Image (gzip compressed)
   Data Size:    1610926 Bytes =  1.5 MB
   Load Address: 84401000
   Entry Point:  84402000
   Verifying Checksum ... OK
   Uncompressing Kernel Image ... OK
   Image Name:   ST40 Linux ramdisk
   Image Type:   SH-4 Linux RAMDisk Image (uncompressed)
   Data Size:    2435165 Bytes =  2.3 MB
   Load Address: 88000000
   Entry Point:  88000000
   Verifying Checksum ...
 OK
   Loading Ramdisk to 84dad000, length 0025285d ... OK

Starting kernel console=ttyAS0,115200 ide0=noprobe mem=36m 
bigphysarea=1512 initrd=initrd.bin init=/sbin/init root=/dev/ram0 
ramdisk_size=262144 - 0x009ad000 - 2435165 ...

Linux version 2.6.17.14_stm22_0037 (root@localhost.localdomain) (gcc 
version 4.1.1 (STMicroelectronics/Linux Base 4.1.1-21)) #22 PREEMPT Mon 
May 21 10:48:22 IST 2007
STMicroelectronics STb7100 Reference board initialisation
STb7109 version 3.x
Built 1 zonelists
Kernel command line: console=ttyAS0,115200 ide0=noprobe mem=36m 
bigphysarea=1512 initrd=initrd.bin init=/sbin/init root=/dev/ram0 
ramdisk_size=262144
PID hash table entries: 256 (order: 8, 1024 bytes)
Using tmu for system timer
Console: colour dummy device 80x25
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 24820k/36864k available (2652k
 kernel code, 12024k reserved, 
348k data, 96k init)
PVR=04061100 CVR=30480000 PRR=00009300
I-cache : n_ways=2 n_sets=256 way_incr=8192
I-cache : entry_mask=0x00001fe0 alias_mask=0x00001000 n_aliases=2
D-cache : n_ways=2 n_sets=512 way_incr=16384
D-cache : entry_mask=0x00003fe0 alias_mask=0x00003000 n_aliases=4
Mount-cache hash table entries: 512
CPU: STb710x
checking if image is initramfs...it isn't (no cpio magic); looks like 
an initrd
Freeing initrd memory: 2378k freed
NET: Registered protocol family 16
Generic PHY: Registered new driver
SCSI subsystem initialized
usbcore: registered new driver usbfs
usbcore: registered new driver hub
NET: Registered protocol family 2
IP route cache hash table entries: 512 (order: -1, 2048 bytes)
TCP established hash table entries: 2048 (order: 1, 8192 bytes)
TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
TCP: Hash tables configured (established 2048 bind
 1024)
TCP reno registered
bigphysarea: Allocated 1512 pages at 0x84776000.
JFFS2 version 2.2. (NAND) (C) 2001-2003 Red Hat, Inc.
io scheduler noop registered
io scheduler anticipatory registered (default)
io scheduler deadline registered
io scheduler cfq registered
STPIO layer initialised
STMicroelectronics ASC driver initialized
ttyAS0 at MMIO 0xb8030000 (irq = 121) is a asc
ttyAS1 at MMIO 0xb8033000 (irq = 120) is a asc
RAMDISK driver initialized: 16 RAM disks of 262144K size 1024 blocksize
STe100p: Registered new driver
STe101p: Registered new driver
nwhw_config: device not found
ata1: SATA max UDMA/133 cmd 0xB9209000 ctl 0xB9209820 bmdma 0x0 irq 170
ata1: SATA link down (SStatus 0)
scsi0 : sata_stm
Generic ST boards onboard flash device: 0x00800000 (8.0Mb) at 
0x00000000
Onboard_Flash: Found 1 x16 devices at 0x0 in 16-bit bank
 Intel/Sharp Extended Query Table at 0x0031
Using buffer write
 method
cfi_cmdset_0001: Erase suspend on write enabled
Creating 3 MTD partitions on "Onboard_Flash":
0x00000000-0x00040000 : "Boot firmware"
ftl_cs: FTL header not found.
0x00040000-0x00140000 : "Kernel"
ftl_cs: FTL header not found.
0x00140000-0x00800000 : "Root FS"
ftl_cs: FTL header not found.
usbmon: debugfs is not available
ST40_start_host_control
ST40_start_host_control proceeding
ST40-ehci ST40-ehci.2: ST EHCI Host Controller
ST40-ehci ST40-ehci.2: new USB bus registered, assigned bus number 1
ST40-ehci ST40-ehci.2: irq 169, io mem 0xb91ffe00
ST40-ehci ST40-ehci.2: USB 0.0 started, EHCI 1.00, driver 10 Dec 2004
usb usb1: configuration #1 chosen from 1 choice
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
2005 April 22 USB 1.1 'Open' Host Controller (OHCI) Driver (ST40)
ST40_start_host_control
ST40-ohci ST40-ohci.1: STB7100 OHCI
ST40-ohci ST40-ohci.1: new USB bus registered, assigned bus
 number 2
ST40-ohci ST40-ohci.1: irq 168, io mem 0xb91ffc00
usb usb2: configuration #1 chosen from 1 choice
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 1 port detected
Initializing USB Mass Storage driver...
usb 1-1: new high speed USB device using ST40-ehci and address 2
usb 1-1: configuration #1 chosen from 1 choice
usbcore: registered new driver usb-storage
USB Mass Storage support registered.
usbcore: registered new driver usbhid
drivers/usb/input/hid-core.c: v2.6:USB HID core driver
pegasus: v0.6.13 (2005/11/13), Pegasus/Pegasus II USB Ethernet driver
usbcore: registered new driver pegasus
eth0: register 'asix' at usb-STB7100_EHCI-1, ASIX AX88772 USB 2.0 
Ethernet, 00:0e:c6:00:00:c8
usbcore: registered new driver asix
usbcore: registered new driver cdc_ether
usbcore: registered new driver net1080
usbcore: registered new driver zaurus
mice: PS/2 mouse device common for all mice
i2c /dev entries driver
stssc
 layer initialized
STMicroelectronics - Coprocessors st231 Init
st-coprocessor-0: No RAM reserved
st231-0 Coprocessor -------------------------------------------
    not configured!
---------------------------------------------------------------
st-coprocessor-1: No RAM reserved
st231-1 Coprocessor -------------------------------------------
    not configured!
---------------------------------------------------------------
TCP bic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
IP-Config: Incomplete network configuration information.
RAMDISK: Compressed image found at block 0

Regards,
Hemanth
       

       
---------------------------------
 Looking for people who are YOUR TYPE?  Find them here!

Re: 2.6.22-rc2 prepatch breaks compile on Dreamcast

[Paul M. <le...@li...>]

On Sat, May 19, 2007 at 01:07:00PM +0100, Adrian McMenamin wrote:
> The patch includes:
> 
> -#if OFFCHIP_NR_IRQS > 0
> -# define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
> -#endif
> 
> 
> but the OFFCHIP_IRQ_BASE symbol is still referenced in the Dreamcast
> code, so a compile generates this:
> 
This will fix it, queued for -rc3:

diff --git a/include/asm-sh/dreamcast/sysasic.h b/include/asm-sh/dreamcast/sysasic.h
index 7874e3d..f334266 100644
--- a/include/asm-sh/dreamcast/sysasic.h
+++ b/include/asm-sh/dreamcast/sysasic.h
@@ -23,7 +23,7 @@
    takes.
 */
 
-#define HW_EVENT_IRQ_BASE  OFFCHIP_IRQ_BASE /* 48 */
+#define HW_EVENT_IRQ_BASE  48
 
 /* IRQ 13 */
 #define HW_EVENT_VSYNC     (HW_EVENT_IRQ_BASE +  5) /* VSync */

[PATCH] Add L-BOX RE2 to mach-types

[Nobuhiro I. <iwa...@ni...>]

Hi , Paul.

I added L-BOX RE2's type to mach-type file.
Please apply .

regards,
 Nobuhiro
-- 
Nobuhiro Iwamatsu
	E-Mail : iwa...@ni...
	GPG ID : 3170EBE9 

Signed-off-by: Nobuhiro Iwamatsu <iwa...@ni...>

diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index fb40f18..8ae43f8 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -34,3 +34,4 @@ R7785RP			SH_R7785RP
 TITAN			SH_TITAN
 SHMIN			SH_SHMIN
 7710VOIPGW		SH_7710VOIPGW
+LBOXRE2			SH_LBOX_RE2

2.6.22-rc2 prepatch breaks compile on Dreamcast

[Adrian M. <ad...@ne...>]

The patch includes:

-#if OFFCHIP_NR_IRQS > 0
-# define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
-#endif


but the OFFCHIP_IRQ_BASE symbol is still referenced in the Dreamcast
code, so a compile generates this:

arch/sh/boards/dreamcast/irq.c: In function `disable_systemasic_irq':
arch/sh/boards/dreamcast/irq.c:59: error: `OFFCHIP_IRQ_BASE' undeclared
(first use in this function)
arch/sh/boards/dreamcast/irq.c:59: error: (Each undeclared identifier is
reported only once
arch/sh/boards/dreamcast/irq.c:59: error: for each function it appears
in.)
arch/sh/boards/dreamcast/irq.c: In function `enable_systemasic_irq':
arch/sh/boards/dreamcast/irq.c:70: error: `OFFCHIP_IRQ_BASE' undeclared
(first use in this function)
arch/sh/boards/dreamcast/irq.c: In function `ack_systemasic_irq':
arch/sh/boards/dreamcast/irq.c:81: error: `OFFCHIP_IRQ_BASE' undeclared
(first use in this function)
arch/sh/boards/dreamcast/irq.c: In function `systemasic_irq_demux':
arch/sh/boards/dreamcast/irq.c:146: error: `OFFCHIP_IRQ_BASE' undeclared
(first use in this function)

Re: APM issues

[Paul M. <le...@li...>]

On Fri, May 18, 2007 at 03:11:59AM -0700, Kristoffer Ericson wrote:
> On Tue, 15 May 2007 08:26:41 +0900
> Paul Mundt <le...@li...> wrote:
> > Sounds like it's not acked and masked properly, start debugging the
> > irq_chip handler that's got this IRQ.
> > 
>   The interrupt (32) is defined by the ipr_mapping and should be handled by
>   disable_ipr_irq(irq) for mask_acked. The line goes : 
>   ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr);
>  
[snip]

> maybe it has something to do with level/edge settings.
> 
Yes, if it's just a normal IPR IRQ, then the IRQ flow is the next thing
to look at.

On Fri, May 18, 2007 at 03:58:09AM -0700, Kristoffer Ericson wrote:
> I've read through the manual and perhaps its due to IRQ0->IRQ3 being
> set as edge instead of level. It says in the manual that to clear edge
> interrupts one needs to  read corresponding bit from IRR0 (1) and then
> write 0. *shrug* best idea yet. It would explain why a single press
> would send out interrupts.
> 
IRQ sensing is configurable, we'll have to implement a bit of logic for
setting the type, and you'll have to toss in a flag at your request_irq()
time with the level/edge selection, but that's not too big of a deal.
Generally we've avoided this since we have next to no pure-edge cases to
worry about (mostly just old broken SuperIOs that people habitually
interface to a level-only pin anyways).

> They should be set as edge by default, I've done some tests trying to
> set IRQ0 as level, but no boot. 
> 
If it's an edge IRQ you should not be seeing a retriggering of the IRQ,
that's more a property of unacked level IRQs that don't deassert until
they've been handled, in the edge case you'll simply miss the IRQ.

Changing the sense selection for an IRQ will not impact your ability to
boot (especially on something as mundane as IRQ0), so I suggest you take
a look at this again. The generic hardirq layer is the way to do this,
including a ->set_type() in the IPR irq_chip(), going around it is only
asking for trouble.

Re: [PATCH] hp6xx/pm.c cleanup

[Paul M. <le...@li...>]

On Thu, May 17, 2007 at 11:27:17PM -0700, Kristoffer Ericson wrote:
> Paul, not sure how much comments are wanted or needed. I believe the pm
> code could use it though, since it takes alot of time going through the
> hardware manuals to see whats being done.
> 
Comments for this sort of stuff are good precisely for the reason you
discovered. The more the merrier.

> Also changed STBCR, STBCR2 to the more correct names of sh7709_STBCR... to better comply with the naming scheme.
> 
This is the only thing I don't care for, but this should arguably be more
generic anyways. The rest looks fine.

Re: [PATCH/FIX] - HD64461.H values and comments

[Paul M. <le...@li...>]

On Thu, May 17, 2007 at 10:42:52PM -0700, Kristoffer Ericson wrote:
> Paul, is this patch okey or should it be done with CONFIG_IO_BASE +
> value? So everything can be altered through the menuconfig? I havent
> seen any other boards using hd64461 though.
> 
It's best to leave it as iobase + regoffset. The fundamental problem here
is just the way that the hd64461 is hooked up. Ideally this should be
done as an mfd driver, hp6xx can submit platform devices for the
peripherals it cares about (relative to hd64461), and the rest just goes
away.

The I/O wrapping stuff for trapping peripheral access is crap, and the
remnants of that is what seems to still be causing some issues. We simply
don't want _any_ of this stuff to be stuck in the I/O routines. With
platform devices it's less of a problem these days anyways, since there
aren't many hardcoded assumptions regarding ISA ports, which much of this
was modelled after.

Really all of arch/sh/cchips/ needs to migrate to drivers/mfd/ anyways,
and that should clean up most of the remaining I/O routine abuse. As
you've pointed out, presently there are no hd64465 users, and only 1
hd64461 user. Simple mfd drivers for both will not be too much work, but
it's arguable whether there's any point in bothering with hd64465 or not.
The boards that were depending on it have been long removed already, and
certainly no one is using this part in any new designs.

Re: APM issues

[Kristoffer E. <kri...@gm...>]

On Tue, 15 May 2007 08:26:41 +0900
Paul Mundt <le...@li...> wrote:

> On Mon, May 14, 2007 at 03:58:44PM -0700, Kristoffer Ericson wrote:
> > Bugtracking the hp6xx_apm functions and ran into some question marks. This
> > happend after the apm merger so its not a big suprise. Doesn't seem to be
> > many systems using apm in arch/sh though.
> > 
> Yes, we've started on the SH7722 work tying in to the clock framework,
> but not quite there yet. hp6xx is the only in-tree user of the code at
> the moment, so you get to run in to all of these problems before anyone
> else :-)
> 
> > Problems:
> > 1. Once powerbutton is hit IRQ 32 is generated and never stops
> >    Best approach? Clear request bit? But will that stop anything since a
> > new request will be created before the power button can be released.
> 
> Sounds like it's not acked and masked properly, start debugging the
> irq_chip handler that's got this IRQ.

I've read through the manual and perhaps its due to IRQ0->IRQ3 being set as edge instead of
level. It says in the manual that to clear edge interrupts one needs to  read corresponding bit from IRR0 (1) and then write 0. *shrug* best idea yet. It would explain why a single press would send out interrupts.

They should be set as edge by default, I've done some tests trying to set IRQ0 as level, but no boot. 


> 
> > 2. mutex_lock(&state_lock); from apm-emulation.c seems to freeze the
> > machine. adding a ifndef config_cpu_subsystem..
> >   makes it run abit longer. I noticed that the mutex lock wasn't in the
> > "old" version. Suggestions?
> 
> If it's freezing on a mutex_lock() it means it's blocked while trying to
> acquire the mutex, meaning someone got it beforehand and is never
> releasing it. Some of this could be related to your call path, I'd
> suggest turning on mutex debugging and lockdep and see if anything
> tumbles out.
> 
> > 3. Getting apm: apm queue event overflowed before it freezes (freezes
> > probably due to some mutex locks I've missed),
> >    this would indicate that more than one request is sent by the apm
> > interrupt handler?
> 
> That seems likely, and would also explain the mutex_lock() re-try before
> unlock. Debugging the interrupt handler first makes the most sense.
> 
> > 4. PM_DISK_FIRMWARE is removed, but im not sure if that will be an issue
> > since the pm is handled by board specific code which doesn't require
> > anything to be saved. It simply turns off all clocks besides tmu/rtc and
> > drops power to lcd/pcmcia. Ram shouldn't be cleared.
> > 
> This should not impact you at all, we were basically just abusing the
> definition of PM_DISK_FIRMWARE anyways. The current scheme should be more
> fundamentally correct.
> 
> > In short I need a good way for the interrupt handler to make sure only one
> > request is sent and someway to get rid off / fix the mutex_lock. It would
> > get ugly with alot of ifdefs but dont see any other solution currently.
> 
> If the IRQ is not being masked and acked, that's a serious bug, and one
> that needs to be corrected. It's not worth wasting any time trying to
> limit the number of requests it sends if it's constantly firing anyways
> (ie, you're never going to go to sleep with IRQs running wild).

[PATCH] hp6xx/pm.c cleanup

[Kristoffer E. <kri...@gm...>]

Greetings,

Paul, not sure how much comments are wanted or needed. I believe the pm code could use it though, since it takes alot of time going through the hardware manuals to see whats being done.

patch_text_short:
Trivial patch, adding comments and correcting include/var names.

patch_txt_long
This patch adds some comments in the hp6xx power managment code. Its quite needed in order to understand what its trying to do (or if needing to bugtrack it).
Also changed STBCR, STBCR2 to the more correct names of sh7709_STBCR... to better comply with the naming scheme.
linux/apm.h is replaced with linux/apm-emulation.h

signed-off-by: Kristoffer Ericson <kri...@gm...>

diff --git a/arch/sh/boards/hp6xx/pm.c b/arch/sh/boards/hp6xx/pm.c
index 8143d1b..3c8c086 100644
--- a/arch/sh/boards/hp6xx/pm.c
+++ b/arch/sh/boards/hp6xx/pm.c
@@ -10,14 +10,25 @@
 #include <linux/suspend.h>
 #include <linux/errno.h>
 #include <linux/time.h>
+#include <linux/apm-emulation.h>
 #include <asm/io.h>
 #include <asm/hd64461.h>
 #include <asm/hp6xx.h>
 #include <asm/cpu/dac.h>
 #include <asm/pm.h>
 
-#define STBCR		0xffffff82
-#define STBCR2		0xffffff88
+#define sh7709_STBCR		0xffffff82	/* STBCR  (Standby control register)   */
+#define sh7709_STBCR2		0xffffff88	/* STBCR2 (Standby control register 2) */
+/* 1 = true, 0 = false
+	bit 0 - Clock supply to SCI1 (IRDA) halted
+	bit 1 - Clock supply to SCI2 (SCIF) halted
+	bit 2 - Clock supply to ADC halted and all registers initialized
+	bit 3 - Clock supply to DAC halted
+	bit 4 - Clock supply to DMAC halted
+	bit 5 - Clock supply to UBC is halted
+	bit 6 - Pins MD5 to MD0 are changed in standby mode
+	bit 7 - Reserved
+*/
 
 static int hp6x0_pm_enter(suspend_state_t state)
 {
@@ -28,38 +39,45 @@ static int hp6x0_pm_enter(suspend_state_t state)
 #endif
 
 #ifdef CONFIG_HD64461_ENABLER
-	outb(0, HD64461_PCC1CSCIER);
+	outb(0, HD64461_PCC1CSCIER);		/* Turn off all channel 1 interrupts */
 
-	scr = inb(HD64461_PCC1SCR);
-	scr |= HD64461_PCCSCR_VCC1;
-	outb(scr, HD64461_PCC1SCR);
+	scr = inb(HD64461_PCC1SCR);		/* Channel 1 (PCMCIA) - card Status Change */
+	scr |= HD64461_PCCSCR_VCC1;		/* Channel 1 voltage pin */
+	outb(scr, HD64461_PCC1SCR);		/* Low level power to channel 1 */
 
-	hd64461_stbcr = inw(HD64461_STBCR);
-	hd64461_stbcr |= HD64461_STBCR_SPC1ST;
-	outw(hd64461_stbcr, HD64461_STBCR);
+	hd64461_stbcr = inw(HD64461_STBCR);	/* Save current hd64461 standby control register  */
+	hd64461_stbcr |= HD64461_STBCR_SPC1ST;	/* Stop clocksupply to channel 1  */
+	outw(hd64461_stbcr, HD64461_STBCR);	/* Send it out */
 #endif
 
 	ctrl_outb(0x1f, DACR);
 
-	stbcr = ctrl_inb(STBCR);
-	ctrl_outb(0x01, STBCR);
+	/* Save current state and halt clocksupply to SCI */
+	stbcr = ctrl_inb(sh7709_STBCR);
+	ctrl_outb(0x01, sh7709_STBCR);
 
-	stbcr2 = ctrl_inb(STBCR2);
-	ctrl_outb(0x7f , STBCR2);
+	/* Save current state and drop all clocksupply */
+	stbcr2 = ctrl_inb(sh7709_STBCR2);
+	ctrl_outb(0x7f , sh7709_STBCR2);
 
+	/* Enable all data buses */
 	outw(0xf07f, HD64461_SCPUCR);
 
+	/* Zzzzz */
 	pm_enter();
 
+	/* Wakeup, Lets restore the old values */
 	outw(0, HD64461_SCPUCR);
-	ctrl_outb(stbcr, STBCR);
-	ctrl_outb(stbcr2, STBCR2);
+	ctrl_outb(stbcr, sh7709_STBCR);
+	ctrl_outb(stbcr2, sh7709_STBCR2);
 
 #ifdef CONFIG_HD64461_ENABLER
+	/* Lets activate our channel 1 again */
 	hd64461_stbcr = inw(HD64461_STBCR);
 	hd64461_stbcr &= ~HD64461_STBCR_SPC1ST;
 	outw(hd64461_stbcr, HD64461_STBCR);
 
+	/* turn on all interrupts on channel 1 again */
 	outb(0x4c, HD64461_PCC1CSCIER);
 	outb(0x00, HD64461_PCC1CSCR);
 #endif

[PATCH/FIX] - HD64461.H values and comments

[Kristoffer E. <kri...@gm...>]

Greetings,

Paul, is this patch okey or should it be done with CONFIG_IO_BASE + value? So everything can be
altered through the menuconfig? I havent seen any other boards using hd64461 though.

Best wishes
Kristoffer Ericson

Patch text:
This patch fixes the problem that arose after port2addr was removed. port2addr took a abstract port value and returned the corresponding real *addr.
Since chipset hd64461 no longer uses port2addr we need to supply it with proper real values. These values have been extracted from both the old port2addr function and hd64461 hardware manual reference. Comments have been added to better document functions.

signed-off-by: Kristoffer Ericson <kri...@gm...>

diff --git a/include/asm-sh/hd64461.h b/include/asm-sh/hd64461.h
index 27e5c34..f004c9b 100644
--- a/include/asm-sh/hd64461.h
+++ b/include/asm-sh/hd64461.h
@@ -1,200 +1,241 @@
 #ifndef __ASM_SH_HD64461
 #define __ASM_SH_HD64461
 /*
- *	$Id: hd64461.h,v 1.5 2004/03/16 00:07:51 lethal Exp $
+ *	Copyright (C) 2007 Kristoffer Ericson
+ *	Copyright (C) 2004 Paul Mundt
  *	Copyright (C) 2000 YAEGASHI Takeshi
- *	Hitachi HD64461 companion chip support
+ *
+ *		Hitachi HD64461 companion chip support
+ *	(please note manual reference 0x10000000 = 0xb0000000)
  */
 
 /* Constants for PCMCIA mappings */
-#define HD64461_PCC_WINDOW	0x01000000
-
-#define HD64461_PCC0_BASE	0xb8000000	/* area 6 */
-#define HD64461_PCC0_ATTR	(HD64461_PCC0_BASE)
-#define HD64461_PCC0_COMM	(HD64461_PCC0_BASE+HD64461_PCC_WINDOW)
-#define HD64461_PCC0_IO		(HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)
-
-#define HD64461_PCC1_BASE	0xb4000000	/* area 5 */
-#define HD64461_PCC1_ATTR	(HD64461_PCC1_BASE)
-#define HD64461_PCC1_COMM	(HD64461_PCC1_BASE+HD64461_PCC_WINDOW)
-
-#define HD64461_STBCR	0x10000
-#define HD64461_STBCR_CKIO_STBY			0x2000
-#define HD64461_STBCR_SAFECKE_IST		0x1000
-#define HD64461_STBCR_SLCKE_IST			0x0800
-#define HD64461_STBCR_SAFECKE_OST		0x0400
-#define HD64461_STBCR_SLCKE_OST			0x0200
-#define HD64461_STBCR_SMIAST			0x0100
-#define HD64461_STBCR_SLCDST			0x0080
-#define HD64461_STBCR_SPC0ST			0x0040
-#define HD64461_STBCR_SPC1ST			0x0020
-#define HD64461_STBCR_SAFEST			0x0010
-#define HD64461_STBCR_STM0ST			0x0008
-#define HD64461_STBCR_STM1ST			0x0004
-#define HD64461_STBCR_SIRST				0x0002
-#define HD64461_STBCR_SURTST			0x0001
-
-#define HD64461_SYSCR	0x10002
-#define HD64461_SCPUCR	0x10004
-
-#define HD64461_LCDCBAR		0x11000
-#define HD64461_LCDCLOR		0x11002
-#define HD64461_LCDCCR		0x11004
-#define HD64461_LCDCCR_STBACK	0x0400
-#define HD64461_LCDCCR_STREQ	0x0100
-#define HD64461_LCDCCR_MOFF	0x0080
-#define HD64461_LCDCCR_REFSEL	0x0040
-#define HD64461_LCDCCR_EPON	0x0020
-#define HD64461_LCDCCR_SPON	0x0010
-
-#define	HD64461_LDR1		0x11010
-#define	HD64461_LDR1_DON	0x01
-#define	HD64461_LDR1_DINV	0x80
-
-#define	HD64461_LDR2		0x11012
-#define	HD64461_LDHNCR		0x11014
-#define	HD64461_LDHNSR		0x11016
-#define HD64461_LDVNTR		0x11018
-#define HD64461_LDVNDR		0x1101a
-#define HD64461_LDVSPR		0x1101c
-#define HD64461_LDR3		0x1101e
-
-#define HD64461_CPTWAR		0x11030
-#define HD64461_CPTWDR		0x11032
-#define HD64461_CPTRAR		0x11034
-#define HD64461_CPTRDR		0x11036
-
-#define HD64461_GRDOR		0x11040
-#define HD64461_GRSCR		0x11042
-#define HD64461_GRCFGR		0x11044
-#define HD64461_GRCFGR_ACCSTATUS		0x10
-#define HD64461_GRCFGR_ACCRESET			0x08
-#define HD64461_GRCFGR_ACCSTART_BITBLT	0x06
-#define HD64461_GRCFGR_ACCSTART_LINE	0x04
-#define HD64461_GRCFGR_COLORDEPTH16		0x01
-
-#define HD64461_LNSARH		0x11046
-#define HD64461_LNSARL		0x11048
-#define HD64461_LNAXLR		0x1104a
-#define HD64461_LNDGR		0x1104c
-#define HD64461_LNAXR		0x1104e
-#define HD64461_LNERTR		0x11050
-#define HD64461_LNMDR		0x11052
-#define HD64461_BBTSSARH	0x11054
-#define HD64461_BBTSSARL	0x11056
-#define HD64461_BBTDSARH	0x11058
-#define HD64461_BBTDSARL	0x1105a
-#define HD64461_BBTDWR		0x1105c
-#define HD64461_BBTDHR		0x1105e
-#define HD64461_BBTPARH		0x11060
-#define HD64461_BBTPARL		0x11062
-#define HD64461_BBTMARH		0x11064
-#define HD64461_BBTMARL		0x11066
-#define HD64461_BBTROPR		0x11068
-#define HD64461_BBTMDR		0x1106a
+#define	HD64461_PCC_WINDOW	0x01000000
+
+/* Area 6 - Slot 0 - memory and/or IO card */
+#define	HD64461_PCC0_BASE	0xb8000000
+#define	HD64461_PCC0_ATTR	(HD64461_PCC0_BASE)				/* 0xb80000000 */
+#define	HD64461_PCC0_COMM	(HD64461_PCC0_BASE+HD64461_PCC_WINDOW)		/* 0xb90000000 */
+#define	HD64461_PCC0_IO		(HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)	/* 0xba0000000 */
+
+/* Area 5 - Slot 1 - memory card only */
+#define	HD64461_PCC1_BASE	0xb4000000
+#define	HD64461_PCC1_ATTR	(HD64461_PCC1_BASE)				/* 0xb4000000 */
+#define	HD64461_PCC1_COMM	(HD64461_PCC1_BASE+HD64461_PCC_WINDOW)		/* 0xb5000000 */
+
+/* Standby Control Register for HD64461 */
+#define	HD64461_STBCR			0xb0000000
+#define	HD64461_STBCR_CKIO_STBY		0x2000
+#define	HD64461_STBCR_SAFECKE_IST	0x1000
+#define	HD64461_STBCR_SLCKE_IST		0x0800
+#define	HD64461_STBCR_SAFECKE_OST	0x0400
+#define	HD64461_STBCR_SLCKE_OST		0x0200
+#define	HD64461_STBCR_SMIAST		0x0100
+#define	HD64461_STBCR_SLCDST		0x0080
+#define	HD64461_STBCR_SPC0ST		0x0040
+#define	HD64461_STBCR_SPC1ST		0x0020
+#define	HD64461_STBCR_SAFEST		0x0010
+#define	HD64461_STBCR_STM0ST		0x0008
+#define	HD64461_STBCR_STM1ST		0x0004
+#define	HD64461_STBCR_SIRST		0x0002
+#define	HD64461_STBCR_SURTST		0x0001
+
+/* System Configuration Register */
+#define	HD64461_SYSCR		0xb0000002
+
+/* CPU Data Bus Control Register */
+#define	HD64461_SCPUCR		0xb0000004
+
+/* Base Adress Register */
+#define	HD64461_LCDCBAR		0xb0001000
+
+/* Line increment adress */
+#define	HD64461_LCDCLOR		0xb0001002
+
+/* Controls LCD controller */
+#define	HD64461_LCDCCR		0xb0001004
+
+/* LCCDR control bits */
+#define	HD64461_LCDCCR_STBACK	0x0400	/* Standby Back */
+#define	HD64461_LCDCCR_STREQ	0x0100	/* Standby Request */
+#define	HD64461_LCDCCR_MOFF	0x0080	/* Memory Off */
+#define	HD64461_LCDCCR_REFSEL	0x0040	/* Refresh Select */
+#define	HD64461_LCDCCR_EPON	0x0020	/* End Power On */
+#define	HD64461_LCDCCR_SPON	0x0010	/* Start Power On */
+
+/* Controls LCD (1) */
+#define	HD64461_LDR1		0xb0001010
+#define	HD64461_LDR1_DON	0x01	/* Display On */
+#define	HD64461_LDR1_DINV	0x80	/* Display Invert */
+
+/* Controls LCD (2) */
+#define	HD64461_LDR2		0xb0001012
+#define	HD64461_LDHNCR		0xb0001014	/* Number of horizontal characters */
+#define	HD64461_LDHNSR		0xb0001016	/* Specify output start position + width of CL1 */
+#define	HD64461_LDVNTR		0xb0001018	/* Specify total vertical lines */
+#define	HD64461_LDVNDR		0xb000101a	/* specify number of display vertical lines */
+#define	HD64461_LDVSPR		0xb000101c	/* specify vertical synchronization pos and AC nr */
+
+/* Controls LCD (3) */
+#define	HD64461_LDR3		0xb000101e
+
+/* Palette Registers */
+#define	HD64461_CPTWAR		0xb0001030	/* Color Palette Write Adress Register */
+#define	HD64461_CPTWDR		0xb0001032	/* Color Palette Write Data Register */
+#define	HD64461_CPTRAR		0xb0001034	/* Color Palette Read Adress Register */
+#define	HD64461_CPTRDR		0xb0001036	/* Color Palette Read Data Register */
+
+#define	HD64461_GRDOR		0xb0001040	/* Display Resolution Offset Register */
+#define	HD64461_GRSCR		0xb0001042	/* Solid Color Register */
+#define	HD64461_GRCFGR		0xb0001044	/* Accelerator Configuration Register */
+
+#define	HD64461_GRCFGR_ACCSTATUS	0x10	/* Accelerator Status */
+#define	HD64461_GRCFGR_ACCRESET		0x08	/* Accelerator Reset */
+#define	HD64461_GRCFGR_ACCSTART_BITBLT	0x06	/* Accelerator Start BITBLT */
+#define	HD64461_GRCFGR_ACCSTART_LINE	0x04	/* Accelerator Start Line Drawing */
+#define	HD64461_GRCFGR_COLORDEPTH16	0x01	/* Sets Colordepth 16 for Accelerator */
+#define	HD64461_GRCFGR_COLORDEPTH8	0x01	/* Sets Colordepth 8 for Accelerator */
+
+/* Line Drawing Registers */
+#define	HD64461_LNSARH		0xb0001046	/* Line Start Adress Register (H) */
+#define	HD64461_LNSARL		0xb0001048	/* Line Start Adress Register (L) */
+#define	HD64461_LNAXLR		0xb000104a	/* Axis Pixel Length Register */
+#define	HD64461_LNDGR		0xb000104c	/* Diagonal Register */
+#define	HD64461_LNAXR		0xb000104e	/* Axial Register */
+#define	HD64461_LNERTR		0xb0001050	/* Start Error Term Register */
+#define	HD64461_LNMDR		0xb0001052	/* Line Mode Register */
+
+/* BitBLT Registers */
+#define	HD64461_BBTSSARH	0xb0001054	/* Source Start Adress Register (H) */
+#define	HD64461_BBTSSARL	0xb0001056	/* Source Start Adress Register (L) */
+#define	HD64461_BBTDSARH	0xb0001058	/* Destination Start Adress Register (H) */
+#define	HD64461_BBTDSARL	0xb000105a	/* Destination Start Adress Register (L) */
+#define	HD64461_BBTDWR		0xb000105c	/* Destination Block Width Register */
+#define	HD64461_BBTDHR		0xb000105e	/* Destination Block Height Register */
+#define	HD64461_BBTPARH		0xb0001060	/* Pattern Start Adress Register (H) */
+#define	HD64461_BBTPARL		0xb0001062	/* Pattern Start Adress Register (L) */
+#define	HD64461_BBTMARH		0xb0001064	/* Mask Start Adress Register (H) */
+#define	HD64461_BBTMARL		0xb0001066	/* Mask Start Adress Register (L) */
+#define	HD64461_BBTROPR		0xb0001068	/* ROP Register */
+#define	HD64461_BBTMDR		0xb000106a	/* BitBLT Mode Register */
 
 /* PC Card Controller Registers */
-#define HD64461_PCC0ISR         0x12000 /* socket 0 interface status */
-#define HD64461_PCC0GCR         0x12002 /* socket 0 general control */
-#define HD64461_PCC0CSCR        0x12004 /* socket 0 card status change */
-#define HD64461_PCC0CSCIER      0x12006 /* socket 0 card status change interrupt enable */
-#define HD64461_PCC0SCR         0x12008 /* socket 0 software control */
-#define HD64461_PCC1ISR         0x12010 /* socket 1 interface status */
-#define HD64461_PCC1GCR         0x12012 /* socket 1 general control */
-#define HD64461_PCC1CSCR        0x12014 /* socket 1 card status change */
-#define HD64461_PCC1CSCIER      0x12016 /* socket 1 card status change interrupt enable */
-#define HD64461_PCC1SCR         0x12018 /* socket 1 software control */
+/* Maps to Physical Area 6 */
+#define	HD64461_PCC0ISR		0xb0002000	/* socket 0 interface status */
+#define	HD64461_PCC0GCR		0xb0002002	/* socket 0 general control */
+#define	HD64461_PCC0CSCR	0xb0002004	/* socket 0 card status change */
+#define	HD64461_PCC0CSCIER	0xb0002006	/* socket 0 card status change interrupt enable */
+#define	HD64461_PCC0SCR		0xb0002008	/* socket 0 software control */
+/* Maps to Physical Area 5 */
+#define	HD64461_PCC1ISR		0xb0002010	/* socket 1 interface status */
+#define	HD64461_PCC1GCR		0xb0002012	/* socket 1 general control */
+#define	HD64461_PCC1CSCR	0xb0002014	/* socket 1 card status change */
+#define	HD64461_PCC1CSCIER	0xb0002016	/* socket 1 card status change interrupt enable */
+#define	HD64461_PCC1SCR		0xb0002018	/* socket 1 software control */
 
 /* PCC Interface Status Register */
-#define HD64461_PCCISR_READY		0x80	/* card ready */
-#define HD64461_PCCISR_MWP		0x40	/* card write-protected */
-#define HD64461_PCCISR_VS2		0x20	/* voltage select pin 2 */
-#define HD64461_PCCISR_VS1		0x10	/* voltage select pin 1 */
-#define HD64461_PCCISR_CD2		0x08	/* card detect 2 */
-#define HD64461_PCCISR_CD1		0x04	/* card detect 1 */
-#define HD64461_PCCISR_BVD2		0x02	/* battery 1 */
-#define HD64461_PCCISR_BVD1		0x01	/* battery 1 */
-
-#define HD64461_PCCISR_PCD_MASK		0x0c    /* card detect */
-#define HD64461_PCCISR_BVD_MASK		0x03    /* battery voltage */
-#define HD64461_PCCISR_BVD_BATGOOD	0x03    /* battery good */
-#define HD64461_PCCISR_BVD_BATWARN	0x01    /* battery low warning */
-#define HD64461_PCCISR_BVD_BATDEAD1	0x02    /* battery dead */
-#define HD64461_PCCISR_BVD_BATDEAD2	0x00    /* battery dead */
+#define	HD64461_PCCISR_READY		0x80	/* card ready */
+#define	HD64461_PCCISR_MWP		0x40	/* card write-protected */
+#define	HD64461_PCCISR_VS2		0x20	/* voltage select pin 2 */
+#define	HD64461_PCCISR_VS1		0x10	/* voltage select pin 1 */
+#define	HD64461_PCCISR_CD2		0x08	/* card detect 2 */
+#define	HD64461_PCCISR_CD1		0x04	/* card detect 1 */
+#define	HD64461_PCCISR_BVD2		0x02	/* battery 1 */
+#define	HD64461_PCCISR_BVD1		0x01	/* battery 1 */
+
+#define	HD64461_PCCISR_PCD_MASK		0x0c	/* card detect */
+#define	HD64461_PCCISR_BVD_MASK		0x03	/* battery voltage */
+#define	HD64461_PCCISR_BVD_BATGOOD	0x03	/* battery good */
+#define	HD64461_PCCISR_BVD_BATWARN	0x01	/* battery low warning */
+#define	HD64461_PCCISR_BVD_BATDEAD1	0x02	/* battery dead */
+#define	HD64461_PCCISR_BVD_BATDEAD2	0x00	/* battery dead */
 
 /* PCC General Control Register */
-#define HD64461_PCCGCR_DRVE		0x80    /* output drive */
-#define HD64461_PCCGCR_PCCR		0x40    /* PC card reset */
-#define HD64461_PCCGCR_PCCT		0x20    /* PC card type, 1=IO&mem, 0=mem */
-#define HD64461_PCCGCR_VCC0		0x10    /* voltage control pin VCC0SEL0 */
-#define HD64461_PCCGCR_PMMOD		0x08    /* memory mode */
-#define HD64461_PCCGCR_PA25		0x04    /* pin A25 */
-#define HD64461_PCCGCR_PA24		0x02    /* pin A24 */
-#define HD64461_PCCGCR_REG		0x01    /* pin PCC0REG# */
+#define	HD64461_PCCGCR_DRVE		0x80	/* output drive */
+#define	HD64461_PCCGCR_PCCR		0x40	/* PC card reset */
+#define	HD64461_PCCGCR_PCCT		0x20	/* PC card type, 1=IO&mem, 0=mem */
+#define	HD64461_PCCGCR_VCC0		0x10	/* voltage control pin VCC0SEL0 */
+#define	HD64461_PCCGCR_PMMOD		0x08	/* memory mode */
+#define	HD64461_PCCGCR_PA25		0x04	/* pin A25 */
+#define	HD64461_PCCGCR_PA24		0x02	/* pin A24 */
+#define	HD64461_PCCGCR_REG		0x01	/* pin PCC0REG# */
 
 /* PCC Card Status Change Register */
-#define HD64461_PCCCSCR_SCDI		0x80    /* sw card detect intr */
-#define HD64461_PCCCSCR_SRV1		0x40    /* reserved */
-#define HD64461_PCCCSCR_IREQ		0x20    /* IREQ intr req */
-#define HD64461_PCCCSCR_SC		0x10    /* STSCHG (status change) pin */
-#define HD64461_PCCCSCR_CDC		0x08    /* CD (card detect) change */
-#define HD64461_PCCCSCR_RC		0x04    /* READY change */
-#define HD64461_PCCCSCR_BW		0x02    /* battery warning change */
-#define HD64461_PCCCSCR_BD		0x01    /* battery dead change */
+#define	HD64461_PCCCSCR_SCDI		0x80	/* sw card detect intr */
+#define	HD64461_PCCCSCR_SRV1		0x40	/* reserved */
+#define	HD64461_PCCCSCR_IREQ		0x20	/* IREQ intr req */
+#define	HD64461_PCCCSCR_SC		0x10	/* STSCHG (status change) pin */
+#define	HD64461_PCCCSCR_CDC		0x08	/* CD (card detect) change */
+#define	HD64461_PCCCSCR_RC		0x04	/* READY change */
+#define	HD64461_PCCCSCR_BW		0x02	/* battery warning change */
+#define	HD64461_PCCCSCR_BD		0x01	/* battery dead change */
 
 /* PCC Card Status Change Interrupt Enable Register */
-#define HD64461_PCCCSCIER_CRE		0x80    /* change reset enable */
-#define HD64461_PCCCSCIER_IREQE_MASK	0x60   /* IREQ enable */
-#define HD64461_PCCCSCIER_IREQE_DISABLED	0x00   /* IREQ disabled */
-#define HD64461_PCCCSCIER_IREQE_LEVEL	0x20   /* IREQ level-triggered */
-#define HD64461_PCCCSCIER_IREQE_FALLING	0x40   /* IREQ falling-edge-trig */
-#define HD64461_PCCCSCIER_IREQE_RISING	0x60   /* IREQ rising-edge-trig */
-
-#define HD64461_PCCCSCIER_SCE		0x10    /* status change enable */
-#define HD64461_PCCCSCIER_CDE		0x08    /* card detect change enable */
-#define HD64461_PCCCSCIER_RE		0x04    /* ready change enable */
-#define HD64461_PCCCSCIER_BWE		0x02    /* battery warn change enable */
-#define HD64461_PCCCSCIER_BDE		0x01    /* battery dead change enable*/
+#define	HD64461_PCCCSCIER_CRE		0x80	/* change reset enable */
+#define	HD64461_PCCCSCIER_IREQE_MASK	0x60	/* IREQ enable */
+#define	HD64461_PCCCSCIER_IREQE_DISABLED 0x00	/* IREQ disabled */
+#define	HD64461_PCCCSCIER_IREQE_LEVEL	0x20	/* IREQ level-triggered */
+#define	HD64461_PCCCSCIER_IREQE_FALLING	0x40	/* IREQ falling-edge-trig */
+#define	HD64461_PCCCSCIER_IREQE_RISING	0x60	/* IREQ rising-edge-trig */
+
+#define	HD64461_PCCCSCIER_SCE		0x10	/* status change enable */
+#define	HD64461_PCCCSCIER_CDE		0x08	/* card detect change enable */
+#define	HD64461_PCCCSCIER_RE		0x04	/* ready change enable */
+#define	HD64461_PCCCSCIER_BWE		0x02	/* battery warn change enable */
+#define	HD64461_PCCCSCIER_BDE		0x01	/* battery dead change enable*/
 
 /* PCC Software Control Register */
-#define HD64461_PCCSCR_VCC1		0x02	/* voltage control pin 1 */
-#define HD64461_PCCSCR_SWP		0x01    /* write protect */
-
-#define HD64461_P0OCR           0x1202a
-#define HD64461_P1OCR           0x1202c
-#define HD64461_PGCR            0x1202e
-
-#define HD64461_GPACR		0x14000
-#define HD64461_GPBCR		0x14002
-#define HD64461_GPCCR		0x14004
-#define HD64461_GPDCR		0x14006
-#define HD64461_GPADR		0x14010
-#define HD64461_GPBDR		0x14012
-#define HD64461_GPCDR		0x14014
-#define HD64461_GPDDR		0x14016
-#define HD64461_GPAICR		0x14020
-#define HD64461_GPBICR		0x14022
-#define HD64461_GPCICR		0x14024
-#define HD64461_GPDICR		0x14026
-#define HD64461_GPAISR		0x14040
-#define HD64461_GPBISR		0x14042
-#define HD64461_GPCISR		0x14044
-#define HD64461_GPDISR		0x14046
-
-#define HD64461_NIRR		0x15000
-#define HD64461_NIMR		0x15002
-
-#define HD64461_IRQBASE		OFFCHIP_IRQ_BASE
-#define HD64461_IRQ_NUM		16
-
-#define HD64461_IRQ_UART	(HD64461_IRQBASE+5)
-#define HD64461_IRQ_IRDA	(HD64461_IRQBASE+6)
-#define HD64461_IRQ_TMU1	(HD64461_IRQBASE+9)
-#define HD64461_IRQ_TMU0	(HD64461_IRQBASE+10)
-#define HD64461_IRQ_GPIO	(HD64461_IRQBASE+11)
-#define HD64461_IRQ_AFE		(HD64461_IRQBASE+12)
-#define HD64461_IRQ_PCC1	(HD64461_IRQBASE+13)
-#define HD64461_IRQ_PCC0	(HD64461_IRQBASE+14)
+#define	HD64461_PCCSCR_VCC1		0x02	/* voltage control pin 1 */
+#define	HD64461_PCCSCR_SWP		0x01	/* write protect */
+
+/* PCC0 Output Pins Control Register */
+#define	HD64461_P0OCR		0xb000202a
+
+/* PCC1 Output Pins Control Register */
+#define	HD64461_P1OCR		0xb000202c
+
+/* PC Card General Control Register */
+#define	HD64461_PGCR		0xb000202e
+
+/* Port Control Registers */
+#define	HD64461_GPACR		0xb0004000	/* Port A - Handles IRDA/TIMER */
+#define	HD64461_GPBCR		0xb0004002	/* Port B - Handles UART */
+#define	HD64461_GPCCR		0xb0004004	/* Port C - Handles PCMCIA 1 */
+#define	HD64461_GPDCR		0xb0004006	/* Port D - Handles PCMCIA 1 */
+
+/* Port Control Data Registers */
+#define	HD64461_GPADR		0xb0004010	/* A */
+#define	HD64461_GPBDR		0xb0004012	/* B */
+#define	HD64461_GPCDR		0xb0004014	/* C */
+#define	HD64461_GPDDR		0xb0004016	/* D */
+
+/* Interrupt Control Registers */
+#define	HD64461_GPAICR		0xb0004020	/* A */
+#define	HD64461_GPBICR		0xb0004022	/* B */
+#define	HD64461_GPCICR		0xb0004024	/* C */
+#define	HD64461_GPDICR		0xb0004026	/* D */
+
+/* Interrupt Status Registers */
+#define	HD64461_GPAISR		0xb0004040	/* A */
+#define	HD64461_GPBISR		0xb0004042	/* B */
+#define	HD64461_GPCISR		0xb0004044	/* C */
+#define	HD64461_GPDISR		0xb0004046	/* D */
+
+/* Interrupt Request Register & Interrupt Mask Register */
+#define	HD64461_NIRR		0xb0005000
+#define	HD64461_NIMR		0xb0005002
+
+#define	HD64461_IRQBASE		OFFCHIP_IRQ_BASE
+#define	HD64461_IRQ_NUM		16
+
+#define	HD64461_IRQ_UART	(HD64461_IRQBASE+5)
+#define	HD64461_IRQ_IRDA	(HD64461_IRQBASE+6)
+#define	HD64461_IRQ_TMU1	(HD64461_IRQBASE+9)
+#define	HD64461_IRQ_TMU0	(HD64461_IRQBASE+10)
+#define	HD64461_IRQ_GPIO	(HD64461_IRQBASE+11)
+#define	HD64461_IRQ_AFE		(HD64461_IRQBASE+12)
+#define	HD64461_IRQ_PCC1	(HD64461_IRQBASE+13)
+#define	HD64461_IRQ_PCC0	(HD64461_IRQBASE+14)
 
 #define __IO_PREFIX	hd64461
 #include <asm/io_generic.h>