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|
From: EXTERNAL B. M. (P. ST-FIR/Eng) <ext...@de...> - 2007-08-13 15:37:59
|
Hi Magnus, thanks for the new priority feature. There are 3 things I noticed. First:=20 The declaration of the new function should probably go to hw_irq.h. Second: Is it forbidden to set the highest possible priority? If not there is a bug in set_priority. if (prio >=3D ((1 << _INTC_WIDTH(ihp->handle)) - 1)) Third: The code doesn't work for processors without mask registers. If the processor only has priority registers the "handle" will not be set in intc_register_irq (because of "if(!primary)") This leads to wrong results from _INTC_WIDTH, which causes intc_set_priority fail with EINVAL When I comment out the "if(!primary)" condition all priorities will be set immediatelly, which also enables them. When I hardcode the _INTC_WIDTH to the correct size in set_priority, the priority will be set as soon as the irq is requested. Regards Markus |
|
From: Magnus D. <mag...@gm...> - 2007-08-13 02:49:57
|
Hi Markus! On 8/10/07, EXTERNAL Brunner Markus (Praktikant; ST-FIR/Eng) <ext...@de...> wrote: > Hi, > > I have fixed the error now. Great! Sorry for not responding earlier. > It was caused by the smc911x driver it requested the irq with > IRQF_TRIGGER_FALLING and overwrote my settings in the board setup. > After changing this to LOW it worked. I wonder if it would make sense to extend the interrupt api to provide a bitmap of all supported sense configurations supported by the driver... That way the driver would tell the interrupt controller which configurations it supports and it's up to the interrupt controller pick one of them. Then the driver reads back which configuration that was selected by the interrupt controller and sets up the hardware it controls accordingly. Or maybe that is too complicated, I'm not sure. But the current framework seems a bit too limited IMO, especially if the interrupt controller only supports a certain sense configuration. The best solution may be the other way around though, where the interrupt controller provides a bitmap of supported sense configurations that the driver may choose from... / magnus |
|
From: Magnus D. <mag...@gm...> - 2007-08-13 02:31:22
|
On 8/12/07, Paul Mundt <le...@li...> wrote: > On Fri, Aug 10, 2007 at 08:31:55PM +0900, Magnus Damm wrote: > > sh: x3 - fix setup_bootmem_node() compile error with shx3_defconfig > > On Fri, Aug 10, 2007 at 08:41:43PM +0900, Magnus Damm wrote: > > sh: intc - add a clear register to struct intc_prio_reg > > On Fri, Aug 10, 2007 at 08:53:17PM +0900, Magnus Damm wrote: > > sh: intc - rework core code > > On Fri, Aug 10, 2007 at 09:05:24PM +0900, Magnus Damm wrote: > > sh: intc - convert board specific r2d code V2 > > On Fri, Aug 10, 2007 at 09:10:27PM +0900, Magnus Damm wrote: > > sh: replace sh specific CONFIG_VOYAGERGX with CONFIG_MFD_SM501 > > On Fri, Aug 10, 2007 at 09:17:18PM +0900, Magnus Damm wrote: > > sh: x3 - add ipi vectors > > These have been applied and pushed out, thanks. Great, thank you! > A few minor nits.. there was quite a bit of whitespace damage and other > bits that checkpatch complained rather loudly about. Please remember to > run the patches through that first so I don't have to clean them up by > hand. While checkpatch does have a tendency to be stupid about some > things, it does catch some fairly obvious stuff. In general, if > checkpatch is happy, I'm happy. Oh, right... I checked all my previous patches with checkpatch, but with this batch I was in a hurry and forgot that step. Sorry about that, I'll try to remember that in the future. I don't want to give you boring whitespace work... =) > Now that the R2D stuff is split up, you should provide updated defconfigs > for both versions, rts7751r2d_defconfig should match the default choice > for the board version (though it might be less ambiguous if we were to > rename that particular defconfig to something closer to the config names). Yep, good idea. I'll cook up a patch for that. / magnus |
|
From: Magnus D. <mag...@gm...> - 2007-08-13 02:26:34
|
On 8/10/07, Paul Mundt <le...@li...> wrote:
> On Fri, Aug 10, 2007 at 08:59:04PM +0900, Magnus Damm wrote:
> > @@ -57,8 +57,8 @@ static struct intc_mask_reg mask_registe
> > 0, UH, 0, 0, TWOD, ZD, PV, CI } },
> > };
> >
> > -static DECLARE_INTC_DESC(intc_desc, "voyagergx", vectors,
> > - NULL, NULL, mask_registers, NULL, NULL);
> > +static __initdata DECLARE_INTC_DESC(intc_desc, "voyagergx", vectors,
> > + NULL, NULL, mask_registers, NULL, NULL);
> >
> > static unsigned int voyagergx_stat2irq[32] = {
> > IRQ_SM501_CI, IRQ_SM501_PV, IRQ_SM501_ZD, IRQ_SM501_2D,
>
> I wonder if it makes more sense to include __initdata in the
> DECLARE_INTC_DESC() itself? Is there ever going to be a situation where
> it's not going to be initdata now that you're copying them out anyways?
Including the __initdata in DECLARE_INTC_DESC() makes sense. I'll
resend in a bit.
Thanks!
/ magnus
|
|
From: Kristoffer E. <kri...@gm...> - 2007-08-12 22:08:55
|
Hey all, I opened up a HP 620LX provided by a friend and it does indeed look like SH7709 is the processor inside. Some hardware data: (CHIP 1) "9750FXS" "HD64461F" "TAIWAN" "ITE" "MBA300" (CHIP 2) "SH-3 7M3/F80" "HD6417709" "JAPAN" So, need to rethink why stuff doesnt work on wince 2.0 machines. /Kristoffer -- Kristoffer Ericson <Kri...@Gm...> |
|
From: Paul M. <le...@li...> - 2007-08-12 06:46:13
|
On Fri, Aug 10, 2007 at 08:31:55PM +0900, Magnus Damm wrote: > sh: x3 - fix setup_bootmem_node() compile error with shx3_defconfig On Fri, Aug 10, 2007 at 08:41:43PM +0900, Magnus Damm wrote: > sh: intc - add a clear register to struct intc_prio_reg On Fri, Aug 10, 2007 at 08:53:17PM +0900, Magnus Damm wrote: > sh: intc - rework core code On Fri, Aug 10, 2007 at 09:05:24PM +0900, Magnus Damm wrote: > sh: intc - convert board specific r2d code V2 On Fri, Aug 10, 2007 at 09:10:27PM +0900, Magnus Damm wrote: > sh: replace sh specific CONFIG_VOYAGERGX with CONFIG_MFD_SM501 On Fri, Aug 10, 2007 at 09:17:18PM +0900, Magnus Damm wrote: > sh: x3 - add ipi vectors These have been applied and pushed out, thanks. A few minor nits.. there was quite a bit of whitespace damage and other bits that checkpatch complained rather loudly about. Please remember to run the patches through that first so I don't have to clean them up by hand. While checkpatch does have a tendency to be stupid about some things, it does catch some fairly obvious stuff. In general, if checkpatch is happy, I'm happy. Now that the R2D stuff is split up, you should provide updated defconfigs for both versions, rts7751r2d_defconfig should match the default choice for the board version (though it might be less ambiguous if we were to rename that particular defconfig to something closer to the config names). |
|
From: Paul M. <le...@li...> - 2007-08-10 12:21:01
|
On Fri, Aug 10, 2007 at 08:59:04PM +0900, Magnus Damm wrote:
> @@ -57,8 +57,8 @@ static struct intc_mask_reg mask_registe
> 0, UH, 0, 0, TWOD, ZD, PV, CI } },
> };
>
> -static DECLARE_INTC_DESC(intc_desc, "voyagergx", vectors,
> - NULL, NULL, mask_registers, NULL, NULL);
> +static __initdata DECLARE_INTC_DESC(intc_desc, "voyagergx", vectors,
> + NULL, NULL, mask_registers, NULL, NULL);
>
> static unsigned int voyagergx_stat2irq[32] = {
> IRQ_SM501_CI, IRQ_SM501_PV, IRQ_SM501_ZD, IRQ_SM501_2D,
I wonder if it makes more sense to include __initdata in the
DECLARE_INTC_DESC() itself? Is there ever going to be a situation where
it's not going to be initdata now that you're copying them out anyways?
|
|
From: Magnus D. <mag...@gm...> - 2007-08-10 12:19:10
|
sh: x3 - add ipi vectors
With the intc dual prio register support in place it is now possible to add
the ipi vectors to x3.
Signed-off-by: Magnus Damm <da...@ig...>
---
arch/sh/kernel/cpu/sh4a/setup-shx3.c | 9 +++++++++
1 file changed, 9 insertions(+)
--- 0005/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-shx3.c 2007-08-10 21:12:59.000000000 +0900
@@ -89,6 +89,8 @@ enum {
FE0, FE1,
GPIO0, GPIO1, GPIO2, GPIO3,
PAM, IRM,
+ INTICI0, INTICI1, INTICI2, INTICI3,
+ INTICI4, INTICI5, INTICI6, INTICI7,
/* interrupt groups */
IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
@@ -137,6 +139,10 @@ static struct intc_vect vectors[] __init
INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0),
+ INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
+ INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
+ INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
+ INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
};
static struct intc_group groups[] __initdata = {
@@ -207,6 +213,9 @@ static struct intc_prio_reg prio_registe
VIN1, VIN0, IIC, DU} },
{ 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
GPIO2, GPIO1, GPIO0, IRM } },
+ { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
+ { INTICI7, INTICI6, INTICI5, INTICI4,
+ INTICI3, INTICI2, INTICI1, INTICI0 } },
};
static __initdata DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups,
|
|
From: Magnus D. <mag...@gm...> - 2007-08-10 12:12:28
|
sh: replace sh specific CONFIG_VOYAGERGX with CONFIG_MFD_SM501
This patch replaces all instances of CONFIG_VOYAGERGX with CONFIG_MFD_SM501.
While at it we make sure the r2d code compiles both with and without SM501.
Signed-off-by: Magnus Damm <da...@ig...>
---
arch/sh/Makefile | 2 -
arch/sh/boards/renesas/rts7751r2d/irq.c | 2 +
arch/sh/boards/renesas/rts7751r2d/setup.c | 39 ++++++++++++++++-------------
arch/sh/cchips/Kconfig | 13 ---------
4 files changed, 25 insertions(+), 31 deletions(-)
--- 0001/arch/sh/Makefile
+++ work/arch/sh/Makefile 2007-08-09 12:02:06.000000000 +0900
@@ -120,7 +120,7 @@ endif
# Companion chips
core-$(CONFIG_HD6446X_SERIES) += arch/sh/cchips/hd6446x/
-core-$(CONFIG_VOYAGERGX) += arch/sh/cchips/voyagergx/
+core-$(CONFIG_MFD_SM501) += arch/sh/cchips/voyagergx/
cpuincdir-$(CONFIG_CPU_SH2) := cpu-sh2
cpuincdir-$(CONFIG_CPU_SH2A) := cpu-sh2a
--- 0007/arch/sh/boards/renesas/rts7751r2d/irq.c
+++ work/arch/sh/boards/renesas/rts7751r2d/irq.c 2007-08-09 12:00:22.000000000 +0900
@@ -153,5 +153,7 @@ void __init init_rts7751r2d_IRQ(void)
}
register_intc_controller(d);
+#ifdef CONFIG_MFD_SM501
setup_voyagergx_irq();
+#endif
}
--- 0007/arch/sh/boards/renesas/rts7751r2d/setup.c
+++ work/arch/sh/boards/renesas/rts7751r2d/setup.c 2007-08-09 12:00:07.000000000 +0900
@@ -73,6 +73,22 @@ static struct platform_device cf_ide_dev
},
};
+static struct resource heartbeat_resources[] = {
+ [0] = {
+ .start = PA_OUTPORT,
+ .end = PA_OUTPORT + 8 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device heartbeat_device = {
+ .name = "heartbeat",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(heartbeat_resources),
+ .resource = heartbeat_resources,
+};
+
+#ifdef CONFIG_MFD_SM501
static struct plat_serial8250_port uart_platform_data[] = {
{
.membase = (void __iomem *)VOYAGER_UART_BASE,
@@ -94,21 +110,6 @@ static struct platform_device uart_devic
},
};
-static struct resource heartbeat_resources[] = {
- [0] = {
- .start = PA_OUTPORT,
- .end = PA_OUTPORT + 8 - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device heartbeat_device = {
- .name = "heartbeat",
- .id = -1,
- .num_resources = ARRAY_SIZE(heartbeat_resources),
- .resource = heartbeat_resources,
-};
-
static struct resource sm501_resources[] = {
[0] = {
.start = 0x10000000,
@@ -133,10 +134,14 @@ static struct platform_device sm501_devi
.resource = sm501_resources,
};
+#endif /* CONFIG_MFD_SM501 */
+
static struct platform_device *rts7751r2d_devices[] __initdata = {
+#ifdef CONFIG_MFD_SM501
&uart_device,
- &heartbeat_device,
&sm501_device,
+#endif
+ &heartbeat_device,
};
static int __init rts7751r2d_devices_setup(void)
@@ -187,7 +192,7 @@ static struct sh_machine_vector mv_rts77
.mv_init_irq = init_rts7751r2d_IRQ,
.mv_irq_demux = rts7751r2d_irq_demux,
-#ifdef CONFIG_USB_SM501
+#if defined (CONFIG_MFD_SM501) && defined(CONFIG_USB_OHCI_HCD)
.mv_consistent_alloc = voyagergx_consistent_alloc,
.mv_consistent_free = voyagergx_consistent_free,
#endif
--- 0001/arch/sh/cchips/Kconfig
+++ work/arch/sh/cchips/Kconfig 2007-08-09 11:58:19.000000000 +0900
@@ -1,18 +1,5 @@
menu "Companion Chips"
-config VOYAGERGX
- bool "VoyagerGX chip support"
- depends on SH_RTS7751R2D
- help
- Selecting this option will support Silicon Motion, Inc. SM501.
- Designed to complement needs for the embedded industry, it
- provides video and 2D capability. To reduce system cost a
- wide variety of include I/O is supported, including analog RGB
- and digital LCD Panel interface, 8-bit parallel interface, USB,
- UART, IrDA, Zoom Video, AC97 or I2S, SSP, PWM, and I2C. There
- are additional GPIO bits that can be used to interface to
- external as well.
-
config HD6446X_SERIES
bool
|
|
From: Magnus D. <mag...@gm...> - 2007-08-10 12:07:23
|
sh: intc - convert board specific r2d code V2
This patch converts the board specific interrupt code for r2d to make use of
intc. While at it we improve the Kconfig to avoid confusion.
- Two sets of interrupt tables exist - one for R2D-1 and one for R2D-PLUS.
- R2D-1 and R2D-PLUS use the same irq constants.
- R2D-1 has AX88796 support, R2D-PLUS does not hook up that IRQ.
- R2D-PLUS has KEY support, R2D-1 does not hook up that IRQ.
- The number and order of IRQ values are disconnected from register bits.
- Interrupt sources now start from IRQ 100.
- The machvec demux function converts from irlm IRQ 0-14 to IRQ 100++.
Tested on R2D-1 and R2D-PLUS boards.
Version 2 adds CONFIG_RTS7751R2D_1 and CONFIG_RTS7751R2D_PLUS together with
intc structured as __initdata.
Signed-off-by: Magnus Damm <da...@ig...>
---
arch/sh/boards/renesas/rts7751r2d/Kconfig | 24 +++-
arch/sh/boards/renesas/rts7751r2d/irq.c | 171 ++++++++++++++++++++---------
arch/sh/boards/renesas/rts7751r2d/setup.c | 8 -
arch/sh/drivers/pci/ops-rts7751r2d.c | 8 -
include/asm-sh/rts7751r2d.h | 65 +++++------
5 files changed, 180 insertions(+), 96 deletions(-)
--- 0001/arch/sh/boards/renesas/rts7751r2d/Kconfig
+++ work/arch/sh/boards/renesas/rts7751r2d/Kconfig 2007-08-09 11:20:43.000000000 +0900
@@ -2,10 +2,28 @@ if SH_RTS7751R2D
menu "RTS7751R2D options"
-config RTS7751R2D_REV11
- bool "RTS7751R2D Rev. 1.1 board support"
+choice
+ prompt "R2D Board Revision"
+ default RTS7751R2D_PLUS
+
+config RTS7751R2D_PLUS
+ bool "R2D-PLUS"
+ help
+ Selecting this option will configure the kernel for R2D-PLUS.
+
+ R2D-PLUS is the smaller of the two R2D board versions, equipped
+ with a single PCI slot.
+
+config RTS7751R2D_1
+ bool "R2D-1"
help
- Selecting this option will support version rev. 1.1.
+ Selecting this option will configure the kernel for R2D-1.
+
+ R2D-1 is the larger of the two R2D board versions, equipped
+ with two PCI slots.
+
+endchoice
+
endmenu
endif
--- 0001/arch/sh/boards/renesas/rts7751r2d/irq.c
+++ work/arch/sh/boards/renesas/rts7751r2d/irq.c 2007-08-09 11:23:43.000000000 +0900
@@ -1,9 +1,10 @@
/*
* linux/arch/sh/boards/renesas/rts7751r2d/irq.c
*
+ * Copyright (C) 2007 Magnus Damm
* Copyright (C) 2000 Kazumoto Kojima
*
- * Renesas Technology Sales RTS7751R2D Support.
+ * Renesas Technology Sales RTS7751R2D Support, R2D-PLUS and R2D-1.
*
* Modified for RTS7751R2D by
* Atom Create Engineering Co., Ltd. 2002.
@@ -16,67 +17,141 @@
#include <asm/voyagergx.h>
#include <asm/rts7751r2d.h>
-#if defined(CONFIG_RTS7751R2D_REV11)
-static int mask_pos[] = {11, 9, 8, 12, 10, 6, 5, 4, 7, 14, 13, 0, 0, 0, 0};
-#else
-static int mask_pos[] = {6, 11, 9, 8, 12, 10, 5, 4, 7, 14, 13, 0, 0, 0, 0};
-#endif
+#define R2D_NR_IRL 13
-static void enable_rts7751r2d_irq(unsigned int irq)
-{
- /* Set priority in IPR back to original value */
- ctrl_outw(ctrl_inw(IRLCNTR1) | (1 << mask_pos[irq]), IRLCNTR1);
-}
+enum {
+ UNUSED = 0,
-static void disable_rts7751r2d_irq(unsigned int irq)
-{
- /* Set the priority in IPR to 0 */
- ctrl_outw(ctrl_inw(IRLCNTR1) & (0xffff ^ (1 << mask_pos[irq])),
- IRLCNTR1);
-}
+ /* board specific interrupt sources (R2D-1 and R2D-PLUS) */
+ EXT, /* EXT_INT0-3 */
+ RTC_T, RTC_A, /* Real Time Clock */
+ AX88796, /* Ethernet controller (R2D-1 board) */
+ KEY, /* Key input (R2D-PLUS board) */
+ SDCARD, /* SD Card */
+ CF_CD, CF_IDE, /* CF Card Detect + CF IDE */
+ SM501, /* SM501 aka Voyager */
+ PCI_INTD_RTL8139, /* Ethernet controller */
+ PCI_INTC_PCI1520, /* Cardbus/PCMCIA bridge */
+ PCI_INTB_RTL8139, /* Ethernet controller with HUB (R2D-PLUS board) */
+ PCI_INTB_SLOT, /* PCI Slot 3.3v (R2D-1 board) */
+ PCI_INTA_SLOT, /* PCI Slot 3.3v */
+ TP, /* Touch Panel */
+};
+
+#ifdef CONFIG_RTS7751R2D_1
+
+/* Vectors for R2D-1 */
+static struct intc_vect vectors_r2d_1[] __initdata = {
+ INTC_IRQ(EXT, IRQ_EXT),
+ INTC_IRQ(RTC_T, IRQ_RTC_T), INTC_IRQ(RTC_A, IRQ_RTC_A),
+ INTC_IRQ(AX88796, IRQ_AX88796), INTC_IRQ(SDCARD, IRQ_SDCARD),
+ INTC_IRQ(CF_CD, IRQ_CF_CD), INTC_IRQ(CF_IDE, IRQ_CF_IDE), /* ng */
+ INTC_IRQ(SM501, IRQ_VOYAGER),
+ INTC_IRQ(PCI_INTD_RTL8139, IRQ_PCI_INTD),
+ INTC_IRQ(PCI_INTC_PCI1520, IRQ_PCI_INTC),
+ INTC_IRQ(PCI_INTB_SLOT, IRQ_PCI_INTB),
+ INTC_IRQ(PCI_INTA_SLOT, IRQ_PCI_INTA),
+ INTC_IRQ(TP, IRQ_TP),
+};
+
+/* IRLMSK mask register layout for R2D-1 */
+static struct intc_mask_reg mask_registers_r2d_1[] __initdata = {
+ { 0xa4000000, 0, 16, /* IRLMSK */
+ { TP, PCI_INTA_SLOT, PCI_INTB_SLOT,
+ PCI_INTC_PCI1520, PCI_INTD_RTL8139,
+ SM501, CF_IDE, CF_CD, SDCARD, AX88796,
+ RTC_A, RTC_T, 0, 0, 0, EXT } },
+};
+
+/* IRLn to IRQ table for R2D-1 */
+static unsigned char irl2irq_r2d_1[R2D_NR_IRL] __initdata = {
+ IRQ_PCI_INTD, IRQ_CF_IDE, IRQ_CF_CD, IRQ_PCI_INTC,
+ IRQ_VOYAGER, IRQ_AX88796, IRQ_RTC_A, IRQ_RTC_T,
+ IRQ_SDCARD, IRQ_PCI_INTA, IRQ_PCI_INTB, IRQ_EXT,
+ IRQ_TP,
+};
+
+static __initdata DECLARE_INTC_DESC(intc_desc_r2d_1, "r2d-1",
+ vectors_r2d_1, NULL, NULL,
+ mask_registers_r2d_1, NULL, NULL);
+
+#endif /* CONFIG_RTS7751R2D_1 */
+
+#ifdef CONFIG_RTS7751R2D_PLUS
+
+/* Vectors for R2D-PLUS */
+static struct intc_vect vectors_r2d_plus[] __initdata = {
+ INTC_IRQ(EXT, IRQ_EXT),
+ INTC_IRQ(RTC_T, IRQ_RTC_T), INTC_IRQ(RTC_A, IRQ_RTC_A),
+ INTC_IRQ(KEY, IRQ_KEY), INTC_IRQ(SDCARD, IRQ_SDCARD),
+ INTC_IRQ(CF_CD, IRQ_CF_CD), INTC_IRQ(CF_IDE, IRQ_CF_IDE),
+ INTC_IRQ(SM501, IRQ_VOYAGER),
+ INTC_IRQ(PCI_INTD_RTL8139, IRQ_PCI_INTD),
+ INTC_IRQ(PCI_INTC_PCI1520, IRQ_PCI_INTC),
+ INTC_IRQ(PCI_INTB_RTL8139, IRQ_PCI_INTB),
+ INTC_IRQ(PCI_INTA_SLOT, IRQ_PCI_INTA),
+ INTC_IRQ(TP, IRQ_TP),
+};
+
+/* IRLMSK mask register layout for R2D-PLUS */
+static struct intc_mask_reg mask_registers_r2d_plus[] __initdata = {
+ { 0xa4000000, 0, 16, /* IRLMSK */
+ { TP, PCI_INTA_SLOT, PCI_INTB_RTL8139,
+ PCI_INTC_PCI1520, PCI_INTD_RTL8139,
+ SM501, CF_IDE, CF_CD, SDCARD, KEY,
+ RTC_A, RTC_T, 0, 0, 0, EXT } },
+};
+
+/* IRLn to IRQ table for R2D-PLUS */
+static unsigned char irl2irq_r2d_plus[R2D_NR_IRL] __initdata = {
+ IRQ_PCI_INTD, IRQ_CF_IDE, IRQ_CF_CD, IRQ_PCI_INTC,
+ IRQ_VOYAGER, IRQ_KEY, IRQ_RTC_A, IRQ_RTC_T,
+ IRQ_SDCARD, IRQ_PCI_INTA, IRQ_PCI_INTB, IRQ_EXT,
+ IRQ_TP,
+};
+
+static __initdata DECLARE_INTC_DESC(intc_desc_r2d_plus, "r2d-plus",
+ vectors_r2d_plus, NULL, NULL,
+ mask_registers_r2d_plus, NULL, NULL);
+
+#endif /* CONFIG_RTS7751R2D_PLUS */
+
+static unsigned char irl2irq[R2D_NR_IRL];
int rts7751r2d_irq_demux(int irq)
{
- return irq;
-}
+ if (irq >= R2D_NR_IRL || !irl2irq[irq])
+ return irq;
-static struct irq_chip rts7751r2d_irq_chip __read_mostly = {
- .name = "rts7751r2d",
- .mask = disable_rts7751r2d_irq,
- .unmask = enable_rts7751r2d_irq,
- .mask_ack = disable_rts7751r2d_irq,
-};
+ return irl2irq[irq];
+}
/*
* Initialize IRQ setting
*/
void __init init_rts7751r2d_IRQ(void)
{
- int i;
+ struct intc_desc *d;
- /* IRL0=KEY Input
- * IRL1=Ethernet
- * IRL2=CF Card
- * IRL3=CF Card Insert
- * IRL4=PCMCIA
- * IRL5=VOYAGER
- * IRL6=RTC Alarm
- * IRL7=RTC Timer
- * IRL8=SD Card
- * IRL9=PCI Slot #1
- * IRL10=PCI Slot #2
- * IRL11=Extention #0
- * IRL12=Extention #1
- * IRL13=Extention #2
- * IRL14=Extention #3
- */
-
- for (i=0; i<15; i++) {
- disable_irq_nosync(i);
- set_irq_chip_and_handler_name(i, &rts7751r2d_irq_chip,
- handle_level_irq, "level");
- enable_rts7751r2d_irq(i);
+ switch (ctrl_inw(PA_BVERREG)) {
+#ifdef CONFIG_RTS7751R2D_PLUS
+ case 0x10:
+ printk(KERN_INFO "Using R2D-PLUS interrupt controller.\n");
+ d = &intc_desc_r2d_plus;
+ memcpy(irl2irq, irl2irq_r2d_plus, R2D_NR_IRL);
+ break;
+#endif
+#ifdef CONFIG_RTS7751R2D_1
+ case 0x11:
+ printk(KERN_INFO "Using R2D-1 interrupt controller.\n");
+ d = &intc_desc_r2d_1;
+ memcpy(irl2irq, irl2irq_r2d_1, R2D_NR_IRL);
+ break;
+#endif
+ default:
+ return;
}
+ register_intc_controller(d);
setup_voyagergx_irq();
}
--- 0001/arch/sh/boards/renesas/rts7751r2d/setup.c
+++ work/arch/sh/boards/renesas/rts7751r2d/setup.c 2007-08-09 11:06:20.000000000 +0900
@@ -54,11 +54,7 @@ static struct resource cf_ide_resources[
.flags = IORESOURCE_MEM,
},
[2] = {
-#ifdef CONFIG_RTS7751R2D_REV11
- .start = 1,
-#else
- .start = 2,
-#endif
+ .start = IRQ_CF_IDE,
.flags = IORESOURCE_IRQ,
},
};
@@ -147,7 +143,7 @@ static int __init rts7751r2d_devices_set
{
int ret;
- if (ctrl_inw(PA_BVERREG) == 0x10) { /* only working on R2D-PLUS */
+ if (ctrl_inw(PA_BVERREG) == 0x10) { /* R2D-PLUS */
ret = platform_device_register(&cf_ide_device);
if (ret)
return ret;
--- 0001/arch/sh/drivers/pci/ops-rts7751r2d.c
+++ work/arch/sh/drivers/pci/ops-rts7751r2d.c 2007-08-09 11:06:20.000000000 +0900
@@ -19,10 +19,10 @@
#include "pci-sh4.h"
static u8 rts7751r2d_irq_tab[] __initdata = {
- IRQ_PCISLOT1,
- IRQ_PCISLOT2,
- IRQ_PCMCIA,
- IRQ_PCIETH,
+ IRQ_PCI_INTA,
+ IRQ_PCI_INTB,
+ IRQ_PCI_INTC,
+ IRQ_PCI_INTD,
};
int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
--- 0001/include/asm-sh/rts7751r2d.h
+++ work/include/asm-sh/rts7751r2d.h 2007-08-09 11:06:20.000000000 +0900
@@ -9,7 +9,7 @@
* Renesas Technology Sales RTS7751R2D support
*/
-/* Box specific addresses. */
+/* Board specific addresses. */
#define PA_BCR 0xa4000000 /* FPGA */
#define PA_IRLMON 0xa4000002 /* Interrupt Status control */
@@ -20,19 +20,19 @@
#define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */
#define PA_PCICD 0xa400000e /* PCI Extention detect control */
#define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */
-#if defined(CONFIG_RTS7751R2D_REV11)
-#define PA_AXRST 0xa4000022 /* AX_LAN Reset control */
-#define PA_CFRST 0xa4000024 /* CF Reset control */
-#define PA_ADMRTS 0xa4000026 /* SD Reset control */
-#define PA_EXTRST 0xa4000028 /* Extention Reset control */
-#define PA_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */
-#else
-#define PA_CFRST 0xa4000022 /* CF Reset control */
-#define PA_ADMRTS 0xa4000024 /* SD Reset control */
-#define PA_EXTRST 0xa4000026 /* Extention Reset control */
-#define PA_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */
-#define PA_KEYCTLCLR 0xa400002a /* Key Interrupt clear */
-#endif
+
+#define PA_R2D1_AXRST 0xa4000022 /* AX_LAN Reset control */
+#define PA_R2D1_CFRST 0xa4000024 /* CF Reset control */
+#define PA_R2D1_ADMRTS 0xa4000026 /* SD Reset control */
+#define PA_R2D1_EXTRST 0xa4000028 /* Extention Reset control */
+#define PA_R2D1_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */
+
+#define PA_R2DPLUS_CFRST 0xa4000022 /* CF Reset control */
+#define PA_R2DPLUS_ADMRTS 0xa4000024 /* SD Reset control */
+#define PA_R2DPLUS_EXTRST 0xa4000026 /* Extention Reset control */
+#define PA_R2DPLUS_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */
+#define PA_R2DPLUS_KEYCTLCLR 0xa400002a /* Key Interrupt clear */
+
#define PA_POWOFF 0xa4000030 /* Board Power OFF control */
#define PA_VERREG 0xa4000032 /* FPGA Version Register */
#define PA_INPORT 0xa4000034 /* KEY Input Port control */
@@ -46,27 +46,22 @@
#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
-#if defined(CONFIG_RTS7751R2D_REV11)
-#define IRQ_PCIETH 0 /* PCI Ethernet IRQ */
-#define IRQ_CFCARD 1 /* CF Card IRQ */
-#define IRQ_CFINST 2 /* CF Card Insert IRQ */
-#define IRQ_PCMCIA 3 /* PCMCIA IRQ */
-#define IRQ_VOYAGER 4 /* VOYAGER IRQ */
-#define IRQ_ONETH 5 /* On board Ethernet IRQ */
-#else
-#define IRQ_KEYIN 0 /* Key Input IRQ */
-#define IRQ_PCIETH 1 /* PCI Ethernet IRQ */
-#define IRQ_CFCARD 2 /* CF Card IRQ */
-#define IRQ_CFINST 3 /* CF Card Insert IRQ */
-#define IRQ_PCMCIA 4 /* PCMCIA IRQ */
-#define IRQ_VOYAGER 5 /* VOYAGER IRQ */
-#endif
-#define IRQ_RTCALM 6 /* RTC Alarm IRQ */
-#define IRQ_RTCTIME 7 /* RTC Timer IRQ */
-#define IRQ_SDCARD 8 /* SD Card IRQ */
-#define IRQ_PCISLOT1 9 /* PCI Slot #1 IRQ */
-#define IRQ_PCISLOT2 10 /* PCI Slot #2 IRQ */
-#define IRQ_EXTENTION 11 /* EXTn IRQ */
+#define R2D_FPGA_IRQ_BASE 100
+
+#define IRQ_VOYAGER (R2D_FPGA_IRQ_BASE + 0)
+#define IRQ_EXT (R2D_FPGA_IRQ_BASE + 1)
+#define IRQ_TP (R2D_FPGA_IRQ_BASE + 2)
+#define IRQ_RTC_T (R2D_FPGA_IRQ_BASE + 3)
+#define IRQ_RTC_A (R2D_FPGA_IRQ_BASE + 4)
+#define IRQ_SDCARD (R2D_FPGA_IRQ_BASE + 5)
+#define IRQ_CF_CD (R2D_FPGA_IRQ_BASE + 6)
+#define IRQ_CF_IDE (R2D_FPGA_IRQ_BASE + 7)
+#define IRQ_AX88796 (R2D_FPGA_IRQ_BASE + 8)
+#define IRQ_KEY (R2D_FPGA_IRQ_BASE + 9)
+#define IRQ_PCI_INTA (R2D_FPGA_IRQ_BASE + 10)
+#define IRQ_PCI_INTB (R2D_FPGA_IRQ_BASE + 11)
+#define IRQ_PCI_INTC (R2D_FPGA_IRQ_BASE + 12)
+#define IRQ_PCI_INTD (R2D_FPGA_IRQ_BASE + 13)
/* arch/sh/boards/renesas/rts7751r2d/irq.c */
void init_rts7751r2d_IRQ(void);
|
|
From: Magnus D. <mag...@gm...> - 2007-08-10 12:00:59
|
sh: intc - mark data structures as __initdata
With the intc core improved it is now possible to put the intc data structures
in the initdata section.
Signed-off-by: Magnus Damm <da...@ig...>
---
arch/sh/cchips/voyagergx/irq.c | 8 ++--
arch/sh/kernel/cpu/sh3/setup-sh7705.c | 19 +++++-----
arch/sh/kernel/cpu/sh3/setup-sh770x.c | 19 +++++-----
arch/sh/kernel/cpu/sh3/setup-sh7710.c | 19 +++++-----
arch/sh/kernel/cpu/sh4/setup-sh7750.c | 58 ++++++++++++++++----------------
arch/sh/kernel/cpu/sh4/setup-sh7760.c | 22 ++++++------
arch/sh/kernel/cpu/sh4a/setup-sh7722.c | 17 ++++-----
arch/sh/kernel/cpu/sh4a/setup-sh7780.c | 47 +++++++++++++------------
arch/sh/kernel/cpu/sh4a/setup-sh7785.c | 54 ++++++++++++++++-------------
arch/sh/kernel/cpu/sh4a/setup-shx3.c | 32 +++++++++--------
include/asm-sh/hw_irq.h | 4 +-
11 files changed, 158 insertions(+), 141 deletions(-)
--- 0004/arch/sh/cchips/voyagergx/irq.c
+++ work/arch/sh/cchips/voyagergx/irq.c 2007-08-08 20:10:15.000000000 +0900
@@ -33,7 +33,7 @@ enum {
UH, TWOD, ZD, PV, CI,
};
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
INTC_IRQ(UP, IRQ_SM501_UP), INTC_IRQ(G54, IRQ_SM501_G54),
INTC_IRQ(G53, IRQ_SM501_G53), INTC_IRQ(G52, IRQ_SM501_G52),
INTC_IRQ(G51, IRQ_SM501_G51), INTC_IRQ(G50, IRQ_SM501_G50),
@@ -49,7 +49,7 @@ static struct intc_vect vectors[] = {
INTC_IRQ(PV, IRQ_SM501_PV), INTC_IRQ(CI, IRQ_SM501_CI),
};
-static struct intc_mask_reg mask_registers[] = {
+static struct intc_mask_reg mask_registers[] __initdata = {
{ VOYAGER_INT_MASK, 0, 32, /* "Interrupt Mask", MMIO_base + 0x30 */
{ UP, G54, G53, G52, G51, G50, G49, G48,
I2C, PW, 0, DMA, PCI, I2S, AC, US,
@@ -57,8 +57,8 @@ static struct intc_mask_reg mask_registe
0, UH, 0, 0, TWOD, ZD, PV, CI } },
};
-static DECLARE_INTC_DESC(intc_desc, "voyagergx", vectors,
- NULL, NULL, mask_registers, NULL, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc, "voyagergx", vectors,
+ NULL, NULL, mask_registers, NULL, NULL);
static unsigned int voyagergx_stat2irq[32] = {
IRQ_SM501_CI, IRQ_SM501_PV, IRQ_SM501_ZD, IRQ_SM501_2D,
--- 0003/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ work/arch/sh/kernel/cpu/sh3/setup-sh7705.c 2007-08-08 20:27:17.000000000 +0900
@@ -36,7 +36,7 @@ enum {
RTC, TMU2, DMAC, USB, SCIF2, SCIF0,
};
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
@@ -57,7 +57,7 @@ static struct intc_vect vectors[] = {
INTC_VECT(REF_RCMI, 0x580),
};
-static struct intc_group groups[] = {
+static struct intc_group groups[] __initdata = {
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
@@ -66,13 +66,13 @@ static struct intc_group groups[] = {
INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
};
-static struct intc_prio priorities[] = {
+static struct intc_prio priorities[] __initdata = {
INTC_PRIO(DMAC, 7),
INTC_PRIO(SCIF2, 3),
INTC_PRIO(SCIF0, 3),
};
-static struct intc_prio_reg prio_registers[] = {
+static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
@@ -84,16 +84,17 @@ static struct intc_prio_reg prio_registe
};
-static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, groups,
- priorities, NULL, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, groups,
+ priorities, NULL, prio_registers, NULL);
-static struct intc_vect vectors_irq[] = {
+static struct intc_vect vectors_irq[] __initdata = {
INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
};
-static DECLARE_INTC_DESC(intc_desc_irq, "sh7705-irq", vectors_irq, NULL,
- priorities, NULL, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc_irq, "sh7705-irq", vectors_irq,
+ NULL, priorities, NULL,
+ prio_registers, NULL);
static struct plat_sci_port sci_platform_data[] = {
{
--- 0003/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ work/arch/sh/kernel/cpu/sh3/setup-sh770x.c 2007-08-08 20:28:17.000000000 +0900
@@ -39,7 +39,7 @@ enum {
RTC, REF, TMU2, DMAC, SCI, SCIF2, SCIF0,
};
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
@@ -71,7 +71,7 @@ static struct intc_vect vectors[] = {
#endif
};
-static struct intc_group groups[] = {
+static struct intc_group groups[] __initdata = {
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
INTC_GROUP(REF, REF_RCMI, REF_ROVI),
@@ -81,14 +81,14 @@ static struct intc_group groups[] = {
INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
};
-static struct intc_prio priorities[] = {
+static struct intc_prio priorities[] __initdata = {
INTC_PRIO(DMAC, 7),
INTC_PRIO(SCI, 3),
INTC_PRIO(SCIF2, 3),
INTC_PRIO(SCIF0, 3),
};
-static struct intc_prio_reg prio_registers[] = {
+static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
@@ -108,19 +108,20 @@ static struct intc_prio_reg prio_registe
#endif
};
-static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups,
- priorities, NULL, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups,
+ priorities, NULL, prio_registers, NULL);
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
-static struct intc_vect vectors_irq[] = {
+static struct intc_vect vectors_irq[] __initdata = {
INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
};
-static DECLARE_INTC_DESC(intc_desc_irq, "sh770x-irq", vectors_irq, NULL,
- priorities, NULL, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc_irq, "sh770x-irq", vectors_irq,
+ NULL, priorities, NULL,
+ prio_registers, NULL);
#endif
static struct resource rtc_resources[] = {
--- 0003/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ work/arch/sh/kernel/cpu/sh3/setup-sh7710.c 2007-08-08 20:29:52.000000000 +0900
@@ -37,7 +37,7 @@ enum {
RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1,
};
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
@@ -63,7 +63,7 @@ static struct intc_vect vectors[] = {
INTC_VECT(REF, 0x580),
};
-static struct intc_group groups[] = {
+static struct intc_group groups[] __initdata = {
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
@@ -73,7 +73,7 @@ static struct intc_group groups[] = {
INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI),
};
-static struct intc_prio priorities[] = {
+static struct intc_prio priorities[] __initdata = {
INTC_PRIO(DMAC1, 7),
INTC_PRIO(DMAC2, 7),
INTC_PRIO(SCIF0, 3),
@@ -85,7 +85,7 @@ static struct intc_prio priorities[] = {
INTC_PRIO(EDMAC2, 5),
};
-static struct intc_prio_reg prio_registers[] = {
+static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
@@ -100,16 +100,17 @@ static struct intc_prio_reg prio_registe
{ 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
};
-static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
- priorities, NULL, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
+ priorities, NULL, prio_registers, NULL);
-static struct intc_vect vectors_irq[] = {
+static struct intc_vect vectors_irq[] __initdata = {
INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
};
-static DECLARE_INTC_DESC(intc_desc_irq, "sh7710-irq", vectors_irq, NULL,
- priorities, NULL, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc_irq, "sh7710-irq", vectors_irq,
+ NULL, priorities, NULL,
+ prio_registers, NULL);
static struct resource rtc_resources[] = {
[0] = {
--- 0003/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ work/arch/sh/kernel/cpu/sh4/setup-sh7750.c 2007-08-08 20:14:50.000000000 +0900
@@ -104,7 +104,7 @@ enum {
DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
};
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
@@ -118,7 +118,7 @@ static struct intc_vect vectors[] = {
INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
};
-static struct intc_group groups[] = {
+static struct intc_group groups[] __initdata = {
INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
@@ -126,13 +126,13 @@ static struct intc_group groups[] = {
INTC_GROUP(REF, REF_RCMI, REF_ROVI),
};
-static struct intc_prio priorities[] = {
+static struct intc_prio priorities[] __initdata = {
INTC_PRIO(SCIF, 3),
INTC_PRIO(SCI1, 3),
INTC_PRIO(DMAC, 7),
};
-static struct intc_prio_reg prio_registers[] = {
+static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
@@ -142,33 +142,33 @@ static struct intc_prio_reg prio_registe
PCIC1, PCIC0_PCISERR } },
};
-static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
- priorities, NULL, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
+ priorities, NULL, prio_registers, NULL);
/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
defined(CONFIG_CPU_SUBTYPE_SH7091)
-static struct intc_vect vectors_dma4[] = {
+static struct intc_vect vectors_dma4[] __initdata = {
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
INTC_VECT(DMAC_DMAE, 0x6c0),
};
-static struct intc_group groups_dma4[] = {
+static struct intc_group groups_dma4[] __initdata = {
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
DMAC_DMTE3, DMAC_DMAE),
};
-static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
- vectors_dma4, groups_dma4,
- priorities, NULL, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
+ vectors_dma4, groups_dma4,
+ priorities, NULL, prio_registers, NULL);
#endif
/* SH7750R and SH7751R both have 8-channel DMA controllers */
#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
-static struct intc_vect vectors_dma8[] = {
+static struct intc_vect vectors_dma8[] __initdata = {
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
@@ -176,26 +176,26 @@ static struct intc_vect vectors_dma8[] =
INTC_VECT(DMAC_DMAE, 0x6c0),
};
-static struct intc_group groups_dma8[] = {
+static struct intc_group groups_dma8[] __initdata = {
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
};
-static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
- vectors_dma8, groups_dma8,
- priorities, NULL, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
+ vectors_dma8, groups_dma8,
+ priorities, NULL, prio_registers, NULL);
#endif
/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
defined(CONFIG_CPU_SUBTYPE_SH7751R)
-static struct intc_vect vectors_tmu34[] = {
+static struct intc_vect vectors_tmu34[] __initdata = {
INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
};
-static struct intc_mask_reg mask_registers[] = {
+static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, TMU4, TMU3,
@@ -204,36 +204,38 @@ static struct intc_mask_reg mask_registe
PCIC1_PCIDMA3, PCIC0_PCISERR } },
};
-static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
- vectors_tmu34, NULL, priorities,
- mask_registers, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
+ vectors_tmu34, NULL, priorities,
+ mask_registers, prio_registers, NULL);
#endif
/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
-static struct intc_vect vectors_irlm[] = {
+static struct intc_vect vectors_irlm[] __initdata = {
INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
};
-static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
- priorities, NULL, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm",
+ vectors_irlm, NULL, priorities,
+ NULL, prio_registers, NULL);
/* SH7751 and SH7751R both have PCI */
#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
-static struct intc_vect vectors_pci[] = {
+static struct intc_vect vectors_pci[] __initdata = {
INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
};
-static struct intc_group groups_pci[] = {
+static struct intc_group groups_pci[] __initdata = {
INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
};
-static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
- priorities, mask_registers, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci,
+ groups_pci, priorities, mask_registers,
+ prio_registers, NULL);
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
--- 0003/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ work/arch/sh/kernel/cpu/sh4/setup-sh7760.c 2007-08-08 20:32:08.000000000 +0900
@@ -43,7 +43,7 @@ enum {
DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF,
};
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
@@ -78,7 +78,7 @@ static struct intc_vect vectors[] = {
INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
};
-static struct intc_group groups[] = {
+static struct intc_group groups[] __initdata = {
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
@@ -92,7 +92,7 @@ static struct intc_group groups[] = {
INTC_GROUP(REF, REF_RCMI, REF_ROVI),
};
-static struct intc_prio priorities[] = {
+static struct intc_prio priorities[] __initdata = {
INTC_PRIO(SCIF0, 3),
INTC_PRIO(SCIF1, 3),
INTC_PRIO(SCIF2, 3),
@@ -101,7 +101,7 @@ static struct intc_prio priorities[] = {
INTC_PRIO(DMABRG, 13),
};
-static struct intc_mask_reg mask_registers[] = {
+static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
{ IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
@@ -117,7 +117,7 @@ static struct intc_mask_reg mask_registe
0, MFI, 0, 0, 0, 0, ADC, CMT, } },
};
-static struct intc_prio_reg prio_registers[] = {
+static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
@@ -131,16 +131,18 @@ static struct intc_prio_reg prio_registe
MFI, 0, ADC, CMT } },
};
-static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
- priorities, mask_registers, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
+ priorities, mask_registers,
+ prio_registers, NULL);
-static struct intc_vect vectors_irq[] = {
+static struct intc_vect vectors_irq[] __initdata = {
INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
};
-static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
- priorities, mask_registers, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq,
+ groups, priorities, mask_registers,
+ prio_registers, NULL);
static struct plat_sci_port sci_platform_data[] = {
{
--- 0003/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-sh7722.c 2007-08-08 20:34:01.000000000 +0900
@@ -84,7 +84,7 @@ enum {
SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
};
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
@@ -117,7 +117,7 @@ static struct intc_vect vectors[] = {
INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
};
-static struct intc_group groups[] = {
+static struct intc_group groups[] __initdata = {
INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
@@ -130,7 +130,7 @@ static struct intc_group groups[] = {
INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
};
-static struct intc_prio priorities[] = {
+static struct intc_prio priorities[] __initdata = {
INTC_PRIO(SCIF0, 3),
INTC_PRIO(SCIF1, 3),
INTC_PRIO(SCIF2, 3),
@@ -138,7 +138,7 @@ static struct intc_prio priorities[] = {
INTC_PRIO(TMU1, 2),
};
-static struct intc_mask_reg mask_registers[] = {
+static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
{ } },
{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
@@ -168,7 +168,7 @@ static struct intc_mask_reg mask_registe
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};
-static struct intc_prio_reg prio_registers[] = {
+static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
@@ -185,13 +185,14 @@ static struct intc_prio_reg prio_registe
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};
-static struct intc_sense_reg sense_registers[] = {
+static struct intc_sense_reg sense_registers[] __initdata = {
{ 0xa414001c, 16, 2, /* ICR1 */
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};
-static DECLARE_INTC_DESC(intc_desc, "sh7722", vectors, groups, priorities,
- mask_registers, prio_registers, sense_registers);
+static __initdata DECLARE_INTC_DESC(intc_desc, "sh7722", vectors, groups,
+ priorities, mask_registers,
+ prio_registers, sense_registers);
void __init plat_irq_setup(void)
{
--- 0003/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-sh7780.c 2007-08-08 20:36:37.000000000 +0900
@@ -114,7 +114,7 @@ enum {
PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
};
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
INTC_VECT(RTC_CUI, 0x4c0),
INTC_VECT(WDT, 0x560),
@@ -150,7 +150,7 @@ static struct intc_vect vectors[] = {
INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
};
-static struct intc_group groups[] = {
+static struct intc_group groups[] __initdata = {
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
@@ -167,12 +167,12 @@ static struct intc_group groups[] = {
INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
};
-static struct intc_prio priorities[] = {
+static struct intc_prio priorities[] __initdata = {
INTC_PRIO(SCIF0, 3),
INTC_PRIO(SCIF1, 3),
};
-static struct intc_mask_reg mask_registers[] = {
+static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
{ 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
@@ -180,7 +180,7 @@ static struct intc_mask_reg mask_registe
HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
};
-static struct intc_prio_reg prio_registers[] = {
+static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
TMU2, TMU2_TICPI } },
{ 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
@@ -194,40 +194,41 @@ static struct intc_prio_reg prio_registe
{ 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
};
-static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities,
- mask_registers, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
+ priorities, mask_registers,
+ prio_registers, NULL);
/* Support for external interrupt pins in IRQ mode */
-static struct intc_vect irq_vectors[] = {
+static struct intc_vect irq_vectors[] __initdata = {
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
};
-static struct intc_mask_reg irq_mask_registers[] = {
+static struct intc_mask_reg irq_mask_registers[] __initdata = {
{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};
-static struct intc_prio_reg irq_prio_registers[] = {
+static struct intc_prio_reg irq_prio_registers[] __initdata = {
{ 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6, IRQ7 } },
};
-static struct intc_sense_reg irq_sense_registers[] = {
+static struct intc_sense_reg irq_sense_registers[] __initdata = {
{ 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6, IRQ7 } },
};
-static DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors,
- NULL, NULL, irq_mask_registers, irq_prio_registers,
- irq_sense_registers);
+static __initdata DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors,
+ NULL, NULL, irq_mask_registers,
+ irq_prio_registers, irq_sense_registers);
/* External interrupt pins in IRL mode */
-static struct intc_vect irl_vectors[] = {
+static struct intc_vect irl_vectors[] __initdata = {
INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
@@ -238,7 +239,7 @@ static struct intc_vect irl_vectors[] =
INTC_VECT(IRL_HHHL, 0x3c0),
};
-static struct intc_mask_reg irl3210_mask_registers[] = {
+static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
{ 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
{ IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
@@ -246,7 +247,7 @@ static struct intc_mask_reg irl3210_mask
IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
};
-static struct intc_mask_reg irl7654_mask_registers[] = {
+static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
{ 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
@@ -255,11 +256,13 @@ static struct intc_mask_reg irl7654_mask
IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
};
-static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
- NULL, NULL, irl7654_mask_registers, NULL, NULL);
-
-static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
- NULL, NULL, irl3210_mask_registers, NULL, NULL);
+static __initdata DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654",
+ irl_vectors, NULL, NULL,
+ irl7654_mask_registers, NULL, NULL);
+
+static __initdata DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210",
+ irl_vectors, NULL, NULL,
+ irl3210_mask_registers, NULL, NULL);
void __init plat_irq_setup(void)
{
--- 0003/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-sh7785.c 2007-08-08 20:38:53.000000000 +0900
@@ -117,7 +117,7 @@ enum {
PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
};
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
INTC_VECT(WDT, 0x560),
INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
@@ -158,7 +158,7 @@ static struct intc_vect vectors[] = {
INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
};
-static struct intc_group groups[] = {
+static struct intc_group groups[] __initdata = {
INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
@@ -175,7 +175,7 @@ static struct intc_group groups[] = {
INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
};
-static struct intc_prio priorities[] = {
+static struct intc_prio priorities[] __initdata = {
INTC_PRIO(SCIF0, 3),
INTC_PRIO(SCIF1, 3),
INTC_PRIO(SCIF2, 3),
@@ -184,7 +184,7 @@ static struct intc_prio priorities[] = {
INTC_PRIO(SCIF5, 3),
};
-static struct intc_mask_reg mask_registers[] = {
+static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
@@ -205,7 +205,7 @@ static struct intc_mask_reg mask_registe
SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
};
-static struct intc_prio_reg prio_registers[] = {
+static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6, IRQ7 } },
{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
@@ -224,38 +224,40 @@ static struct intc_prio_reg prio_registe
{ 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
};
-static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, priorities,
- mask_registers, prio_registers, NULL);
-
+static __initdata DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
+ priorities, mask_registers,
+ prio_registers, NULL);
/* Support for external interrupt pins in IRQ mode */
-static struct intc_vect vectors_irq0123[] = {
+static struct intc_vect vectors_irq0123[] __initdata = {
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
};
-static struct intc_vect vectors_irq4567[] = {
+static struct intc_vect vectors_irq4567[] __initdata = {
INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
};
-static struct intc_sense_reg sense_registers[] = {
+static struct intc_sense_reg sense_registers[] __initdata = {
{ 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6, IRQ7 } },
};
-static DECLARE_INTC_DESC(intc_desc_irq0123, "sh7785-irq0123", vectors_irq0123,
- NULL, NULL, mask_registers, prio_registers,
- sense_registers);
-
-static DECLARE_INTC_DESC(intc_desc_irq4567, "sh7785-irq4567", vectors_irq4567,
- NULL, NULL, mask_registers, prio_registers,
- sense_registers);
+static __initdata DECLARE_INTC_DESC(intc_desc_irq0123, "sh7785-irq0123",
+ vectors_irq0123, NULL, NULL,
+ mask_registers, prio_registers,
+ sense_registers);
+
+static __initdata DECLARE_INTC_DESC(intc_desc_irq4567, "sh7785-irq4567",
+ vectors_irq4567, NULL, NULL,
+ mask_registers, prio_registers,
+ sense_registers);
/* External interrupt pins in IRL mode */
-static struct intc_vect vectors_irl0123[] = {
+static struct intc_vect vectors_irl0123[] __initdata = {
INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
@@ -266,7 +268,7 @@ static struct intc_vect vectors_irl0123[
INTC_VECT(IRL0_HHHL, 0x3c0),
};
-static struct intc_vect vectors_irl4567[] = {
+static struct intc_vect vectors_irl4567[] __initdata = {
INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
@@ -277,11 +279,13 @@ static struct intc_vect vectors_irl4567[
INTC_VECT(IRL4_HHHL, 0xcc0),
};
-static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
- NULL, NULL, mask_registers, NULL, NULL);
-
-static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
- NULL, NULL, mask_registers, NULL, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123",
+ vectors_irl0123, NULL, NULL,
+ mask_registers, NULL, NULL);
+
+static __initdata DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567",
+ vectors_irl4567, NULL, NULL,
+ mask_registers, NULL, NULL);
void __init plat_irq_setup(void)
{
--- 0003/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-shx3.c 2007-08-08 20:40:38.000000000 +0900
@@ -94,7 +94,7 @@ enum {
DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3,
};
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
INTC_VECT(HUDII, 0x3e0),
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),
@@ -138,7 +138,7 @@ static struct intc_vect vectors[] = {
INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0),
};
-static struct intc_group groups[] = {
+static struct intc_group groups[] __initdata = {
INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
@@ -158,14 +158,14 @@ static struct intc_group groups[] = {
INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
};
-static struct intc_prio priorities[] = {
+static struct intc_prio priorities[] __initdata = {
INTC_PRIO(SCIF0, 3),
INTC_PRIO(SCIF1, 3),
INTC_PRIO(SCIF2, 3),
INTC_PRIO(SCIF3, 3),
};
-static struct intc_mask_reg mask_registers[] = {
+static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
{ IRQ0, IRQ1, IRQ2, IRQ3 } },
{ 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */
@@ -190,7 +190,7 @@ static struct intc_mask_reg mask_registe
SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
};
-static struct intc_prio_reg prio_registers[] = {
+static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
{ 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
@@ -208,25 +208,26 @@ static struct intc_prio_reg prio_registe
GPIO2, GPIO1, GPIO0, IRM } },
};
-static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, priorities,
- mask_registers, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups,
+ priorities, mask_registers,
+ prio_registers, NULL);
/* Support for external interrupt pins in IRQ mode */
-static struct intc_vect vectors_irq[] = {
+static struct intc_vect vectors_irq[] __initdata = {
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
};
-static struct intc_sense_reg sense_registers[] = {
+static struct intc_sense_reg sense_registers[] __initdata = {
{ 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
};
-static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
- priorities, mask_registers, prio_registers,
- sense_registers);
+static __initdata DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq,
+ groups, priorities, mask_registers,
+ prio_registers, sense_registers);
/* External interrupt pins in IRL mode */
-static struct intc_vect vectors_irl[] = {
+static struct intc_vect vectors_irl[] __initdata = {
INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
@@ -237,8 +238,9 @@ static struct intc_vect vectors_irl[] =
INTC_VECT(IRL_HHHL, 0x3c0),
};
-static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
- priorities, mask_registers, prio_registers, NULL);
+static __initdata DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl,
+ groups, priorities, mask_registers,
+ prio_registers, NULL);
void __init plat_irq_setup_pins(int mode)
{
--- 0004/include/asm-sh/hw_irq.h
+++ work/include/asm-sh/hw_irq.h 2007-08-08 20:45:51.000000000 +0900
@@ -42,10 +42,10 @@ struct intc_prio {
struct intc_group {
intc_enum enum_id;
- intc_enum *enum_ids;
+ intc_enum enum_ids[32];
};
-#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } }
+#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
struct intc_mask_reg {
unsigned long set_reg, clr_reg, reg_width;
|
|
From: Magnus D. <mag...@gm...> - 2007-08-10 11:55:17
|
sh: intc - rework core code
This patch reworks the intc core, implementing the following features:
- Support dual priority registers - one set and one clear register
- All 8/16/32 bit register combinations are now supported
- Both single mask and single enable bitmap register are supported
- Add code to set interrupt priority
- Speedup sense and priority configuration code
- Allocate data using bootmem, allows intc data structures to be __initdata
- Save memory - allocated memory footprint is smaller than intc structures
Signed-off-by: Magnus Damm <da...@ig...>
---
Boot tested on r2d, r7780, r7785 and x3.
More serious testing performed on r2d with fpga and voyager interrupts.
arch/sh/cchips/voyagergx/irq.c | 2
arch/sh/kernel/cpu/irq/intc.c | 560 ++++++++++++++++++++++++----------------
include/asm-sh/hw_irq.h | 4
3 files changed, 343 insertions(+), 223 deletions(-)
--- 0001/arch/sh/cchips/voyagergx/irq.c
+++ work/arch/sh/cchips/voyagergx/irq.c 2007-08-09 19:42:23.000000000 +0900
@@ -50,7 +50,7 @@ static struct intc_vect vectors[] = {
};
static struct intc_mask_reg mask_registers[] = {
- { VOYAGER_INT_MASK, 1, 32, /* "Interrupt Mask", MMIO_base + 0x30 */
+ { VOYAGER_INT_MASK, 0, 32, /* "Interrupt Mask", MMIO_base + 0x30 */
{ UP, G54, G53, G52, G51, G50, G49, G48,
I2C, PW, 0, DMA, PCI, I2S, AC, US,
0, 0, U1, U0, CV, MC, S1, S0,
--- 0003/arch/sh/kernel/cpu/irq/intc.c
+++ work/arch/sh/kernel/cpu/irq/intc.c 2007-08-09 19:42:23.000000000 +0900
@@ -20,176 +20,228 @@
#include <linux/module.h>
#include <linux/io.h>
#include <linux/interrupt.h>
+#include <linux/bootmem.h>
-#define _INTC_MK(fn, idx, bit, value) \
- ((fn) << 24 | ((value) << 16) | ((idx) << 8) | (bit))
-#define _INTC_FN(h) (h >> 24)
-#define _INTC_VALUE(h) ((h >> 16) & 0xff)
-#define _INTC_IDX(h) ((h >> 8) & 0xff)
-#define _INTC_BIT(h) (h & 0xff)
+#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
+ ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
+ ((addr_e) << 16) | ((addr_d << 24)))
+
+#define _INTC_SHIFT(h) (h & 0x1f)
+#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
+#define _INTC_FN(h) ((h >> 9) & 0xf)
+#define _INTC_MODE(h) ((h >> 13) & 0x7)
+#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
+#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
+
+struct intc_handle_int {
+ unsigned int irq;
+ unsigned long handle;
+};
+
+struct intc_desc_int {
+ unsigned long *reg;
+ unsigned int nr_reg;
+ struct intc_handle_int *prio;
+ unsigned int nr_prio;
+ struct intc_handle_int *sense;
+ unsigned int nr_sense;
+ struct irq_chip chip;
+};
-#define _INTC_PTR(desc, member, data) \
- (desc->member + _INTC_IDX(data))
+static unsigned int intc_prio_level[NR_IRQS]; /* for now */
-static inline struct intc_desc *get_intc_desc(unsigned int irq)
+static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
{
struct irq_chip *chip = get_irq_chip(irq);
- return (void *)((char *)chip - offsetof(struct intc_desc, chip));
+ return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
}
static inline unsigned int set_field(unsigned int value,
unsigned int field_value,
- unsigned int width,
- unsigned int shift)
+ unsigned int handle)
{
+ unsigned int width = _INTC_WIDTH(handle);
+ unsigned int shift = _INTC_SHIFT(handle);
+
value &= ~(((1 << width) - 1) << shift);
value |= field_value << shift;
return value;
}
-static inline unsigned int set_prio_field(struct intc_desc *desc,
- unsigned int value,
- unsigned int priority,
- unsigned int data)
+static void write_8(unsigned long addr, unsigned long h, unsigned long data)
{
- unsigned int width = _INTC_PTR(desc, prio_regs, data)->field_width;
-
- return set_field(value, priority, width, _INTC_BIT(data));
+ ctrl_outb(set_field(0, data, h), addr);
}
-static void disable_prio_16(struct intc_desc *desc, unsigned int data)
+static void write_16(unsigned long addr, unsigned long h, unsigned long data)
{
- unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
-
- ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr);
+ ctrl_outw(set_field(0, data, h), addr);
}
-static void enable_prio_16(struct intc_desc *desc, unsigned int data)
+static void write_32(unsigned long addr, unsigned long h, unsigned long data)
{
- unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
- unsigned int prio = _INTC_VALUE(data);
-
- ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr);
+ ctrl_outl(set_field(0, data, h), addr);
}
-static void disable_prio_32(struct intc_desc *desc, unsigned int data)
+static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
{
- unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
-
- ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr);
+ ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
}
-static void enable_prio_32(struct intc_desc *desc, unsigned int data)
+static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
{
- unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
- unsigned int prio = _INTC_VALUE(data);
-
- ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr);
+ ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
}
-static void write_set_reg_8(struct intc_desc *desc, unsigned int data)
+static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
{
- ctrl_outb(1 << _INTC_BIT(data),
- _INTC_PTR(desc, mask_regs, data)->set_reg);
+ ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
}
-static void write_clr_reg_8(struct intc_desc *desc, unsigned int data)
-{
- ctrl_outb(1 << _INTC_BIT(data),
- _INTC_PTR(desc, mask_regs, data)->clr_reg);
-}
+enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
-static void write_set_reg_32(struct intc_desc *desc, unsigned int data)
-{
- ctrl_outl(1 << _INTC_BIT(data),
- _INTC_PTR(desc, mask_regs, data)->set_reg);
-}
+static void (*intc_reg_fns[])(unsigned long addr,
+ unsigned long h,
+ unsigned long data) = {
+ [REG_FN_WRITE_BASE + 0] = write_8,
+ [REG_FN_WRITE_BASE + 1] = write_16,
+ [REG_FN_WRITE_BASE + 3] = write_32,
+ [REG_FN_MODIFY_BASE + 0] = modify_8,
+ [REG_FN_MODIFY_BASE + 1] = modify_16,
+ [REG_FN_MODIFY_BASE + 3] = modify_32,
+};
-static void write_clr_reg_32(struct intc_desc *desc, unsigned int data)
-{
- ctrl_outl(1 << _INTC_BIT(data),
- _INTC_PTR(desc, mask_regs, data)->clr_reg);
-}
+enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
+ MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
+ MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
+ MODE_PRIO_REG, /* Priority value written to enable interrupt */
+ MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
+};
-static void or_set_reg_16(struct intc_desc *desc, unsigned int data)
-{
- unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg;
+static void intc_mode_field(unsigned long addr,
+ unsigned long handle,
+ void (*fn)(unsigned long,
+ unsigned long,
+ unsigned long),
+ unsigned int irq)
+{
+ fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
+}
+
+static void intc_mode_zero(unsigned long addr,
+ unsigned long handle,
+ void (*fn)(unsigned long,
+ unsigned long,
+ unsigned long),
+ unsigned int irq)
+{
+ fn(addr, handle, 0);
+}
+
+static void intc_mode_prio(unsigned long addr,
+ unsigned long handle,
+ void (*fn)(unsigned long,
+ unsigned long,
+ unsigned long),
+ unsigned int irq)
+{
+ fn(addr, handle, intc_prio_level[irq]);
+}
+
+static void (*intc_enable_fns[])(unsigned long addr,
+ unsigned long handle,
+ void (*fn)(unsigned long,
+ unsigned long,
+ unsigned long),
+ unsigned int irq) = {
+ [MODE_ENABLE_REG] = intc_mode_field,
+ [MODE_MASK_REG] = intc_mode_zero,
+ [MODE_DUAL_REG] = intc_mode_field,
+ [MODE_PRIO_REG] = intc_mode_prio,
+ [MODE_PCLR_REG] = intc_mode_prio,
+};
- ctrl_outw(ctrl_inw(addr) | 1 << _INTC_BIT(data), addr);
-}
+static void (*intc_disable_fns[])(unsigned long addr,
+ unsigned long handle,
+ void (*fn)(unsigned long,
+ unsigned long,
+ unsigned long),
+ unsigned int irq) = {
+ [MODE_ENABLE_REG] = intc_mode_zero,
+ [MODE_MASK_REG] = intc_mode_field,
+ [MODE_DUAL_REG] = intc_mode_field,
+ [MODE_PRIO_REG] = intc_mode_zero,
+ [MODE_PCLR_REG] = intc_mode_field,
+};
-static void and_set_reg_16(struct intc_desc *desc, unsigned int data)
+static inline void _intc_enable(unsigned int irq, unsigned long handle)
{
- unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg;
+ struct intc_desc_int *d = get_intc_desc(irq);
+ unsigned long addr = d->reg[_INTC_ADDR_E(handle)];
- ctrl_outw(ctrl_inw(addr) & ~(1 << _INTC_BIT(data)), addr);
+ intc_enable_fns[_INTC_MODE(handle)](addr, handle,
+ intc_reg_fns[_INTC_FN(handle)],
+ irq);
}
+
-static void or_set_reg_32(struct intc_desc *desc, unsigned int data)
+static void intc_enable(unsigned int irq)
{
- unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg;
-
- ctrl_outl(ctrl_inl(addr) | 1 << _INTC_BIT(data), addr);
+ _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
}
-static void and_set_reg_32(struct intc_desc *desc, unsigned int data)
+static void intc_disable(unsigned int irq)
{
- unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg;
-
- ctrl_outl(ctrl_inl(addr) & ~(1 << _INTC_BIT(data)), addr);
-}
-
-enum { REG_FN_ERROR=0,
- REG_FN_DUAL_8, REG_FN_DUAL_32,
- REG_FN_ENA_16, REG_FN_ENA_32,
- REG_FN_PRIO_16, REG_FN_PRIO_32 };
-
-static struct {
- void (*enable)(struct intc_desc *, unsigned int);
- void (*disable)(struct intc_desc *, unsigned int);
-} intc_reg_fns[] = {
- [REG_FN_DUAL_8] = { write_clr_reg_8, write_set_reg_8 },
- [REG_FN_DUAL_32] = { write_clr_reg_32, write_set_reg_32 },
- [REG_FN_ENA_16] = { or_set_reg_16, and_set_reg_16 },
- [REG_FN_ENA_32] = { or_set_reg_32, and_set_reg_32 },
- [REG_FN_PRIO_16] = { enable_prio_16, disable_prio_16 },
- [REG_FN_PRIO_32] = { enable_prio_32, disable_prio_32 },
-};
-
-static void intc_enable(unsigned int irq)
+ struct intc_desc_int *desc = get_intc_desc(irq);
+ unsigned long handle = (unsigned long) get_irq_chip_data(irq);
+ unsigned long addr = desc->reg[_INTC_ADDR_D(handle)];
+
+ intc_disable_fns[_INTC_MODE(handle)](addr, handle,
+ intc_reg_fns[_INTC_FN(handle)],
+ irq);
+}
+
+static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
+ unsigned int nr_hp,
+ unsigned int irq)
{
- struct intc_desc *desc = get_intc_desc(irq);
- unsigned int data = (unsigned int) get_irq_chip_data(irq);
+ int i;
- intc_reg_fns[_INTC_FN(data)].enable(desc, data);
-}
+ for (i = 0; i < nr_hp; i++) {
+ if ((hp + i)->irq != irq)
+ continue;
-static void intc_disable(unsigned int irq)
-{
- struct intc_desc *desc = get_intc_desc(irq);
- unsigned int data = (unsigned int) get_irq_chip_data(irq);
+ return hp + i;
+ }
- intc_reg_fns[_INTC_FN(data)].disable(desc, data);
+ return NULL;
}
-static void set_sense_16(struct intc_desc *desc, unsigned int data)
+int intc_set_priority(unsigned int irq, unsigned int prio)
{
- unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
- unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
- unsigned int bit = _INTC_BIT(data);
- unsigned int value = _INTC_VALUE(data);
+ struct intc_desc_int *d = get_intc_desc(irq);
+ struct intc_handle_int *ihp;
- ctrl_outw(set_field(ctrl_inw(addr), value, width, bit), addr);
-}
+ if (!intc_prio_level[irq] || prio <= 1)
+ return -EINVAL;
-static void set_sense_32(struct intc_desc *desc, unsigned int data)
-{
- unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
- unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
- unsigned int bit = _INTC_BIT(data);
- unsigned int value = _INTC_VALUE(data);
+ ihp = intc_find_irq(d->prio, d->nr_prio, irq);
+ if (ihp) {
+ if (prio >= ((1 << _INTC_WIDTH(ihp->handle)) - 1))
+ return -EINVAL;
+
+ intc_prio_level[irq] = prio;
+
+ /*
+ * only set secondary masking method directly
+ * primary masking method is using intc_prio_level[irq]
+ * priority level will be set during next enable()
+ */
- ctrl_outl(set_field(ctrl_inl(addr), value, width, bit), addr);
+ if (ihp->handle)
+ _intc_enable(irq, ihp->handle);
+ }
+ return 0;
}
#define VALID(x) (x | 0x80)
@@ -203,92 +255,38 @@ static unsigned char intc_irq_sense_tabl
static int intc_set_sense(unsigned int irq, unsigned int type)
{
- struct intc_desc *desc = get_intc_desc(irq);
+ struct intc_desc_int *d = get_intc_desc(irq);
unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
- unsigned int i, j, data, bit;
- intc_enum enum_id = 0;
-
- for (i = 0; i < desc->nr_vectors; i++) {
- struct intc_vect *vect = desc->vectors + i;
-
- if (evt2irq(vect->vect) != irq)
- continue;
+ struct intc_handle_int *ihp;
+ unsigned long addr;
- enum_id = vect->enum_id;
- break;
- }
-
- if (!enum_id || !value || !desc->sense_regs)
+ if (!value)
return -EINVAL;
- value ^= VALID(0);
-
- for (i = 0; i < desc->nr_sense_regs; i++) {
- struct intc_sense_reg *sr = desc->sense_regs + i;
-
- for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
- if (sr->enum_ids[j] != enum_id)
- continue;
-
- bit = sr->reg_width - ((j + 1) * sr->field_width);
- data = _INTC_MK(0, i, bit, value);
-
- switch(sr->reg_width) {
- case 16:
- set_sense_16(desc, data);
- break;
- case 32:
- set_sense_32(desc, data);
- break;
- }
-
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
-static unsigned int __init intc_find_dual_handler(unsigned int width)
-{
- switch (width) {
- case 8:
- return REG_FN_DUAL_8;
- case 32:
- return REG_FN_DUAL_32;
+ ihp = intc_find_irq(d->sense, d->nr_sense, irq);
+ if (ihp) {
+ addr = d->reg[_INTC_ADDR_E(ihp->handle)];
+ intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
}
-
- BUG();
- return REG_FN_ERROR;
+ return 0;
}
-static unsigned int __init intc_find_prio_handler(unsigned int width)
+static unsigned int __init intc_get_reg(struct intc_desc_int *d,
+ unsigned long address)
{
- switch (width) {
- case 16:
- return REG_FN_PRIO_16;
- case 32:
- return REG_FN_PRIO_32;
- }
-
- BUG();
- return REG_FN_ERROR;
-}
+ unsigned int k;
-static unsigned int __init intc_find_ena_handler(unsigned int width)
-{
- switch (width) {
- case 16:
- return REG_FN_ENA_16;
- case 32:
- return REG_FN_ENA_32;
+ for (k = 0; k < d->nr_reg; k++) {
+ if (d->reg[k] == address)
+ return k;
}
BUG();
- return REG_FN_ERROR;
+ return 0;
}
-static intc_enum __init intc_grp_id(struct intc_desc *desc, intc_enum enum_id)
+static intc_enum __init intc_grp_id(struct intc_desc *desc,
+ intc_enum enum_id)
{
struct intc_group *g = desc->groups;
unsigned int i, j;
@@ -333,10 +331,12 @@ static unsigned int __init intc_prio_val
}
static unsigned int __init intc_mask_data(struct intc_desc *desc,
+ struct intc_desc_int *d,
intc_enum enum_id, int do_grps)
{
struct intc_mask_reg *mr = desc->mask_regs;
- unsigned int i, j, fn;
+ unsigned int i, j, fn, mode;
+ unsigned long reg_e, reg_d;
for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
mr = desc->mask_regs + i;
@@ -345,32 +345,48 @@ static unsigned int __init intc_mask_dat
if (mr->enum_ids[j] != enum_id)
continue;
- switch (mr->clr_reg) {
- case 1: /* 1 = enabled interrupt - "enable" register */
- fn = intc_find_ena_handler(mr->reg_width);
- break;
- default:
- fn = intc_find_dual_handler(mr->reg_width);
+ if (mr->set_reg && mr->clr_reg) {
+ fn = REG_FN_WRITE_BASE;
+ mode = MODE_DUAL_REG;
+ reg_e = mr->clr_reg;
+ reg_d = mr->set_reg;
+ }
+ else {
+ fn = REG_FN_MODIFY_BASE;
+ if (mr->set_reg) {
+ mode = MODE_ENABLE_REG;
+ reg_e = mr->set_reg;
+ reg_d = mr->set_reg;
+ }
+ else {
+ mode = MODE_MASK_REG;
+ reg_e = mr->clr_reg;
+ reg_d = mr->clr_reg;
+ }
}
- if (fn == REG_FN_ERROR)
- return 0;
-
- return _INTC_MK(fn, i, (mr->reg_width - 1) - j, 0);
+ fn += (mr->reg_width >> 3) - 1;
+ return _INTC_MK(fn, mode,
+ intc_get_reg(d, reg_e),
+ intc_get_reg(d, reg_d),
+ 1,
+ (mr->reg_width - 1) - j);
}
}
if (do_grps)
- return intc_mask_data(desc, intc_grp_id(desc, enum_id), 0);
+ return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
return 0;
}
static unsigned int __init intc_prio_data(struct intc_desc *desc,
+ struct intc_desc_int *d,
intc_enum enum_id, int do_grps)
{
struct intc_prio_reg *pr = desc->prio_regs;
- unsigned int i, j, fn, bit, prio;
+ unsigned int i, j, fn, mode, bit;
+ unsigned long reg_e, reg_d;
for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
pr = desc->prio_regs + i;
@@ -379,26 +395,70 @@ static unsigned int __init intc_prio_dat
if (pr->enum_ids[j] != enum_id)
continue;
- fn = intc_find_prio_handler(pr->reg_width);
- if (fn == REG_FN_ERROR)
- return 0;
+ if (pr->set_reg && pr->clr_reg) {
+ fn = REG_FN_WRITE_BASE;
+ mode = MODE_PCLR_REG;
+ reg_e = pr->set_reg;
+ reg_d = pr->clr_reg;
+ }
+ else {
+ fn = REG_FN_MODIFY_BASE;
+ mode = MODE_PRIO_REG;
+ if (!pr->set_reg)
+ BUG();
+ reg_e = pr->set_reg;
+ reg_d = pr->set_reg;
+ }
- prio = intc_prio_value(desc, enum_id, 1);
+ fn += (pr->reg_width >> 3) - 1;
bit = pr->reg_width - ((j + 1) * pr->field_width);
BUG_ON(bit < 0);
- return _INTC_MK(fn, i, bit, prio);
+ return _INTC_MK(fn, mode,
+ intc_get_reg(d, reg_e),
+ intc_get_reg(d, reg_d),
+ pr->field_width, bit);
}
}
if (do_grps)
- return intc_prio_data(desc, intc_grp_id(desc, enum_id), 0);
+ return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
+
+ return 0;
+}
+
+static unsigned int __init intc_sense_data(struct intc_desc *desc,
+ struct intc_desc_int *d,
+ intc_enum enum_id)
+{
+ struct intc_sense_reg *sr = desc->sense_regs;
+ unsigned int i, j, fn, bit;
+
+ for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
+ sr = desc->sense_regs + i;
+
+ for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
+ if (sr->enum_ids[j] != enum_id)
+ continue;
+
+ fn = REG_FN_MODIFY_BASE;
+ fn += (sr->reg_width >> 3) - 1;
+ bit = sr->reg_width - ((j + 1) * sr->field_width);
+
+ BUG_ON(bit < 0);
+
+ return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
+ 0, sr->field_width, bit);
+ }
+ }
return 0;
}
-static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
+static void __init intc_register_irq(struct intc_desc *desc,
+ struct intc_desc_int *d,
+ intc_enum enum_id,
unsigned int irq)
{
unsigned int data[2], primary;
@@ -410,15 +470,15 @@ static void __init intc_register_irq(str
* 4. priority, multiple interrupt sources (groups)
*/
- data[0] = intc_mask_data(desc, enum_id, 0);
- data[1] = intc_prio_data(desc, enum_id, 0);
+ data[0] = intc_mask_data(desc, d, enum_id, 0);
+ data[1] = intc_prio_data(desc, d, enum_id, 0);
primary = 0;
if (!data[0] && data[1])
primary = 1;
- data[0] = data[0] ? data[0] : intc_mask_data(desc, enum_id, 1);
- data[1] = data[1] ? data[1] : intc_prio_data(desc, enum_id, 1);
+ data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
+ data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
if (!data[primary])
primary ^= 1;
@@ -426,31 +486,91 @@ static void __init intc_register_irq(str
BUG_ON(!data[primary]); /* must have primary masking method */
disable_irq_nosync(irq);
- set_irq_chip_and_handler_name(irq, &desc->chip,
+ set_irq_chip_and_handler_name(irq, &d->chip,
handle_level_irq, "level");
set_irq_chip_data(irq, (void *)data[primary]);
+ /* record the desired priority level */
+ intc_prio_level[irq] = intc_prio_value(desc, enum_id, 1);
+
/* enable secondary masking method if present */
if (data[!primary])
- intc_reg_fns[_INTC_FN(data[!primary])].enable(desc,
- data[!primary]);
+ _intc_enable(irq, data[!primary]);
+
+ /* add irq to d->prio list if priority is available */
+ if (data[1]) {
+ (d->prio + d->nr_prio)->irq = irq;
+ if (!primary) /* only secondary priority can access regs */
+ (d->prio + d->nr_prio)->handle = data[1];
+ d->nr_prio++;
+ }
+
+ /* add irq to d->sense list if sense is available */
+ data[0] = intc_sense_data(desc, d, enum_id);
+ if (data[0]) {
+ (d->sense + d->nr_sense)->irq = irq;
+ (d->sense + d->nr_sense)->handle = data[0];
+ d->nr_sense++;
+ }
/* irq should be disabled by default */
- desc->chip.mask(irq);
+ d->chip.mask(irq);
}
void __init register_intc_controller(struct intc_desc *desc)
{
- unsigned int i;
+ unsigned int i, k;
+ struct intc_desc_int *d;
+
+ d = alloc_bootmem(sizeof(*d));
+
+ d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
+ d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
+ d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
+
+ d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
+ k = 0;
+
+ if (desc->mask_regs) {
+ for (i = 0; i < desc->nr_mask_regs; i++) {
+ if (desc->mask_regs[i].set_reg)
+ d->reg[k++] = desc->mask_regs[i].set_reg;
+ if (desc->mask_regs[i].clr_reg)
+ d->reg[k++] = desc->mask_regs[i].clr_reg;
+ }
+ }
+
+ if (desc->prio_regs) {
+ d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
+
+ for (i = 0; i < desc->nr_prio_regs; i++) {
+ if (desc->prio_regs[i].set_reg)
+ d->reg[k++] = desc->prio_regs[i].set_reg;
+ if (desc->prio_regs[i].clr_reg)
+ d->reg[k++] = desc->prio_regs[i].clr_reg;
+ }
+ }
+
+ if (desc->sense_regs) {
+ d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
+
+ for (i = 0; i < desc->nr_sense_regs; i++) {
+ if (desc->sense_regs[i].reg)
+ d->reg[k++] = desc->sense_regs[i].reg;
+ }
+ }
+
+ BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
- desc->chip.mask = intc_disable;
- desc->chip.unmask = intc_enable;
- desc->chip.mask_ack = intc_disable;
- desc->chip.set_type = intc_set_sense;
+ d->chip.name = desc->name;
+ d->chip.mask = intc_disable;
+ d->chip.unmask = intc_enable;
+ d->chip.mask_ack = intc_disable;
+ d->chip.set_type = intc_set_sense;
for (i = 0; i < desc->nr_vectors; i++) {
struct intc_vect *vect = desc->vectors + i;
- intc_register_irq(desc, vect->enum_id, evt2irq(vect->vect));
+ intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
}
}
--- 0003/include/asm-sh/hw_irq.h
+++ work/include/asm-sh/hw_irq.h 2007-08-09 19:42:23.000000000 +0900
@@ -75,7 +75,7 @@ struct intc_desc {
unsigned int nr_prio_regs;
struct intc_sense_reg *sense_regs;
unsigned int nr_sense_regs;
- struct irq_chip chip;
+ char *name;
};
#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
@@ -86,7 +86,7 @@ struct intc_desc symbol = { \
_INTC_ARRAY(priorities), \
_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
_INTC_ARRAY(sense_regs), \
- .chip.name = chipname, \
+ chipname, \
}
void __init register_intc_controller(struct intc_desc *desc);
|
|
From: EXTERNAL B. M. (P. ST-FIR/Eng) <ext...@de...> - 2007-08-10 11:47:50
|
Hi, I have fixed the error now.=20 It was caused by the smc911x driver it requested the irq with=20 IRQF_TRIGGER_FALLING and overwrote my settings in the board setup.=20 After changing this to LOW it worked. Regards Markus |
|
From: Magnus D. <mag...@gm...> - 2007-08-10 11:43:59
|
sh: intc - add a clear register to struct intc_prio_reg
We need a secondary register member in struct intc_prio_reg to support dual
priority registers used by ipi on x3.
Signed-off-by: Magnus Damm <da...@ig...>
---
arch/sh/kernel/cpu/irq/intc.c | 8 ++++----
arch/sh/kernel/cpu/sh3/setup-sh7705.c | 16 ++++++++--------
arch/sh/kernel/cpu/sh3/setup-sh770x.c | 16 ++++++++--------
arch/sh/kernel/cpu/sh3/setup-sh7710.c | 20 ++++++++++----------
arch/sh/kernel/cpu/sh4/setup-sh7750.c | 14 +++++++-------
arch/sh/kernel/cpu/sh4/setup-sh7760.c | 22 +++++++++++-----------
arch/sh/kernel/cpu/sh4a/setup-sh7722.c | 26 +++++++++++++-------------
arch/sh/kernel/cpu/sh4a/setup-sh7780.c | 24 +++++++++++++-----------
arch/sh/kernel/cpu/sh4a/setup-sh7785.c | 29 ++++++++++++++++-------------
arch/sh/kernel/cpu/sh4a/setup-shx3.c | 25 ++++++++++++++-----------
include/asm-sh/hw_irq.h | 2 +-
11 files changed, 105 insertions(+), 97 deletions(-)
--- 0001/arch/sh/kernel/cpu/irq/intc.c
+++ work/arch/sh/kernel/cpu/irq/intc.c 2007-08-08 15:21:39.000000000 +0900
@@ -59,14 +59,14 @@ static inline unsigned int set_prio_fiel
static void disable_prio_16(struct intc_desc *desc, unsigned int data)
{
- unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
+ unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr);
}
static void enable_prio_16(struct intc_desc *desc, unsigned int data)
{
- unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
+ unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
unsigned int prio = _INTC_VALUE(data);
ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr);
@@ -74,14 +74,14 @@ static void enable_prio_16(struct intc_d
static void disable_prio_32(struct intc_desc *desc, unsigned int data)
{
- unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
+ unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr);
}
static void enable_prio_32(struct intc_desc *desc, unsigned int data)
{
- unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
+ unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
unsigned int prio = _INTC_VALUE(data);
ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr);
--- 0001/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ work/arch/sh/kernel/cpu/sh3/setup-sh7705.c 2007-08-08 15:10:20.000000000 +0900
@@ -73,14 +73,14 @@ static struct intc_prio priorities[] = {
};
static struct intc_prio_reg prio_registers[] = {
- { 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
- { 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
- { 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
- { 0xa4000018, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } },
- { 0xa400001a, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } },
- { 0xa4080000, 16, 4, /* IPRF */ { 0, 0, USB } },
- { 0xa4080002, 16, 4, /* IPRG */ { TPU0, TPU1 } },
- { 0xa4080004, 16, 4, /* IPRH */ { TPU2, TPU3 } },
+ { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
+ { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
+ { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
+ { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } },
+ { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } },
+ { 0xa4080000, 0, 16, 4, /* IPRF */ { 0, 0, USB } },
+ { 0xa4080002, 0, 16, 4, /* IPRG */ { TPU0, TPU1 } },
+ { 0xa4080004, 0, 16, 4, /* IPRH */ { TPU2, TPU3 } },
};
--- 0001/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ work/arch/sh/kernel/cpu/sh3/setup-sh770x.c 2007-08-08 15:10:49.000000000 +0900
@@ -89,22 +89,22 @@ static struct intc_prio priorities[] = {
};
static struct intc_prio_reg prio_registers[] = {
- { 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
- { 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
+ { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
+ { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
- { 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
- { 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
- { 0xa400001a, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
+ { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
+ { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
+ { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
- { 0xa4000018, 16, 4, /* IPRD */ { PINT07, PINT815, } },
- { 0xa400001a, 16, 4, /* IPRE */ { 0, SCIF0 } },
+ { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
+ { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707)
- { 0xa400001c, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
+ { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
#endif
};
--- 0001/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ work/arch/sh/kernel/cpu/sh3/setup-sh7710.c 2007-08-08 15:11:19.000000000 +0900
@@ -86,18 +86,18 @@ static struct intc_prio priorities[] = {
};
static struct intc_prio_reg prio_registers[] = {
- { 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
- { 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
- { 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
- { 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
- { 0xa400001a, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
- { 0xa4080000, 16, 4, /* IPRF */ { 0, DMAC2 } },
+ { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
+ { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
+ { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
+ { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
+ { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
+ { 0xa4080000, 0, 16, 4, /* IPRF */ { 0, DMAC2 } },
#ifdef CONFIG_CPU_SUBTYPE_SH7710
- { 0xa4080000, 16, 4, /* IPRF */ { IPSEC } },
+ { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC } },
#endif
- { 0xa4080002, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
- { 0xa4080004, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
- { 0xa4080006, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
+ { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
+ { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
+ { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
--- 0001/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ work/arch/sh/kernel/cpu/sh4/setup-sh7750.c 2007-08-08 15:20:04.000000000 +0900
@@ -133,13 +133,13 @@ static struct intc_prio priorities[] = {
};
static struct intc_prio_reg prio_registers[] = {
- { 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
- { 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
- { 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
- { 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
- { 0xfe080000, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
- TMU4, TMU3,
- PCIC1, PCIC0_PCISERR } },
+ { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
+ { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
+ { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
+ { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
+ { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
+ TMU4, TMU3,
+ PCIC1, PCIC0_PCISERR } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
--- 0001/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ work/arch/sh/kernel/cpu/sh4/setup-sh7760.c 2007-08-08 15:20:25.000000000 +0900
@@ -118,17 +118,17 @@ static struct intc_mask_reg mask_registe
};
static struct intc_prio_reg prio_registers[] = {
- { 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
- { 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
- { 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
- { 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
- { 0xfe080000, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
- { 0xfe080004, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
- HAC0, HAC1, I2C0, I2C1 } },
- { 0xfe080008, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
- SCIF1, SCIF2, SIM, HSPI } },
- { 0xfe08000c, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
- MFI, 0, ADC, CMT } },
+ { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
+ { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
+ { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
+ { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
+ { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
+ { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
+ HAC0, HAC1, I2C0, I2C1 } },
+ { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
+ SCIF1, SCIF2, SIM, HSPI } },
+ { 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
+ MFI, 0, ADC, CMT } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
--- 0001/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-sh7722.c 2007-08-08 15:13:57.000000000 +0900
@@ -169,19 +169,19 @@ static struct intc_mask_reg mask_registe
};
static struct intc_prio_reg prio_registers[] = {
- { 0xa4080000, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
- { 0xa4080004, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
- { 0xa4080008, 16, 4, /* IPRC */ { } },
- { 0xa408000c, 16, 4, /* IPRD */ { } },
- { 0xa4080010, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
- { 0xa4080014, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
- { 0xa4080018, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
- { 0xa408001c, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
- { 0xa4080020, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
- { 0xa4080024, 16, 4, /* IPRJ */ { 0, 0, SIU } },
- { 0xa4080028, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
- { 0xa408002c, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
- { 0xa4140010, 32, 4, /* INTPRI00 */
+ { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
+ { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
+ { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
+ { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
+ { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
+ { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
+ { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
+ { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
+ { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
+ { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
+ { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
+ { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
+ { 0xa4140010, 0, 32, 4, /* INTPRI00 */
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};
--- 0001/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-sh7780.c 2007-08-08 15:16:38.000000000 +0900
@@ -181,15 +181,17 @@ static struct intc_mask_reg mask_registe
};
static struct intc_prio_reg prio_registers[] = {
- { 0xffd40000, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, TMU2, TMU2_TICPI } },
- { 0xffd40004, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
- { 0xffd40008, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
- { 0xffd4000c, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
- { 0xffd40010, 32, 8, /* INT2PRI4 */ { CMT, HAC, PCISERR, PCIINTA, } },
- { 0xffd40014, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
- PCIINTD, PCIC5 } },
- { 0xffd40018, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
- { 0xffd4001c, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
+ { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
+ TMU2, TMU2_TICPI } },
+ { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
+ { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
+ { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
+ { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
+ PCISERR, PCIINTA, } },
+ { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
+ PCIINTD, PCIC5 } },
+ { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
+ { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities,
@@ -210,8 +212,8 @@ static struct intc_mask_reg irq_mask_reg
};
static struct intc_prio_reg irq_prio_registers[] = {
- { 0xffd00010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
- IRQ4, IRQ5, IRQ6, IRQ7 } },
+ { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
+ IRQ4, IRQ5, IRQ6, IRQ7 } },
};
static struct intc_sense_reg irq_sense_registers[] = {
--- 0001/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-sh7785.c 2007-08-08 15:16:22.000000000 +0900
@@ -206,19 +206,22 @@ static struct intc_mask_reg mask_registe
};
static struct intc_prio_reg prio_registers[] = {
- { 0xffd00010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
- IRQ4, IRQ5, IRQ6, IRQ7 } },
- { 0xffd40000, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, TMU2, TMU2_TICPI } },
- { 0xffd40004, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
- { 0xffd40008, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
- { 0xffd4000c, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
- { 0xffd40010, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
- { 0xffd40014, 32, 8, /* INT2PRI5 */ { HAC0, HAC1, PCISERR, PCIINTA } },
- { 0xffd40018, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
- PCIINTD, PCIC5 } },
- { 0xffd4001c, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
- { 0xffd40020, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
- { 0xffd40024, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
+ { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
+ IRQ4, IRQ5, IRQ6, IRQ7 } },
+ { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
+ TMU2, TMU2_TICPI } },
+ { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
+ { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
+ SCIF2, SCIF3 } },
+ { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
+ { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
+ { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
+ PCISERR, PCIINTA } },
+ { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
+ PCIINTD, PCIC5 } },
+ { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
+ { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
+ { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, priorities,
--- 0001/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-shx3.c 2007-08-08 15:17:21.000000000 +0900
@@ -191,18 +191,21 @@ static struct intc_mask_reg mask_registe
};
static struct intc_prio_reg prio_registers[] = {
- { 0xfe410010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
+ { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
- { 0xfe410800, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
- TMU3, TMU2, TMU1, TMU0 } },
- { 0xfe410804, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
- SCIF3, SCIF2, SCIF1, SCIF0 } },
- { 0xfe410808, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0, PCII56789, PCII4,
- PCII3, PCII2, PCII1, PCII0 } },
- { 0xfe41080c, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
- VIN1, VIN0, IIC, DU} },
- { 0xfe410810, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
- GPIO2, GPIO1, GPIO0, IRM } },
+ { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
+ TMU3, TMU2, TMU1, TMU0 } },
+ { 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
+ SCIF3, SCIF2,
+ SCIF1, SCIF0 } },
+ { 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0,
+ PCII56789, PCII4,
+ PCII3, PCII2,
+ PCII1, PCII0 } },
+ { 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
+ VIN1, VIN0, IIC, DU} },
+ { 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
+ GPIO2, GPIO1, GPIO0, IRM } },
};
static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, priorities,
--- 0001/include/asm-sh/hw_irq.h
+++ work/include/asm-sh/hw_irq.h 2007-08-08 15:09:21.000000000 +0900
@@ -53,7 +53,7 @@ struct intc_mask_reg {
};
struct intc_prio_reg {
- unsigned long reg, reg_width, field_width;
+ unsigned long set_reg, clr_reg, reg_width, field_width;
intc_enum enum_ids[16];
};
|
|
From: Magnus D. <mag...@gm...> - 2007-08-10 11:33:56
|
sh: x3 - fix setup_bootmem_node() compile error with shx3_defconfig
This makes sure the function prototype for setup_bootmem_node() gets included.
The file setup-shx3.c does not compile otherwise for CONFIG_NUMA=n.
Signed-off-by: Magnus Damm <da...@ig...>
---
arch/sh/kernel/cpu/sh4a/setup-shx3.c | 1 +
1 file changed, 1 insertion(+)
--- 0001/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ work/arch/sh/kernel/cpu/sh4a/setup-shx3.c 2007-08-09 19:33:32.000000000 +0900
@@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/io.h>
+#include <asm/mmzone.h>
#include <asm/sci.h>
static struct plat_sci_port sci_platform_data[] = {
|
|
From: Markus B. <sup...@go...> - 2007-08-08 22:38:20
|
Hello Paul,
all clock-sh*.c in the sh3 folder seem to be the same except for the bitmasks and the mult/div tables.
So I thought it would be a good thing to send code duplication to ifdef hell ;-)
For that I created asm-sh/cpu-sh3/clock.h and defined the bitmasks there.
I don't have a SH7712 datasheet, so I couldn't check it.
btw, what about a datasheets page on the linux-sh wiki?
I left clock-sh7709.c because it uses set_bus_parent, which isn't used by the other cpus.
I don't know if that's important, but I don't want to break anything.
It would be great if there will be a "#else #error" in clock.h if all CPUs are in.
Because:
1. this would make things easier if an old cpu will be removed
2. you can be sure the cpu is supported, or not.
This patch is only tested on SH7720, but doesn't make any "real" changes.
Signed-off by: Markus Brunner <sup...@gm...>
Signed-off by: Mark Jonas <to...@gm...>
---
arch/sh/kernel/cpu/sh3/Makefile | 3 -
arch/sh/kernel/cpu/sh3/clock-sh3.c | 31 ++++++++----
arch/sh/kernel/cpu/sh3/clock-sh7705.c | 84 ----------------------------------
arch/sh/kernel/cpu/sh3/clock-sh7706.c | 84 ----------------------------------
arch/sh/kernel/cpu/sh3/clock-sh7710.c | 78 -------------------------------
include/asm-sh/cpu-sh3/clock.h | 81 ++++++++++++++++++++++++++++++++
6 files changed, 101 insertions(+), 260 deletions(-)
diff -upNr sh-2.6-orig/arch/sh/kernel/cpu/sh3/Makefile sh-2.6-mod/arch/sh/kernel/cpu/sh3/Makefile
--- sh-2.6-orig/arch/sh/kernel/cpu/sh3/Makefile 2007-07-31 12:11:46.000000000 +0200
+++ sh-2.6-mod/arch/sh/kernel/cpu/sh3/Makefile 2007-08-08 23:57:56.000000000 +0200
@@ -15,9 +15,6 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setu
# Primary on-chip clocks (common)
clock-$(CONFIG_CPU_SH3) := clock-sh3.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7705) := clock-sh7705.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7706) := clock-sh7706.o
clock-$(CONFIG_CPU_SUBTYPE_SH7709) := clock-sh7709.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7710) := clock-sh7710.o
obj-y += $(clock-y)
diff -upNr sh-2.6-orig/arch/sh/kernel/cpu/sh3/clock-sh3.c sh-2.6-mod/arch/sh/kernel/cpu/sh3/clock-sh3.c
--- sh-2.6-orig/arch/sh/kernel/cpu/sh3/clock-sh3.c 2007-07-04 21:46:25.000000000 +0200
+++ sh-2.6-mod/arch/sh/kernel/cpu/sh3/clock-sh3.c 2007-08-09 00:16:34.000000000 +0200
@@ -21,16 +21,19 @@
#include <asm/clock.h>
#include <asm/freq.h>
#include <asm/io.h>
+#include <asm/cpu/clock.h>
-static int stc_multipliers[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
-static int ifc_divisors[] = { 1, 2, 3, 4, 1, 1, 1, 1 };
-static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
+static int stc_multipliers[] = STC_MULTIPLIERS;
+static int ifc_divisors[] = IFC_DIVISORS;
+static int pfc_divisors[] = PFC_DIVISORS;
static void master_clk_init(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
- int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
-
+ int idx = (frqcr & PFC_BITS) >> PFC_BITS_SHIFT;
+#ifdef PFC_BITS_H
+ idx |= (frqcr & PFC_BITS_H) >> PFC_BITS_H_SHIFT;
+#endif
clk->rate *= pfc_divisors[idx];
}
@@ -41,8 +44,10 @@ static struct clk_ops sh3_master_clk_ops
static void module_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
- int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
-
+ int idx = (frqcr & PFC_BITS) >> PFC_BITS_SHIFT;
+#ifdef PFC_BITS_H
+ idx |= (frqcr & PFC_BITS_H) >> PFC_BITS_H_SHIFT;
+#endif
clk->rate = clk->parent->rate / pfc_divisors[idx];
}
@@ -53,8 +58,10 @@ static struct clk_ops sh3_module_clk_ops
static void bus_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
- int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
-
+ int idx = (frqcr & STC_BITS) >> STC_BITS_SHIFT;
+#ifdef STC_BITS_H
+ idx |= (frqcr & STC_BITS_H) >> STC_BITS_H_SHIFT;
+#endif
clk->rate = clk->parent->rate / stc_multipliers[idx];
}
@@ -65,8 +72,10 @@ static struct clk_ops sh3_bus_clk_ops =
static void cpu_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
- int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
-
+ int idx = (frqcr & IFC_BITS) >> IFC_BITS_SHIFT;
+#ifdef IFC_BITS_H
+ idx |= ((frqcr & IFC_BITS_H) >> IFC_BITS_H_SHIFT) |
+#endif
clk->rate = clk->parent->rate / ifc_divisors[idx];
}
diff -upNr sh-2.6-orig/arch/sh/kernel/cpu/sh3/clock-sh7705.c sh-2.6-mod/arch/sh/kernel/cpu/sh3/clock-sh7705.c
--- sh-2.6-orig/arch/sh/kernel/cpu/sh3/clock-sh7705.c 2007-07-04 21:46:25.000000000 +0200
+++ sh-2.6-mod/arch/sh/kernel/cpu/sh3/clock-sh7705.c 1970-01-01 01:00:00.000000000 +0100
@@ -1,84 +0,0 @@
-/*
- * arch/sh/kernel/cpu/sh3/clock-sh7705.c
- *
- * SH7705 support for the clock framework
- *
- * Copyright (C) 2005 Paul Mundt
- *
- * FRQCR parsing hacked out of arch/sh/kernel/time.c
- *
- * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
- * Copyright (C) 2000 Philipp Rumpf <pr...@tu...>
- * Copyright (C) 2002, 2003, 2004 Paul Mundt
- * Copyright (C) 2002 M. R. Brown <mr...@li...>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <asm/clock.h>
-#include <asm/freq.h>
-#include <asm/io.h>
-
-/*
- * SH7705 uses the same divisors as the generic SH-3 case, it's just the
- * FRQCR layout that is a bit different..
- */
-static int stc_multipliers[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
-static int ifc_divisors[] = { 1, 2, 3, 4, 1, 1, 1, 1 };
-static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
-
-static void master_clk_init(struct clk *clk)
-{
- clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0003];
-}
-
-static struct clk_ops sh7705_master_clk_ops = {
- .init = master_clk_init,
-};
-
-static void module_clk_recalc(struct clk *clk)
-{
- int idx = ctrl_inw(FRQCR) & 0x0003;
- clk->rate = clk->parent->rate / pfc_divisors[idx];
-}
-
-static struct clk_ops sh7705_module_clk_ops = {
- .recalc = module_clk_recalc,
-};
-
-static void bus_clk_recalc(struct clk *clk)
-{
- int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8;
- clk->rate = clk->parent->rate / stc_multipliers[idx];
-}
-
-static struct clk_ops sh7705_bus_clk_ops = {
- .recalc = bus_clk_recalc,
-};
-
-static void cpu_clk_recalc(struct clk *clk)
-{
- int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4;
- clk->rate = clk->parent->rate / ifc_divisors[idx];
-}
-
-static struct clk_ops sh7705_cpu_clk_ops = {
- .recalc = cpu_clk_recalc,
-};
-
-static struct clk_ops *sh7705_clk_ops[] = {
- &sh7705_master_clk_ops,
- &sh7705_module_clk_ops,
- &sh7705_bus_clk_ops,
- &sh7705_cpu_clk_ops,
-};
-
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
-{
- if (idx < ARRAY_SIZE(sh7705_clk_ops))
- *ops = sh7705_clk_ops[idx];
-}
-
diff -upNr sh-2.6-orig/arch/sh/kernel/cpu/sh3/clock-sh7706.c sh-2.6-mod/arch/sh/kernel/cpu/sh3/clock-sh7706.c
--- sh-2.6-orig/arch/sh/kernel/cpu/sh3/clock-sh7706.c 2007-07-04 21:46:25.000000000 +0200
+++ sh-2.6-mod/arch/sh/kernel/cpu/sh3/clock-sh7706.c 1970-01-01 01:00:00.000000000 +0100
@@ -1,84 +0,0 @@
-/*
- * arch/sh/kernel/cpu/sh3/clock-sh7706.c
- *
- * SH7706 support for the clock framework
- *
- * Copyright (C) 2006 Takashi YOSHII
- *
- * Based on arch/sh/kernel/cpu/sh3/clock-sh7709.c
- * Copyright (C) 2005 Andriy Skulysh
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <asm/clock.h>
-#include <asm/freq.h>
-#include <asm/io.h>
-
-static int stc_multipliers[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
-static int ifc_divisors[] = { 1, 2, 4, 1, 3, 1, 1, 1 };
-static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
-
-static void master_clk_init(struct clk *clk)
-{
- int frqcr = ctrl_inw(FRQCR);
- int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
-
- clk->rate *= pfc_divisors[idx];
-}
-
-static struct clk_ops sh7706_master_clk_ops = {
- .init = master_clk_init,
-};
-
-static void module_clk_recalc(struct clk *clk)
-{
- int frqcr = ctrl_inw(FRQCR);
- int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
-
- clk->rate = clk->parent->rate / pfc_divisors[idx];
-}
-
-static struct clk_ops sh7706_module_clk_ops = {
- .recalc = module_clk_recalc,
-};
-
-static void bus_clk_recalc(struct clk *clk)
-{
- int frqcr = ctrl_inw(FRQCR);
- int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
-
- clk->rate = clk->parent->rate / stc_multipliers[idx];
-}
-
-static struct clk_ops sh7706_bus_clk_ops = {
- .recalc = bus_clk_recalc,
-};
-
-static void cpu_clk_recalc(struct clk *clk)
-{
- int frqcr = ctrl_inw(FRQCR);
- int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
-
- clk->rate = clk->parent->rate / ifc_divisors[idx];
-}
-
-static struct clk_ops sh7706_cpu_clk_ops = {
- .recalc = cpu_clk_recalc,
-};
-
-static struct clk_ops *sh7706_clk_ops[] = {
- &sh7706_master_clk_ops,
- &sh7706_module_clk_ops,
- &sh7706_bus_clk_ops,
- &sh7706_cpu_clk_ops,
-};
-
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
-{
- if (idx < ARRAY_SIZE(sh7706_clk_ops))
- *ops = sh7706_clk_ops[idx];
-}
diff -upNr sh-2.6-orig/arch/sh/kernel/cpu/sh3/clock-sh7710.c sh-2.6-mod/arch/sh/kernel/cpu/sh3/clock-sh7710.c
--- sh-2.6-orig/arch/sh/kernel/cpu/sh3/clock-sh7710.c 2007-07-31 12:11:46.000000000 +0200
+++ sh-2.6-mod/arch/sh/kernel/cpu/sh3/clock-sh7710.c 1970-01-01 01:00:00.000000000 +0100
@@ -1,78 +0,0 @@
-/*
- * arch/sh/kernel/cpu/sh3/clock-sh7710.c
- *
- * SH7710 support for the clock framework
- *
- * Copyright (C) 2005 Paul Mundt
- *
- * FRQCR parsing hacked out of arch/sh/kernel/time.c
- *
- * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
- * Copyright (C) 2000 Philipp Rumpf <pr...@tu...>
- * Copyright (C) 2002, 2003, 2004 Paul Mundt
- * Copyright (C) 2002 M. R. Brown <mr...@li...>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <asm/clock.h>
-#include <asm/freq.h>
-#include <asm/io.h>
-
-static int md_table[] = { 1, 2, 3, 4, 6, 8, 12 };
-
-static void master_clk_init(struct clk *clk)
-{
- clk->rate *= md_table[ctrl_inw(FRQCR) & 0x0007];
-}
-
-static struct clk_ops sh7710_master_clk_ops = {
- .init = master_clk_init,
-};
-
-static void module_clk_recalc(struct clk *clk)
-{
- int idx = (ctrl_inw(FRQCR) & 0x0007);
- clk->rate = clk->parent->rate / md_table[idx];
-}
-
-static struct clk_ops sh7710_module_clk_ops = {
- .recalc = module_clk_recalc,
-};
-
-static void bus_clk_recalc(struct clk *clk)
-{
- int idx = (ctrl_inw(FRQCR) & 0x0700) >> 8;
- clk->rate = clk->parent->rate / md_table[idx];
-}
-
-static struct clk_ops sh7710_bus_clk_ops = {
- .recalc = bus_clk_recalc,
-};
-
-static void cpu_clk_recalc(struct clk *clk)
-{
- int idx = (ctrl_inw(FRQCR) & 0x0070) >> 4;
- clk->rate = clk->parent->rate / md_table[idx];
-}
-
-static struct clk_ops sh7710_cpu_clk_ops = {
- .recalc = cpu_clk_recalc,
-};
-
-static struct clk_ops *sh7710_clk_ops[] = {
- &sh7710_master_clk_ops,
- &sh7710_module_clk_ops,
- &sh7710_bus_clk_ops,
- &sh7710_cpu_clk_ops,
-};
-
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
-{
- if (idx < ARRAY_SIZE(sh7710_clk_ops))
- *ops = sh7710_clk_ops[idx];
-}
-
diff -upNr sh-2.6-orig/include/asm-sh/cpu-sh3/clock.h sh-2.6-mod/include/asm-sh/cpu-sh3/clock.h
--- sh-2.6-orig/include/asm-sh/cpu-sh3/clock.h 1970-01-01 01:00:00.000000000 +0100
+++ sh-2.6-mod/include/asm-sh/cpu-sh3/clock.h 2007-08-09 00:09:15.000000000 +0200
@@ -0,0 +1,81 @@
+/*
+ * include/asm-sh/cpu-sh3/clock.h
+ *
+ * Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ * Multipliers and divisors for the SH3 clock
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _CPU_SH3_CLOCK_H
+#define _CPU_SH3_CLOCK_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7705)
+#define PFC_BITS 0x0003
+#define PFC_BITS_SHIFT 0
+#define STC_BITS 0x0300
+#define STC_BITS_SHIFT 8
+#define IFC_BITS 0x0030
+#define IFC_BITS_SHIFT 4
+
+#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7708)
+/* only SH7708, SH7708S and not SH7708R are supported */
+#define PFC_BITS 0x0003
+#define PFC_BITS_SHIFT 0
+#define STC_BITS 0x0030
+#define STC_BITS_SHIFT 4
+#define IFC_BITS 0x000c
+#define IFC_BITS_SHIFT 2
+
+#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
+#define PFC_BITS 0x0007
+#define PFC_BITS_SHIFT 0
+#define STC_BITS 0x0700
+#define STC_BITS_SHIFT 8
+#define IFC_BITS 0x0070
+#define IFC_BITS_SHIFT 4
+
+#else
+/* CONFIG_CPU_SUBTYPE_SH7706 */
+#define PFC_BITS_H 0x2000
+#define PFC_BITS_H_SHIFT 11
+#define PFC_BITS 0x0003
+#define PFC_BITS_SHIFT 0
+#define STC_BITS_H 0x8000
+#define STC_BITS_H_SHIFT 13
+#define STC_BITS 0x0030
+#define STC_BITS_SHIFT 4
+#define IFC_BITS_H 0x4000
+#define IFC_BITS_H_SHIFT 12
+#define IFC_BITS 0x000c
+#define IFC_BITS_SHIFT 2
+#endif
+
+/*
+ * Multipliers and Divisor tables
+ */
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7708)
+#define STC_MULTIPLIERS { 1, 2, 4, 1, 3, 6, 1, 1 }
+#define IFC_DIVISORS { 1, 2, 4, 1, 3, 1, 1, 1 }
+#define PFC_DIVISORS STC_MULTIPLIERS
+
+#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
+#define STC_MULTIPLIERS { 1, 2, 3, 4, 6, 8, 12 }
+#define IFC_DIVISORS STC_MULTIPLIERS
+#define PFC_DIVISORS STC_MULTIPLIERS
+
+#else
+/* CONFIG_CPU_SUBTYPE_SH7705 */
+#define STC_MULTIPLIERS { 1, 2, 3, 4, 6, 1, 1, 1 }
+#define IFC_DIVISORS { 1, 2, 3, 4, 1, 1, 1, 1 }
+#define PFC_DIVISORS STC_MULTIPLIERS
+#endif
+
+#endif /* _CPU_SH3_CLOCK_H */
|
|
From: Kristoffer E. <kri...@gm...> - 2007-08-08 18:20:41
|
Greetings,
Jlime-current uses linus.git with lethal.git merge. I havent started bugtracking it yet, but quite obvious it has to do with IRQ updates.
Feedback appreciated.
Best wishes
Kristoffer
The big lines are of course:
hp6x0_apm: IRQ 32 request failed
hp680_touchscreen.c: Can't allocate irq 35
HD64461 PCMCIA socket 1: can't request irq 93
ata1: PATA max PIO0 cmd 0xb50001f0 ctl 0xb50001fe bmdma 0x00000000 irq 93
ata1.00: qc timeout (cmd 0x91)
ata1.00: failed to IDENTIFY (INIT_DEV_PARAMS failed, err_mask=0x4)
ata1.00: qc timeout (cmd 0x91)
ata1.00: failed to IDENTIFY (INIT_DEV_PARAMS failed, err_mask=0x4)
ata1.00: limiting speed to UDMA7:PIO5
ata1.00: qc timeout (cmd 0x91)
ata1.00: failed to IDENTIFY (INIT_DEV_PARAMS failed, err_mask=0x4)
ata1: EH pending after completion, repeating EH (cnt=4)
Bootlog:
Linux version 2.6.23-rc1-gac42b72f-dirty (kristoffer@NightCrawler) (gcc version 3.4.5) #2 Sun Jul 29 17:28:02 PDT 2007
Booting machvec: hp6xx
Node 0: start_pfn = 0xd000, low = 0xf000
Zone PFN ranges:
Normal 53248 -> 61440
Movable zone start PFN for each node
early_node_map[1] active PFN ranges
0: 53248 -> 61440
Built 1 zonelists in Zone order. Total pages: 8128
Kernel command line: mem=32M root=/dev/sda4 console=ttySC1,115200 init=/bin/sh
PID hash table entries: 128 (order: 7, 512 bytes)
Using tmu for system timer
Using 5.528 MHz high precision timer.
Console: colour dummy device 80x25
Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)
Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)
Memory: 29908k/32768k available (1896k kernel code, 499k data, 72k init)
Mount-cache hash table entries: 512
CPU: SH7729
NET: Registered protocol family 16
SCSI subsystem initialized
DMA: Registering DMA API.
DMA: Registering sh_dmac handler (4 channels).
Time: SuperH clocksource has been installed.
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 1024 (order: 1, 8192 bytes)
TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
TCP: Hash tables configured (established 1024 bind 1024)
TCP reno registered
hp6x0_apm: IRQ 32 request failed
HD64461 configured at 0xb0000000 on irq 36(mapped into 80 to 95)
HD64461: enabling PCMCIA devices
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
Console: switching to colour frame buffer device 80x30
fb0: Hitachi HD64461 frame buffer device
SuperH SCI(F) driver initialized
sh-sci: ttySC0 at MMIO 0xfffffe80 (irq = 25) is a sci
sh-sci: ttySC1 at MMIO 0xa4000150 (irq = 59) is a scif
console [ttySC1] enabled
sh-sci sh-sci: Attempting to register port 3 when only 2 are available.
sh-sci sh-sci: Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!
loop: module loaded
SCSI Media Changer driver v0.25
scsi0 : pata_platform
ata1: PATA max PIO0 cmd 0xb50001f0 ctl 0xb50001fe bmdma 0x00000000 irq 93
ata1.00: qc timeout (cmd 0x91)
ata1.00: failed to IDENTIFY (INIT_DEV_PARAMS failed, err_mask=0x4)
ata1.00: qc timeout (cmd 0x91)
ata1.00: failed to IDENTIFY (INIT_DEV_PARAMS failed, err_mask=0x4)
ata1.00: limiting speed to UDMA7:PIO5
ata1.00: qc timeout (cmd 0x91)
ata1.00: failed to IDENTIFY (INIT_DEV_PARAMS failed, err_mask=0x4)
ata1: EH pending after completion, repeating EH (cnt=4)
HD64461 PCMCIA bridge.
HD64461 Initializing Socket 0, IRQ 95
HD64461 PCMCIA socket 1: can't request irq 93
mice: PS/2 mouse device common for all mice
hp680_touchscreen.c: Can't allocate irq 35
sh-rtc sh-rtc: rtc core: registered sh as rtc0
TCP cubic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
NET: Registered protocol family 15
ieee80211: 802.11 data/management/control stack, git-1.1.13
ieee80211: Copyright (C) 2004-2005 Intel Corporation <jke...@li...>
sh-rtc sh-rtc: setting the system clock to 1999-01-01 00:03:12 (915148992)
VFS: Cannot open root device "sda4" or unknown-block(0,0)
Please append a correct "root=" boot option; here are the available partitions:
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
--
Kristoffer Ericson <Kri...@Gm...>
|
|
From: EXTERNAL B. M. (P. ST-FIR/Eng) <ext...@de...> - 2007-08-08 09:30:12
|
Hello Magnus, I've migrated the SH7720 setup to the new intc code. I've some questions about the new INTC code. What are groups exactly for? Group irqs which belong to one logical unit? Group irqs which must share the ipr, or a similar register? I assume both, but I'm not sure. How to handle irqs which don't have a ipr register and don't have a mask register? H-UDI hasn't a mask/ipr register on SH7720, so it would trigger the BUG_ON in intc_register_irq. I won't use that irq, so I didnt include it. And now the important question. How to set the board specific irqs? I don't need a special irq demux, or irq mask, like the existing boards. (se7722) I just have to set the priority and the level-sense. I thought set_irq_type(...) is enough if the registers got correctly associated with the irqs in the CPU setup. The sens register gets correctly set, but I get the following error message, when using the ethernet device (IRQ3). Also I don't know how to set the board specific irq-prioritys in a clean way.=20 At the moment I set it in the CPU setup. Do I have to declare an intc description again, or is there a better way? udhcpc (v1.6.1) started eth0: link down eth0: link up, 100Mbps, full-duplex, lpa 0x05E1 irq 35: nobody cared (try booting with the "irqpoll" option) Stack: (0x8feb3cf8 to 0x8feb4000) 3ce0: 8c006d8e 8feb3d08 3d00: 8c2966d4 8c29367c 8c03d3f4 8feb3d10 8c03d64a 8feb3d24 00000100 8c2966d4 3d20: 00000000 00000000 00000000 8c03dfaa 8feb3d4c 8c2e5710 0000000a 00000000 3d40: 8feb3e18 00000023 8c29367c 8c0037ec 8feb3d5c 8c2eabbc 00000033 8c0070dc 3d60: 8feb3dd0 00000000 8c0037b0 ffffffff 000000f0 00000000 40000000 00000100 3d80: 8c290334 0000000c a4140016 00000004 00000002 8c2eabbc 00000000 00000000 3da0: 0000000a 8c2e5710 8feb3dd0 8feb3dd0 8c019772 8c019886 40000000 00497300 3dc0: 00000340 00000038 ffffffff ffffffff 8c019886 8feb3df0 a8000068 008c42c8 3de0: 00000000 00000000 8c2eabbc 000000f0 8c0199f6 8feb3dfc 00000033 8c0037f2 3e00: 8feb3e04 8c0070dc 8feb3e78 a8000000 8c0037b0 ffffffff 00000000 00000000 3e20: 40000000 00000001 008c42c8 a800005c ffffffff 000000f0 a800005c 8c28e090 3e40: a8000000 00000000 008c42c8 a8000068 8feb3e78 8feb3e78 8c1652ba 8c16527c 3e60: 40000000 00497300 00000340 00000000 ffffffff ffffffff 8df57462 8c167554 3e80: 8feb3e9c 00000000 8c190e10 00001002 00000000 8df57400 8df57080 8c191004 3ea0: 8feb3eac 8df570fc 8df57080 8c191544 8feb3ec0 8df570fc 8df57080 00001043 3ec0: 8c1d0158 8feb3ee0 8dff9df8 00008914 00000000 ffffff9d 8df57080 7bbc1c8c 3ee0: 30687465 00000000 00000000 00000000 00001043 00000000 004bf53c 004819f2 3f00: 00001043 00000000 004bf53c 004819f2 00000000 00000000 8c1d2058 8feb3f38 3f20: 00494834 fffffff7 7bbc1c8c 7bbc1c8c 8c3b7238 00008914 8c18350a 8feb3f40 3f40: 8c070714 8feb3f58 7bbc1c8c 00000000 8c3b7238 7bbc1c8c 8c0707a2 8feb3f64 3f60: 7bbc1c8c 8fed2000 8fee16b8 8c070aa2 8feb3f80 00008914 00000004 8c3b7238 3f80: 00000000 8c0071fc 004948de 7bbc1cac ffffff0f 00000001 8feb3ff8 8c070a70 3fa0: 0044f280 00001002 7bbc1c9c 00000036 00000004 00008914 7bbc1c8c 00000000 3fc0: 7bbc1cac 00000120 7bbc1f1c 00000004 7bbc1cac 00494834 004948de 7bbc1c8c 3fe0: 0044f284 0040c9b8 00000000 00497300 00000022 00000000 0000004c 00000160 Call trace: [<8c006d8e>] dump_stack+0xe/0x280 [<8c03d3f4>] __report_bad_irq+0x24/0x90 [<8c03d64a>] note_interrupt+0x1ea/0x220 [<8c03dfaa>] handle_level_irq+0xba/0x100 [<8c0037ec>] do_IRQ+0x3c/0x90 [<8c0070dc>] ret_from_exception+0x0/0x14 [<8c0037b0>] do_IRQ+0x0/0x90 [<8c019772>] __do_softirq+0x32/0xe0 [<8c019886>] do_softirq+0x66/0x80 [<8c019886>] do_softirq+0x66/0x80 [<8c0199f6>] irq_exit+0x36/0x50 [<8c0037f2>] do_IRQ+0x42/0x90 [<8c0070dc>] ret_from_exception+0x0/0x14 [<8c0037b0>] do_IRQ+0x0/0x90 [<8c1652ba>] smc911x_enable+0x3aa/0x430 [<8c16527c>] smc911x_enable+0x36c/0x430 [<8c167554>] smc911x_open+0x64/0xe0 [<8c190e10>] dev_set_rx_mode+0x0/0x50 [<8c191004>] dev_open+0xa4/0x100 [<8c191544>] dev_change_flags+0x74/0x1d0 [<8c1d0158>] devinet_ioctl+0x5f8/0x6e0 [<8c1d2058>] inet_ioctl+0x88/0xf0 [<8c18350a>] sock_ioctl+0xea/0x260 [<8c070714>] do_ioctl+0x54/0x70 [<8c0707a2>] vfs_ioctl+0x72/0x340 [<8c070aa2>] sys_ioctl+0x32/0x80 [<8c0071fc>] syscall_call+0xc/0x10 [<8c070a70>] sys_ioctl+0x0/0x80 handlers: [<8c1667b0>] (smc911x_interrupt+0x0/0x930) Disabling IRQ #35 |
|
From: Paul M. <le...@li...> - 2007-08-07 10:08:40
|
On Tue, Aug 07, 2007 at 11:58:45AM +0200, EXTERNAL Brunner Markus (Praktikant; ST-FIR/Eng) wrote:
> Paul Mundt wrote:
> > Does something like this help?
> >
> > diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
> > index 23c5948..129b2cf 100644
> > --- a/arch/sh/kernel/machvec.c
> > +++ b/arch/sh/kernel/machvec.c
> > @@ -91,6 +91,13 @@ void __init sh_mv_setup(void)
> > (unsigned long)&__machvec_start);
> >
> > /*
> > + * Sanity check for machvec section alignment. Ensure
> > + * __initmv hasn't been misused.
> > + */
> > + if (machvec_size % sizeof(struct sh_machine_vector))
> > + panic("machvec misaligned, invalid __initmv
> use?");
> > +
> > + /*
> > * If the machvec hasn't been preselected, use the first
> > * vector (usually the only one) from .machvec.init.
> > */
>
> It would have found my fault and it will probably find the faults of
> others.
> I don't think this error is very extraordinary, because __initmv abuse
> was once a goodness. ;-)
> http://lkml.org/lkml/diff/2007/6/23/116/1
>
Yes, I didn't ack the patch primarily because it completely missed the
point. The __initmv cleanup largely happened here:
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=82f81f4784479df17a80caff4a7156da0a2f7dea
I'll apply the sanity check so people aren't more inclined to step on
this. This is actually the first time this issue has come up, but it's
also the first time we've enabled use of the machvec section
unconditionally. Hopefully the sanity check will curb some confusion.
|
|
From: EXTERNAL B. M. (P. ST-FIR/Eng) <ext...@de...> - 2007-08-07 09:58:58
|
Paul Mundt wrote:
> Does something like this help?
>=20
> diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
> index 23c5948..129b2cf 100644
> --- a/arch/sh/kernel/machvec.c
> +++ b/arch/sh/kernel/machvec.c
> @@ -91,6 +91,13 @@ void __init sh_mv_setup(void)
> (unsigned long)&__machvec_start);
>=20
> /*
> + * Sanity check for machvec section alignment. Ensure
> + * __initmv hasn't been misused.
> + */
> + if (machvec_size % sizeof(struct sh_machine_vector))
> + panic("machvec misaligned, invalid __initmv
use?");
> +
> + /*
> * If the machvec hasn't been preselected, use the first
> * vector (usually the only one) from .machvec.init.
> */
It would have found my fault and it will probably find the faults of
others.=20
I don't think this error is very extraordinary, because __initmv abuse
was once a goodness. ;-)
http://lkml.org/lkml/diff/2007/6/23/116/1
|
|
From: Paul M. <le...@li...> - 2007-08-07 09:18:39
|
On Tue, Aug 07, 2007 at 11:09:47AM +0200, EXTERNAL Brunner Markus (Praktikant; ST-FIR/Eng) wrote:
> Paul Mundt wrote:
> > On Tue, Aug 07, 2007 at 10:37:10AM +0200, EXTERNAL Brunner Markus
> > (Praktikant; ST-FIR/Eng) wrote:
> >> markus@linux-markus:~/kernels$ sh3-unknown-linux-gnu-nm vmlinux |
> >> grep mpr2 8c2c18c0 t __initcall_mpr2_devices_setup6
> >> 8c2c1b00 T init_mpr2_IRQ
> >> 8c2c03d4 t mpr2_devices
> >> 8c2b1870 t mpr2_devices_setup
> >> 8c2b16d0 t mpr2_setup
> >> 8c2c1a70 t mv_mpr2
> >>
> >> This is with earlyprintk enabled. Now size and addresses have
> >> changed and mv_mpr2 isn't at the beginning of the machvec anymore.
> >>
> > This is rather interesting. Looking at your board patch again, it
> > seems
> > like this might be caused by the __initmv sprinkling you have on other
> > functions. __initmv is intended _only_ for the machvec description
> > itself, init functions referenced from within it should be flagged as
> > __init. We only ever expect to find full machvec structs within the
> > machvec section, so this is likely what is screwing it up. Please try
> > again with __initmv removed from everything but the machvec definition
> > itself :-)
> >
>
> Thanks a lot! This fixed it.
> I thought I already removed all of them, but one was still left.
>
Does something like this help?
diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
index 23c5948..129b2cf 100644
--- a/arch/sh/kernel/machvec.c
+++ b/arch/sh/kernel/machvec.c
@@ -91,6 +91,13 @@ void __init sh_mv_setup(void)
(unsigned long)&__machvec_start);
/*
+ * Sanity check for machvec section alignment. Ensure
+ * __initmv hasn't been misused.
+ */
+ if (machvec_size % sizeof(struct sh_machine_vector))
+ panic("machvec misaligned, invalid __initmv use?");
+
+ /*
* If the machvec hasn't been preselected, use the first
* vector (usually the only one) from .machvec.init.
*/
|
|
From: EXTERNAL B. M. (P. ST-FIR/Eng) <ext...@de...> - 2007-08-07 09:10:03
|
Paul Mundt wrote: > On Tue, Aug 07, 2007 at 10:37:10AM +0200, EXTERNAL Brunner Markus > (Praktikant; ST-FIR/Eng) wrote:=20 >> markus@linux-markus:~/kernels$ sh3-unknown-linux-gnu-nm vmlinux | >> grep mpr2 8c2c18c0 t __initcall_mpr2_devices_setup6 >> 8c2c1b00 T init_mpr2_IRQ >> 8c2c03d4 t mpr2_devices >> 8c2b1870 t mpr2_devices_setup >> 8c2b16d0 t mpr2_setup >> 8c2c1a70 t mv_mpr2 >>=20 >> This is with earlyprintk enabled. Now size and addresses have >> changed and mv_mpr2 isn't at the beginning of the machvec anymore.=20 >>=20 > This is rather interesting. Looking at your board patch again, it > seems=20 > like this might be caused by the __initmv sprinkling you have on other > functions. __initmv is intended _only_ for the machvec description > itself, init functions referenced from within it should be flagged as > __init. We only ever expect to find full machvec structs within the > machvec section, so this is likely what is screwing it up. Please try > again with __initmv removed from everything but the machvec definition > itself :-) >=20 Thanks a lot! This fixed it.=20 I thought I already removed all of them, but one was still left. Regards Markus |
|
From: Paul M. <le...@li...> - 2007-08-07 08:49:37
|
On Tue, Aug 07, 2007 at 10:37:10AM +0200, EXTERNAL Brunner Markus (Praktikant; ST-FIR/Eng) wrote: > markus@linux-markus:~/kernels$ sh3-unknown-linux-gnu-nm vmlinux | grep mpr2 > 8c2c18c0 t __initcall_mpr2_devices_setup6 > 8c2c1b00 T init_mpr2_IRQ > 8c2c03d4 t mpr2_devices > 8c2b1870 t mpr2_devices_setup > 8c2b16d0 t mpr2_setup > 8c2c1a70 t mv_mpr2 > > This is with earlyprintk enabled. Now size and addresses have changed and mv_mpr2 isn't at the beginning of the machvec anymore. > This is rather interesting. Looking at your board patch again, it seems like this might be caused by the __initmv sprinkling you have on other functions. __initmv is intended _only_ for the machvec description itself, init functions referenced from within it should be flagged as __init. We only ever expect to find full machvec structs within the machvec section, so this is likely what is screwing it up. Please try again with __initmv removed from everything but the machvec definition itself :-) |
|
From: EXTERNAL B. M. (P. ST-FIR/Eng) <ext...@de...> - 2007-08-07 08:37:22
|
... > Also, if you give it a sh_mv=3Dfoo, do you get the proper list?=20 No.=20 >> When I tried to specify any other string (including the correct = mv_name) to sh_mv=3D booting stopped after=20 >> [ =A0 =A00.000000] console [sercon0] enabled > Beyond that, what boot loader are you using?=20 I don't have a real bootloader on the board. I load zImage at address = 0x8c210000 with a JTAG debugger.=20 > You might also try bumping the load address up higher in case=20 > the boot loader happens to be stepping on something. Afaik no other address will work. > Have you tried this with sh-bios support enabled and disabled in the = kernel?=20 > Are the results the same for both?=20 I don't have a BIOS on the board. Enabling the sh-bios in the kernel = will break the kernel. =20 > If that doesn't reveal any clues, can you build with debugging symbols > and post your kernel image somewhere so I can disassemble it? Not possible at the moment, but i will do that in about 7 hours. > That's a bit unusual. Can you print out what the size of the machvec > section is (ie, &__machvec_end - &__machvec_start)?=20 Yes, and in combination with nm this gives some interesting results: This is without earlyprintk. Note that mv_mpr2 has the same address as = __machvec_start [ 0.000000] Linux version 2.6.23-rc2 (markus@linux-markus) (gcc = version 3.4.6) #38 Tue Aug 7 09:25:06 CEST 2007 [ 0.000000] machvec start: 0x8c2c1a70 machvec end 0x8c2c1b20 size: = 0x2c [ 0.000000] Booting machvec: mpr2 [ 0.000000] Magic Panel Release 2 A.2 markus@linux-markus:~/kernels$ sh3-unknown-linux-gnu-nm vmlinux | grep = mpr2 8c2c18c0 t __initcall_mpr2_devices_setup6 8c2c1b00 T init_mpr2_IRQ 8c2c03d4 t mpr2_devices 8c2b1870 t mpr2_devices_setup 8c2b16d0 t mpr2_setup 8c2c1a70 t mv_mpr2 This is with earlyprintk enabled. Now size and addresses have changed = and mv_mpr2 isn't at the beginning of the machvec anymore. [ 0.000000] Linux version 2.6.23-rc2 (markus@linux-markus) (gcc = version 3.4.6) #36 Tue Aug 7 09:19:31 CEST 2007 [ 0.000000] console [sercon0] enabled [ 0.000000] machvec start: 0x8c2c1bfc machvec end 0x8c2c1cb0 size: = 0x2d [ 0.000000] Booting machvec: ./ [ 0.000000] Node 0: start_pfn =3D 0xc000, low =3D 0xff00 markus@linux-markus:~/kernels$ sh3-unknown-linux-gnu-nm vmlinux | grep = mpr2 8c2c1a4c t __initcall_mpr2_devices_setup6 8c2c1c90 T init_mpr2_IRQ 8c2c0554 t mpr2_devices 8c2b19e0 t mpr2_devices_setup 8c2b1840 t mpr2_setup 8c2c1c00 t mv_mpr2 Regards Markus |
|
From: Paul M. <le...@li...> - 2007-08-07 03:22:39
|
On Mon, Aug 06, 2007 at 10:50:53PM +0200, Markus Brunner wrote: > [ ? ?0.000000] Linux version 2.6.23-rc1 (markus@linux-markus) (gcc version 3.4.6) #8 Mon Aug 6 13:17:37 CEST 2007 > [ ? ?0.000000] console [sercon0] enabled > [ ? ?0.000000] Booting machvec: ./ > > Boot seemed to be quite normal, but LEDs and ethernet obviously didn't work. > > When I added sh_mv=generic to the command line, the only noticeable difference was the line > [ ? ?0.000000] Booting machvec: generic > > When I tried to specify any other string (including the correct mv_name) to sh_mv= booting stopped after > [ ? ?0.000000] console [sercon0] enabled > > I added some debug outputs to get_mv_byname in machvec.c to see what > strings get compared, but only > [ ? ?0.000000] ./ > [ ? ?0.000000] <NULL> > Seem to be there > That's a bit unusual. Can you print out what the size of the machvec section is (ie, &__machvec_end - &__machvec_start)? Also, if you give it a sh_mv=foo, do you get the proper list? Beyond that, what boot loader are you using? Have you tried this with sh-bios support enabled and disabled in the kernel? Are the results the same for both? You might also try bumping the load address up higher in case the boot loader happens to be stepping on something. If that doesn't reveal any clues, can you build with debugging symbols and post your kernel image somewhere so I can disassemble it? |
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