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From: Andy P. <at...@us...> - 2002-04-09 12:33:27
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/gcc In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-mips/gcc Added Files: sgidefs.h Log Message: Synch to 2.4.15 commit 1 --- NEW FILE --- /* * include/sgidefs.h * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1996 by Ralf Baechle * * This file is here to satisfy GCC's expectations. */ #ifndef __SGIDEFS_H #define __SGIDEFS_H #include <asm/sgidefs.h> #endif /* __SGIDEFS_H */ |
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:26
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/ddb5xxx
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-mips/ddb5xxx
Added Files:
ddb5477.h ddb5xxx.h debug.h pci.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/***********************************************************************
*
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*
* include/asm-mips/ddb5xxx/ddb5477.h
* DDB 5477 specific definitions and macros.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
***********************************************************************
*/
#ifndef __ASM_DDB5XXX_DDB5477_H
#define __ASM_DDB5XXX_DDB5477_H
#include <linux/config.h>
#include <asm/ddb5xxx/ddb5xxx.h>
/*
* This contains macros that are specific to DDB5477 or renamed from
* DDB5476.
*/
/*
* renamed PADRs
*/
#define DDB_LCS0 DDB_LDCS0
#define DDB_LCS1 DDB_LDCS1
#define DDB_LCS2 DDB_LDCS2
#define DDB_VRC5477 DDB_INTCS
/*
* New CPU interface registers
*/
#define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */
#define DDB_INTCTRL1 0x0404 /* Interrupt Control 1 */
#define DDB_INTCTRL2 0x0408 /* Interrupt Control 2 */
#define DDB_INTCTRL3 0x040c /* Interrupt Control 3 */
#define DDB_INT0STAT 0x0420 /* INT0 Status [R] */
#define DDB_INT1STAT 0x0428 /* INT1 Status [R] */
#define DDB_INT2STAT 0x0430 /* INT2 Status [R] */
#define DDB_INT3STAT 0x0438 /* INT3 Status [R] */
#define DDB_INT4STAT 0x0440 /* INT4 Status [R] */
#define DDB_NMISTAT 0x0450 /* NMI Status [R] */
#define DDB_INTCLR32 0x0468 /* Interrupt Clear */
#define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */
#define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */
#undef DDB_CPUSTAT /* duplicate in Vrc-5477 */
#define DDB_CPUSTAT 0x0480 /* CPU Status [R] */
#define DDB_BUSCTRL 0x0488 /* Internal Bus Control */
/*
* Timer registers
*/
#define DDB_REFCTRL_L DDB_T0CTRL
#define DDB_REFCTRL_H (DDB_T0CTRL+4)
#define DDB_REFCNTR DDB_T0CNTR
#define DDB_SPT0CTRL_L DDB_T1CTRL
#define DDB_SPT0CTRL_H (DDB_T1CTRL+4)
#define DDB_SPT1CTRL_L DDB_T2CTRL
#define DDB_SPT1CTRL_H (DDB_T2CTRL+4)
#define DDB_SPT1CNTR DDB_T1CTRL
#define DDB_WDTCTRL_L DDB_T3CTRL
#define DDB_WDTCTRL_H (DDB_T3CTRL+4)
#define DDB_WDTCNTR DDB_T3CNTR
/*
* DMA registers are moved. We don't care about it for now. TODO.
*/
/*
* BARs for ext PCI (PCI0)
*/
#undef DDB_BARC
#undef DDB_BARB
#define DDB_BARC0 0x0210 /* PCI0 Control */
#define DDB_BARM010 0x0218 /* PCI0 SDRAM bank01 */
#define DDB_BARM230 0x0220 /* PCI0 SDRAM bank23 */
#define DDB_BAR00 0x0240 /* PCI0 LDCS0 */
#define DDB_BAR10 0x0248 /* PCI0 LDCS1 */
#define DDB_BAR20 0x0250 /* PCI0 LDCS2 */
#define DDB_BAR30 0x0258 /* PCI0 LDCS3 */
#define DDB_BAR40 0x0260 /* PCI0 LDCS4 */
#define DDB_BAR50 0x0268 /* PCI0 LDCS5 */
#define DDB_BARB0 0x0280 /* PCI0 BOOT */
#define DDB_BARP00 0x0290 /* PCI0 for IOPCI Window0 */
#define DDB_BARP10 0x0298 /* PCI0 for IOPCI Window1 */
/*
* BARs for IOPIC (PCI1)
*/
#define DDB_BARC1 0x0610 /* PCI1 Control */
#define DDB_BARM011 0x0618 /* PCI1 SDRAM bank01 */
#define DDB_BARM231 0x0620 /* PCI1 SDRAM bank23 */
#define DDB_BAR01 0x0640 /* PCI1 LDCS0 */
#define DDB_BAR11 0x0648 /* PCI1 LDCS1 */
#define DDB_BAR21 0x0650 /* PCI1 LDCS2 */
#define DDB_BAR31 0x0658 /* PCI1 LDCS3 */
#define DDB_BAR41 0x0660 /* PCI1 LDCS4 */
#define DDB_BAR51 0x0668 /* PCI1 LDCS5 */
#define DDB_BARB1 0x0680 /* PCI1 BOOT */
#define DDB_BARP01 0x0690 /* PCI1 for ext PCI Window0 */
#define DDB_BARP11 0x0698 /* PCI1 for ext PCI Window1 */
/*
* Other registers for ext PCI (PCI0)
*/
#define DDB_PCIINIT00 0x02f0 /* PCI0 Initiator 0 */
#define DDB_PCIINIT10 0x02f8 /* PCI0 Initiator 1 */
#define DDB_PCISWP0 0x02b0 /* PCI0 Swap */
#define DDB_PCIERR0 0x02b8 /* PCI0 Error */
#define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */
#define DDB_PCICTL0_H 0x02e4 /* PCI0 Control-H */
#define DDB_PCIARB0_L 0x02e8 /* PCI0 Arbitration-L */
#define DDB_PCIARB0_H 0x02ec /* PCI0 Arbitration-H */
/*
* Other registers for IOPCI (PCI1)
*/
#define DDB_IOPCIW0 0x00d0 /* PCI Address Window 0 [R/W] */
#define DDB_IOPCIW1 0x00d8 /* PCI Address Window 1 [R/W] */
#define DDB_PCIINIT01 0x06f0 /* PCI1 Initiator 0 */
#define DDB_PCIINIT11 0x06f8 /* PCI1 Initiator 1 */
#define DDB_PCISWP1 0x06b0 /* PCI1 Swap */
#define DDB_PCIERR1 0x06b8 /* PCI1 Error */
#define DDB_PCICTL1_L 0x06e0 /* PCI1 Control-L */
#define DDB_PCICTL1_H 0x06e4 /* PCI1 Control-H */
#define DDB_PCIARB1_L 0x06e8 /* PCI1 Arbitration-L */
#define DDB_PCIARB1_H 0x06ec /* PCI1 Arbitration-H */
/*
* Local Bus
*/
#define DDB_LCST0 0x0110 /* LB Chip Select Timing 0 */
#define DDB_LCST1 0x0118 /* LB Chip Select Timing 1 */
#undef DDB_LCST2
#define DDB_LCST2 0x0120 /* LB Chip Select Timing 2 */
#undef DDB_LCST3
#undef DDB_LCST4
#undef DDB_LCST5
#undef DDB_LCST6
#undef DDB_LCST7
#undef DDB_LCST8
#define DDB_ERRADR 0x0150 /* Error Address Register */
#define DDB_ERRCS 0x0160
#define DDB_BTM 0x0170 /* Boot Time Mode value */
/*
* MISC registers
*/
#define DDB_GIUFUNSEL 0x4040 /* select dual-func pins */
#define DDB_PIBMISC 0x0750 /* USB buffer enable / power saving */
/*
* Memory map (physical address)
*
* Note most of the following address must be properly aligned by the
* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
* PCI_IO_BASE must be aligned along 16MB boundary.
*/
#define DDB_SDRAM_BASE 0x00000000
#define DDB_SDRAM_SIZE 0x08000000 /* 128MB, for sure? */
#define DDB_PCI0_MEM_BASE 0x08000000
#define DDB_PCI0_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_PCI1_MEM_BASE 0x10000000
#define DDB_PCI1_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_PCI0_CONFIG_BASE 0x18000000
#define DDB_PCI0_CONFIG_SIZE 0x01000000 /* 16 MB */
#define DDB_PCI1_CONFIG_BASE 0x19000000
#define DDB_PCI1_CONFIG_SIZE 0x01000000 /* 16 MB */
#define DDB_PCI_IO_BASE 0x1a000000 /* we concatenate two IOs */
#define DDB_PCI0_IO_BASE 0x1a000000
#define DDB_PCI0_IO_SIZE 0x01000000 /* 16 MB */
#define DDB_PCI1_IO_BASE 0x1b000000
#define DDB_PCI1_IO_SIZE 0x01000000 /* 16 MB */
#define DDB_LCS0_BASE 0x1c000000 /* flash memory */
#define DDB_LCS0_SIZE 0x01000000 /* 16 MB */
#define DDB_LCS1_BASE 0x1d000000 /* misc */
#define DDB_LCS1_SIZE 0x01000000 /* 16 MB */
#define DDB_LCS2_BASE 0x1e000000 /* Mezzanine */
#define DDB_LCS2_SIZE 0x01000000 /* 16 MB */
#define DDB_VRC5477_BASE 0x1fa00000 /* VRC5477 control regs */
#define DDB_VRC5477_SIZE 0x00200000 /* 2MB */
#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
#define DDB_LED DDB_LCS1_BASE + 0x10000
/*
* DDB5477 specific functions
*/
extern void ddb5477_irq_setup(void);
/* route irq to cpu int pin */
extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip);
/* low-level routine for enabling vrc5477 irq, bypassing high-level */
extern void ll_vrc5477_irq_enable(int vrc5477_irq);
extern void ll_vrc5477_irq_disable(int vrc5477_irq);
/*
* debug routines
*/
#if defined(CONFIG_LL_DEBUG)
extern void vrc5477_show_pdar_regs(void);
extern void vrc5477_show_pci_regs(void);
extern void vrc5477_show_bar_regs(void);
extern void vrc5477_show_int_regs(void);
extern void vrc5477_show_all_regs(void);
#endif
#endif /* __ASM_DDB5XXX_DDB5477_H */
--- NEW FILE ---
/***********************************************************************
*
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*
* Copyright (C) 2000 Geert Uytterhoeven <ge...@so...>
* Sony Software Development Center Europe (SDCE), Brussels
*
* include/asm-mips/ddb5xxx/ddb5xxx.h
* Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
***********************************************************************
*/
#ifndef __ASM_DDB5XXX_DDB5XXX_H
#define __ASM_DDB5XXX_DDB5XXX_H
#include <linux/config.h>
#include <linux/types.h>
#include <asm/ddb5xxx/debug.h>
/*
* This file is based on the following documentation:
*
* NEC Vrc 5074 System Controller Data Sheet, June 1998
*
* [jsun] It is modified so that this file only contains the macros
* that are true for all DDB 5xxx boards. The modification is based on
*
* uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke)
* Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000
*
*/
#define DDB_BASE 0xbfa00000
#define DDB_SIZE 0x00200000 /* 2 MB */
/*
* Physical Device Address Registers (PDARs)
*/
#define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
#define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
#define DDB_LDCS0 0x0010 /* Device Chip-Select 0 [R/W] */
#define DDB_LDCS1 0x0018 /* Device Chip-Select 1 [R/W] */
#define DDB_LDCS2 0x0020 /* Device Chip-Select 2 [R/W] */
#define DDB_LDCS3 0x0028 /* Device Chip-Select 3 [R/W] */
#define DDB_LDCS4 0x0030 /* Device Chip-Select 4 [R/W] */
#define DDB_LDCS5 0x0038 /* Device Chip-Select 5 [R/W] */
#define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
#define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
#define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */
/* [R/W] */
#define DDB_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */
/* Vrc5477 has two more, IOPCIW0, IOPCIW1 */
/*
* CPU Interface Registers
*/
#define DDB_CPUSTAT 0x0080 /* CPU Status [R/W] */
#define DDB_INTCTRL 0x0088 /* Interrupt Control [R/W] */
#define DDB_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */
#define DDB_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */
/* Enable [R/W] */
#define DDB_INTCLR 0x00A0 /* Interrupt Clear [R/W] */
#define DDB_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
/*
* Memory-Interface Registers
*/
#define DDB_MEMCTRL 0x00C0 /* Memory Control */
#define DDB_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
#define DDB_CHKERR 0x00D0 /* Memory Check Error Status [R] */
/*
* PCI-Bus Registers
*/
#define DDB_PCICTRL 0x00E0 /* PCI Control [R/W] */
#define DDB_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
#define DDB_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
#define DDB_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
#define DDB_PCIERR 0x00B8 /* PCI Error [R/W] */
/*
* Local-Bus Registers
*/
#define DDB_LCNFG 0x0100 /* Local Bus Configuration [R/W] */
#define DDB_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */
#define DDB_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */
#define DDB_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */
#define DDB_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */
#define DDB_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */
#define DDB_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */
#define DDB_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */
#define DDB_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */
/* Enables [R/W] */
#define DDB_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */
#define DDB_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */
/*
* DMA Registers
*/
#define DDB_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */
#define DDB_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */
#define DDB_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */
#define DDB_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */
#define DDB_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */
#define DDB_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */
/*
* Timer Registers
*/
#define DDB_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */
#define DDB_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */
#define DDB_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */
#define DDB_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */
#define DDB_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */
#define DDB_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */
#define DDB_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */
#define DDB_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */
/*
* PCI Configuration Space Registers
*/
#define DDB_PCI_BASE 0x0200
#define DDB_VID 0x0200 /* PCI Vendor ID [R] */
#define DDB_DID 0x0202 /* PCI Device ID [R] */
#define DDB_PCICMD 0x0204 /* PCI Command [R/W] */
#define DDB_PCISTS 0x0206 /* PCI Status [R/W] */
#define DDB_REVID 0x0208 /* PCI Revision ID [R] */
#define DDB_CLASS 0x0209 /* PCI Class Code [R] */
#define DDB_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
#define DDB_MLTIM 0x020D /* PCI Latency Timer [R/W] */
#define DDB_HTYPE 0x020E /* PCI Header Type [R] */
#define DDB_BIST 0x020F /* BIST [R] (unimplemented) */
#define DDB_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
#define DDB_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
#define DDB_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
#define DDB_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
/* (unimplemented) */
#define DDB_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
#define DDB_SSID 0x022E /* PCI Sub-System ID [R/W] */
#define DDB_ROM 0x0230 /* Expansion ROM Base Address [R] */
/* (unimplemented) */
#define DDB_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
#define DDB_INTPIN 0x023D /* PCI Interrupt Pin [R] */
#define DDB_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
#define DDB_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
#define DDB_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
#define DDB_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
#define DDB_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
#define DDB_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
#define DDB_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
#define DDB_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
#define DDB_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
#define DDB_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
/*
* Nile 4 Register Access
*/
static inline void ddb_sync(void)
{
volatile u32 *p = (volatile u32 *)0xbfc00000;
(void)(*p);
}
static inline void ddb_out32(u32 offset, u32 val)
{
*(volatile u32 *)(DDB_BASE+offset) = val;
ddb_sync();
}
static inline u32 ddb_in32(u32 offset)
{
u32 val = *(volatile u32 *)(DDB_BASE+offset);
ddb_sync();
return val;
}
static inline void ddb_out16(u32 offset, u16 val)
{
*(volatile u16 *)(DDB_BASE+offset) = val;
ddb_sync();
}
static inline u16 ddb_in16(u32 offset)
{
u16 val = *(volatile u16 *)(DDB_BASE+offset);
ddb_sync();
return val;
}
static inline void ddb_out8(u32 offset, u8 val)
{
*(volatile u8 *)(DDB_BASE+offset) = val;
ddb_sync();
}
static inline u8 ddb_in8(u32 offset)
{
u8 val = *(volatile u8 *)(DDB_BASE+offset);
ddb_sync();
return val;
}
/*
* Physical Device Address Registers
*/
extern u32
ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible);
extern void
ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
int on_memory_bus, int pci_visible);
/*
* PCI Master Registers
*/
#define DDB_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
#define DDB_PCICMD_IO 1 /* PCI I/O Space */
#define DDB_PCICMD_MEM 3 /* PCI Memory Space */
#define DDB_PCICMD_CFG 5 /* PCI Configuration Space */
/*
* additional options for pci init reg (no shifting needed)
*/
#define DDB_PCI_CFGTYPE1 0x200 /* for pci init0/1 regs */
#define DDB_PCI_ACCESS_32 0x10 /* for pci init0/1 regs */
extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options);
/*
* we need to reset pci bus when we start up and shutdown
*/
extern void ddb_pci_reset_bus(void);
/*
* include the board dependent part
*/
#if defined(CONFIG_DDB5074)
#include <asm/ddb5xxx/ddb5074.h>
#elif defined(CONFIG_DDB5476)
#include <asm/ddb5xxx/ddb5476.h>
#elif defined(CONFIG_DDB5477)
#include <asm/ddb5xxx/ddb5477.h>
#else
#error "Unknown DDB board!"
#endif
#endif /* __ASM_DDB5XXX_DDB5XXX_H */
--- NEW FILE ---
/***********************************************************************
*
* Copyright 2001 MontaVista Software Inc.
* Author: js...@mv... or js...@ju...
*
* include/asm-mips/ddb5xxx/debug.h
* Some debug macros used by ddb code.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
***********************************************************************
*/
#ifndef __ASM_DDB5XXX_DEBUG_H
#define __ASM_DDB5XXX_DEBUG_H
#include <linux/config.h>
/*
* macro for catching spurious errors. Eable to LL_DEBUG in kernel hacking
* config menu.
*/
#ifdef CONFIG_LL_DEBUG
#include <linux/kernel.h>
#define MIPS_ASSERT(x) if (!(x)) { panic("MIPS_ASSERT failed at %s:%d\n", __FILE__, __LINE__); }
#define MIPS_VERIFY(x, y) MIPS_ASSERT(x y)
#define MIPS_DEBUG(x) do { x; } while (0)
#else
#define MIPS_ASSERT(x)
#define MIPS_VERIFY(x, y) x
#define MIPS_DEBUG(x)
#endif
#endif /* __ASM_DDB5XXX_DEBUG_H */
--- NEW FILE ---
#ifndef __ASM_DDB5XXXX_PCI_H
#define __ASM_DDB5XXXX_PCI_H
/*
* This file essentially defines the interface between board
* specific PCI code and MIPS common PCI code. Should potentially put
* into include/asm/pci.h file.
*/
#include <linux/ioport.h>
#include <linux/pci.h>
/*
* Each pci channel is a top-level PCI bus seem by CPU. A machine with
* multiple PCI channels may have multiple PCI host controllers or a
* single controller supporting multiple channels.
*/
struct pci_channel {
struct pci_ops *pci_ops;
struct resource *io_resource;
struct resource *mem_resource;
};
/*
* each board defines an array of pci_channels, that ends with all NULL entry
*/
extern struct pci_channel mips_pci_channels[];
/*
* board supplied pci irq fixup routine
*/
extern void pcibios_fixup_irqs(void);
#endif /* __ASM_DDB5XXXX_PCI_H */
|
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From: Andy P. <at...@us...> - 2002-04-09 12:33:21
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-generic
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-generic
Added Files:
tlb.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/* asm-generic/tlb.h
*
* Generic TLB shootdown code
*
* Copyright 2001 Red Hat, Inc.
* Based on code from mm/memory.c Copyright Linus Torvalds and others.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef _ASM_GENERIC__TLB_H
#define _ASM_GENERIC__TLB_H
#include <linux/config.h>
#ifdef CONFIG_SMP
/* aim for something that fits in the L1 cache */
#define FREE_PTE_NR 508
/* mmu_gather_t is an opaque type used by the mm code for passing around any
* data needed by arch specific code for tlb_remove_page. This structure can
* be per-CPU or per-MM as the page table lock is held for the duration of TLB
* shootdown.
*/
typedef struct free_pte_ctx {
struct mm_struct *mm;
unsigned long nr; /* set to ~0UL means fast mode */
unsigned long start_addr, end_addr;
pte_t ptes[FREE_PTE_NR];
} mmu_gather_t;
/* Users of the generic TLB shootdown code must declare this storage space. */
extern mmu_gather_t mmu_gathers[NR_CPUS];
/* tlb_gather_mmu
* Return a pointer to an initialized mmu_gather_t.
*/
static inline mmu_gather_t *tlb_gather_mmu(struct mm_struct *mm)
{
mmu_gather_t *tlb = &mmu_gathers[smp_processor_id()];
tlb->mm = mm;
/* Use fast mode if there is only one user of this mm (this process) */
tlb->nr = (atomic_read(&(mm)->mm_users) == 1) ? ~0UL : 0UL;
return tlb;
}
/* void tlb_remove_page(mmu_gather_t *tlb, pte_t *ptep, unsigned long addr)
* Must perform the equivalent to __free_pte(pte_get_and_clear(ptep)), while
* handling the additional races in SMP caused by other CPUs caching valid
* mappings in their TLBs.
*/
#define tlb_remove_page(ctxp, pte, addr) do {\
/* Handle the common case fast, first. */\
if ((ctxp)->nr == ~0UL) {\
__free_pte(*(pte));\
pte_clear((pte));\
break;\
}\
if (!(ctxp)->nr) \
(ctxp)->start_addr = (addr);\
(ctxp)->ptes[(ctxp)->nr++] = ptep_get_and_clear(pte);\
(ctxp)->end_addr = (addr) + PAGE_SIZE;\
if ((ctxp)->nr >= FREE_PTE_NR)\
tlb_finish_mmu((ctxp), 0, 0);\
} while (0)
/* tlb_finish_mmu
* Called at the end of the shootdown operation to free up any resources
* that were required. The page talbe lock is still held at this point.
*/
static inline void tlb_finish_mmu(struct free_pte_ctx *ctx, unsigned long start, unsigned long end)
{
unsigned long i, nr;
/* Handle the fast case first. */
if (ctx->nr == ~0UL) {
flush_tlb_range(ctx->mm, start, end);
return;
}
nr = ctx->nr;
ctx->nr = 0;
if (nr)
flush_tlb_range(ctx->mm, ctx->start_addr, ctx->end_addr);
for (i=0; i < nr; i++) {
pte_t pte = ctx->ptes[i];
__free_pte(pte);
}
}
#else
/* The uniprocessor functions are quite simple and are inline macros in an
* attempt to get gcc to generate optimal code since this code is run on each
* page in a process at exit.
*/
typedef struct mm_struct mmu_gather_t;
#define tlb_gather_mmu(mm) (mm)
#define tlb_finish_mmu(tlb, start, end) flush_tlb_range(tlb, start, end)
#define tlb_remove_page(tlb, ptep, addr) do {\
pte_t __pte = *(ptep);\
pte_clear(ptep);\
__free_pte(__pte);\
} while (0)
#endif
#endif /* _ASM_GENERIC__TLB_H */
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:18
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-anakin
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/arch-anakin
Added Files:
dma.h hardware.h ide.h io.h irq.h irqs.h keyboard.h memory.h
param.h serial.h serial_reg.h system.h time.h timex.h
uncompress.h vmalloc.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/dma.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 09-Apr-2001 W/TTC Created
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#define MAX_DMA_ADDRESS 0xffffffff
#define MAX_DMA_CHANNELS 0
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/hardware.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 10-Apr-2001 TTC Created
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/*
* Memory map
*/
#define SRAM_START 0x00000000
#define SRAM_SIZE 0x00100000
#define SRAM_BASE 0xdf000000
#define SDRAM_START 0x20000000
#define SDRAM_SIZE 0x04000000
#define SDRAM_BASE 0xc0000000
#define IO_START 0x40000000
#define IO_SIZE 0x00100000
#define IO_BASE 0xe0000000
#define FLASH_START 0x60000000
#define FLASH_SIZE 0x00080000
#define FLASH_BASE 0xe8000000
#define VGA_START 0x80000000
#define VGA_SIZE 0x0002db40
#define VGA_BASE 0xf0000000
/*
* IO map
*/
#define IO_CONTROLLER 0x00000
#define INTERRUPT_CONTROLLER 0x02000
#define UART0 0x04000
#define UART1 0x06000
#define UART2 0x08000
#define CODEC 0x0a000
#define UART4 0x0c000
#define UART3 0x0e000
#define DISPLAY_CONTROLLER 0x10000
#define DAB 0x12000
#define STATE_CONTROLLER 0x14000
#define CAN 0x23000
#define COMPACTFLASH 0x24000
/*
* Use SRAM for D-cache flush
*/
#define FLUSH_BASE_PHYS SRAM_START
#define FLUSH_BASE SRAM_BASE
#define UNCACHEABLE_ADDR (SRAM_BASE + 0x10000)
/*
* Use SDRAM for memory
*/
#define MEM_SIZE SDRAM_SIZE
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/ide.h
*
* Copyright 2001 Blue Mug Inc. for Acunia N.V.
*
* 08-jun-2001: Initial clone of arch-sa1100/ide.h by Jon McClintock
* (jo...@bl...).
*/
#include <linux/config.h>
#include <asm/irq.h>
#include <asm/hardware.h>
/*
* Set up a hw structure for a specified data port, control port and IRQ.
* This should follow whatever the default interface uses.
*/
static __inline__ void
ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq)
{
ide_ioreg_t reg;
int i;
int regincr = 4;
memset(hw, 0, sizeof(*hw));
reg = (ide_ioreg_t)data_port;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg;
reg += regincr;
}
hw->io_ports[IDE_CONTROL_OFFSET] = (ide_ioreg_t) ctrl_port;
if (irq)
*irq = 0;
}
/*
* This registers the standard ports for this architecture with the IDE
* driver.
*/
static __inline__ void
ide_init_default_hwifs(void)
{
hw_regs_t hw;
ide_init_hwif_ports(&hw, IO_BASE + COMPACTFLASH,
IO_BASE + COMPACTFLASH + IDE_CONTROL_OFFSET, NULL);
hw.irq = IRQ_COMPACTFLASH;
ide_register_hw(&hw, NULL);
}
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/io.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 10-Apr-2001 TTC Created
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) a
#define __arch_getw(a) (*(volatile unsigned short *) (a))
#define __arch_putw(b, a) (*(volatile unsigned short *) (a) = (b))
#define iomem_valid_addr(i, s) 1
#define iomem_to_phys(i) i
/*
* We don't support ins[lb]/outs[lb]. Make them fault.
*/
#define __raw_readsb(p,d,l) do { *(int *)0 = 0; } while (0)
#define __raw_readsl(p,d,l) do { *(int *)0 = 0; } while (0)
#define __raw_writesb(p,d,l) do { *(int *)0 = 0; } while (0)
#define __raw_writesl(p,d,l) do { *(int *)0 = 0; } while (0)
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/irq.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 10-Apr-2001 TTC Created
*/
#ifndef __ASM_ARCH_IRQ_H
#define __ASM_ARCH_IRQ_H
#define fixup_irq(i) i
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/irqs.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 10-Apr-2001 TTC Created
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#define NR_IRQS 16
#define IRQ_UART0 0
#define IRQ_UART1 1
#define IRQ_UART2 2
#define IRQ_TICK 3
#define IRQ_CODEC 4
#define IRQ_UART4 5
#define IRQ_TOUCHSCREEN 6
#define IRQ_UART3 7
#define IRQ_FIFO 8
#define IRQ_CAN 9
#define IRQ_COMPACTFLASH 10
#define IRQ_BOSH 12
#define IRQ_ANAKIN 15
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/keyboard.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 11-Apr-2001 TTC Created
*/
#define kbd_init_hw() do { } while (0)
#define kbd_enable_irq() do { } while (0)
#define kbd_disable_irq() do { } while (0)
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/memory.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 09-Apr-2001 TTC Created
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define TASK_SIZE (3u * 1024 * 1024 * 1024)
#define TASK_SIZE_26 (64u * 1024 * 1024)
#define TASK_UNMAPPED_BASE (1u * 1024 * 1024 * 1024)
#define PAGE_OFFSET 0xc0000000
#define PHYS_OFFSET 0x20000000
#define __virt_to_phys(a) ((a) - PAGE_OFFSET + PHYS_OFFSET)
#define __phys_to_virt(a) ((a) + PAGE_OFFSET - PHYS_OFFSET)
#define __virt_to_bus(a) __virt_to_phys(a)
#define __bus_to_virt(a) __phys_to_virt(a)
#define __virt_to_phys__is_a_macro
#define __phys_to_virt__is_a_macro
#define __virt_to_bus__is_a_macro
#define __bus_to_virt__is_a_macro
#define PHYS_TO_NID(addr) (0)
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/param.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 11-Apr-2001 TTC Created
*/
#ifndef __ASM_ARCH_PARAM_H
#define __ASM_ARCH_PARAM_H
/*
* Reserved for future use
*/
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/serial.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 11-Apr-2001 TTC Created
*/
#ifndef __ASM_ARCH_SERIAL_H
#define __ASM_ARCH_SERIAL_H
#include <asm/io.h>
#include <asm/irq.h>
/*
* UART3 and UART4 are not supported yet
*/
#define RS_TABLE_SIZE 3
#define STD_SERIAL_PORT_DEFNS \
{ 0, 0, IO_BASE + UART0, IRQ_UART0, 0 }, \
{ 0, 0, IO_BASE + UART1, IRQ_UART1, 0 }, \
{ 0, 0, IO_BASE + UART2, IRQ_UART2, 0 }
#define EXTRA_SERIAL_PORT_DEFNS
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/serial_reg.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 09-Apr-2001 TTC Created
*/
#ifndef ASM_ARCH_SERIAL_REG_H
#define ASM_ARCH_SERIAL_REG_H
/*
* Serial registers (other than tx/rx)
*/
/*
* [UARTx + 0x10]
*/
#define RXRELEASE (1 << 0)
#define TXEMPTY (1 << 1)
#define CTS (1 << 2)
#define PRESCALER (31 << 3)
#define SETBAUD(baud) ((230400 / (baud) - 1) << 3)
#define GETBAUD(prescaler) (230400 / (((prescaler) >> 3) + 1))
/*
* [UARTx + 0x18]
*/
#define IRQENABLE (1 << 0)
#define SENDREQUEST (1 << 1)
#define RTS (1 << 2)
#define DTR (1 << 3)
#define DCD (1 << 4)
#define BLOCKRX (1 << 5)
#define PARITY (3 << 6)
#define SETPARITY(parity) ((parity) << 6)
#define GETPARITY(parity) ((parity) >> 6)
#define NONEPARITY (0)
#define ODDPARITY (1)
#define EVENPARITY (2)
/*
* [UARTx + 0x1c]
*/
#define TX (1 << 0)
#define RX (1 << 1)
#define OVERRUN (1 << 2)
/*
* [UARTx + 0x20]
*/
#define SETBREAK (1 << 0)
/*
* Software interrupt register
*/
#define TXENABLE (1 << 0)
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/system.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 11-Apr-2001 TTC Created
* 04-May-2001 W/PB Removed cpu_do_idle()
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
static inline void
arch_idle(void)
{
}
static inline void
arch_reset(char mode)
{
cpu_reset(0);
}
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/time.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 10-Apr-2001 TTC Created
*/
#ifndef __ASM_ARCH_TIME_H
#define __ASM_ARCH_TIME_H
static void
anakin_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
do_timer(regs);
}
static inline void
setup_timer(void)
{
timer_irq.handler = anakin_timer_interrupt;
timer_irq.flags = SA_INTERRUPT;
setup_arm_irq(IRQ_TICK, &timer_irq);
}
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/timex.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 09-Apr-2001 TTC Created
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
/*
* Timex specification for Anakin
*/
#define CLOCK_TICK_RATE (1000 / 8)
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/uncompress.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 10-Apr-2001 TTC Created
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <asm/io.h>
#include <asm/arch/serial_reg.h>
#ifndef CONFIG_ANAKIN_DEFAULT_BAUDRATE
#define CONFIG_ANAKIN_DEFAULT_BAUDRATE 9600
#endif
static inline void
putc(int c)
{
while (!(__raw_readl(IO_START + UART0 + 0x10) & TXEMPTY));
__raw_writel(c, IO_START + UART0 + 0x14);
__raw_writel(__raw_readl(IO_START + UART0 + 0x18)
| SENDREQUEST, IO_START + UART0 + 0x18);
}
static void
puts(const char *s)
{
int c;
while ((c = *s++)) {
putc(c);
if (c == '\n') putc('\r');
}
}
static void
arch_decomp_setup(void)
{
__raw_writel(__raw_readl(IO_START + UART0 + 0x10) & ~PRESCALER
| SETBAUD(CONFIG_ANAKIN_DEFAULT_BAUDRATE),
IO_START + UART0 + 0x10);
__raw_writel(__raw_readl(IO_START + UART0 + 0x18) & ~(IRQENABLE
| RTS | DTR | BLOCKRX | PARITY),
IO_START + UART0 + 0x18);
}
#define arch_decomp_wdog()
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-anakin/vmalloc.h
*
* Copyright (C) 2001 Aleph One Ltd. for Acunia N.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 09-Apr-2001 TTC Created
*/
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
/*
* VMALLOC_ARCH_OFFSET must be set to VMALLOC_OFFSET (check
* linux/arch/arm/kernel/traps.c)
*/
#define VMALLOC_ARCH_OFFSET (8 * 1024 * 1024)
#define VMALLOC_VMADDR(a) ((unsigned int) (a))
#define VMALLOC_START ((VMALLOC_VMADDR(high_memory) + VMALLOC_ARCH_OFFSET) & ~(VMALLOC_ARCH_OFFSET - 1))
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
#endif
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:24:20
|
Update of /cvsroot/linux-vax/kernel-2.4/drivers/scsi/dpt In directory usw-pr-cvs1:/tmp/cvs-serv11836/drivers/scsi/dpt Log Message: Directory /cvsroot/linux-vax/kernel-2.4/drivers/scsi/dpt added to the repository |
|
From: Andy P. <at...@us...> - 2002-04-09 12:22:38
|
Update of /cvsroot/linux-vax/kernel-2.4/drivers/scsi/aic7xxx/aicasm In directory usw-pr-cvs1:/tmp/cvs-serv11348/drivers/scsi/aic7xxx/aicasm Log Message: Directory /cvsroot/linux-vax/kernel-2.4/drivers/scsi/aic7xxx/aicasm added to the repository |
|
From: Andy P. <at...@us...> - 2002-04-09 12:17:30
|
Update of /cvsroot/linux-vax/kernel-2.4/include/video In directory usw-pr-cvs1:/tmp/cvs-serv10167/video Modified Files: fbcon.h macmodes.h newport.h Log Message: sync to 2.4.15 commit 2 Index: fbcon.h =================================================================== RCS file: /cvsroot/linux-vax/kernel-2.4/include/video/fbcon.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- fbcon.h 14 Jan 2001 16:59:07 -0000 1.1.1.1 +++ fbcon.h 9 Apr 2002 12:17:22 -0000 1.2 @@ -206,7 +206,7 @@ #define fb_writel sbus_writel #define fb_memset sbus_memset_io -#elif defined(__i386__) || defined(__alpha__) +#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) #define fb_readb __raw_readb #define fb_readw __raw_readw Index: macmodes.h =================================================================== RCS file: /cvsroot/linux-vax/kernel-2.4/include/video/macmodes.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- macmodes.h 14 Jan 2001 16:59:07 -0000 1.1.1.1 +++ macmodes.h 9 Apr 2002 12:17:22 -0000 1.2 @@ -38,7 +38,9 @@ #define VMODE_1152_870_75 18 /* 1152x870, 75Hz */ #define VMODE_1280_960_75 19 /* 1280x960, 75Hz */ #define VMODE_1280_1024_75 20 /* 1280x1024, 75Hz */ -#define VMODE_MAX 20 +#define VMODE_1152_768_60 21 /* 1152x768, 60Hz Titanium PowerBook */ +#define VMODE_1600_1024_60 22 /* 1600x1024, 60Hz 22" Cinema Display */ +#define VMODE_MAX 22 #define VMODE_CHOOSE 99 #define CMODE_NVRAM -1 Index: newport.h =================================================================== RCS file: /cvsroot/linux-vax/kernel-2.4/include/video/newport.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- newport.h 14 Jan 2001 16:59:11 -0000 1.1.1.1 +++ newport.h 9 Apr 2002 12:17:22 -0000 1.2 @@ -486,7 +486,7 @@ * DCBMODE register defines: */ -/* Widht of the data being transfered for each DCBDATA[01] word */ +/* Width of the data being transferred for each DCBDATA[01] word */ #define DCB_DATAWIDTH_4 0x0 #define DCB_DATAWIDTH_1 0x1 #define DCB_DATAWIDTH_2 0x2 |
|
From: Andy P. <at...@us...> - 2002-04-09 12:17:23
|
Update of /cvsroot/linux-vax/kernel-2.4/drivers/scsi/aic7xxx_old In directory usw-pr-cvs1:/tmp/cvs-serv10220/drivers/scsi/aic7xxx_old Log Message: Directory /cvsroot/linux-vax/kernel-2.4/drivers/scsi/aic7xxx_old added to the repository |
|
From: Andy P. <at...@us...> - 2002-04-09 11:41:43
|
Update of /cvsroot/linux-vax/kernel-2.4/drivers/char/mwave In directory usw-pr-cvs1:/tmp/cvs-serv683/drivers/char/mwave Log Message: Directory /cvsroot/linux-vax/kernel-2.4/drivers/char/mwave added to the repository |
|
From: Andy P. <at...@us...> - 2002-04-09 11:41:38
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/gt64120/momenco_ocelot In directory usw-pr-cvs1:/tmp/cvs-serv657/include/asm-mips/gt64120/momenco_ocelot Log Message: Directory /cvsroot/linux-vax/kernel-2.4/include/asm-mips/gt64120/momenco_ocelot added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:39:30
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Update of /cvsroot/linux-vax/kernel-2.4/drivers/net/wireless In directory usw-pr-cvs1:/tmp/cvs-serv32559/drivers/net/wireless Log Message: Directory /cvsroot/linux-vax/kernel-2.4/drivers/net/wireless added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:35:08
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Update of /cvsroot/linux-vax/kernel-2.4/net/8021q In directory usw-pr-cvs1:/tmp/cvs-serv31433/net/8021q Log Message: Directory /cvsroot/linux-vax/kernel-2.4/net/8021q added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:35:00
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Update of /cvsroot/linux-vax/kernel-2.4/net/bluetooth In directory usw-pr-cvs1:/tmp/cvs-serv31391/net/bluetooth Log Message: Directory /cvsroot/linux-vax/kernel-2.4/net/bluetooth added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:29:17
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Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips64/gcc In directory usw-pr-cvs1:/tmp/cvs-serv29516/include/asm-mips64/gcc Log Message: Directory /cvsroot/linux-vax/kernel-2.4/include/asm-mips64/gcc added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:29:17
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Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-anakin In directory usw-pr-cvs1:/tmp/cvs-serv28166/include/asm-arm/arch-anakin Log Message: Directory /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-anakin added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:29:11
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Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips64/mips-boards In directory usw-pr-cvs1:/tmp/cvs-serv29605/include/asm-mips64/mips-boards Log Message: Directory /cvsroot/linux-vax/kernel-2.4/include/asm-mips64/mips-boards added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:23:25
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Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-epxa10db In directory usw-pr-cvs1:/tmp/cvs-serv28269/include/asm-arm/arch-epxa10db Log Message: Directory /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-epxa10db added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:22:53
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Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-integrator In directory usw-pr-cvs1:/tmp/cvs-serv28096/include/asm-arm/arch-integrator Log Message: Directory /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-integrator added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:13:36
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Update of /cvsroot/linux-vax/kernel-2.4/include/net/bluetooth In directory usw-pr-cvs1:/tmp/cvs-serv25199/include/net/bluetooth Log Message: Directory /cvsroot/linux-vax/kernel-2.4/include/net/bluetooth added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:10:08
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Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/mips-boards In directory usw-pr-cvs1:/tmp/cvs-serv24128/include/asm-mips/mips-boards Log Message: Directory /cvsroot/linux-vax/kernel-2.4/include/asm-mips/mips-boards added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:09:30
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Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/gcc In directory usw-pr-cvs1:/tmp/cvs-serv23994/include/asm-mips/gcc Log Message: Directory /cvsroot/linux-vax/kernel-2.4/include/asm-mips/gcc added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:09:16
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Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/gt64120 In directory usw-pr-cvs1:/tmp/cvs-serv23899/include/asm-mips/gt64120 Log Message: Directory /cvsroot/linux-vax/kernel-2.4/include/asm-mips/gt64120 added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:09:06
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Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/ddb5xxx In directory usw-pr-cvs1:/tmp/cvs-serv23801/include/asm-mips/ddb5xxx Log Message: Directory /cvsroot/linux-vax/kernel-2.4/include/asm-mips/ddb5xxx added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:08:31
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Update of /cvsroot/linux-vax/kernel-2.4/include/linux/isdn In directory usw-pr-cvs1:/tmp/cvs-serv21452/include/linux/isdn Log Message: Directory /cvsroot/linux-vax/kernel-2.4/include/linux/isdn added to the repository |
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From: Andy P. <at...@us...> - 2002-04-09 11:07:45
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Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/it8172 In directory usw-pr-cvs1:/tmp/cvs-serv23175/include/asm-mips/it8172 Log Message: Directory /cvsroot/linux-vax/kernel-2.4/include/asm-mips/it8172 added to the repository |
