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Update of /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/xtalk
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-ia64/sn/xtalk
Modified Files:
xbow.h xbow_info.h xswitch.h xtalk.h xtalk_private.h
xtalkaddrs.h xwidget.h
Log Message:
Synch to 2.4.15 commit 1
Index: xbow.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/xtalk/xbow.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- xbow.h 14 Jan 2001 17:03:46 -0000 1.1.1.1
+++ xbow.h 9 Apr 2002 12:33:13 -0000 1.2
@@ -494,7 +494,7 @@
typedef union xbw0_status_u {
xbowreg_t statusword;
struct {
- uint32_t mult_err:1, /* Multiple error occured */
+ uint32_t mult_err:1, /* Multiple error occurred */
connect_tout:1, /* Connection timeout */
xtalk_err:1, /* Xtalk pkt with error bit */
/* End of Xbridge only */
@@ -524,7 +524,7 @@
/* End of Xbridge only */
xtalk_err:1, /* Xtalk pkt with error bit */
connect_tout:1, /* Connection timeout */
- mult_err:1; /* Multiple error occured */
+ mult_err:1; /* Multiple error occurred */
} xbw0_stfield;
} xbw0_status_t;
Index: xbow_info.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/xtalk/xbow_info.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
Index: xswitch.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/xtalk/xswitch.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
Index: xtalk.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/xtalk/xtalk.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- xtalk.h 14 Jan 2001 17:03:49 -0000 1.1.1.1
+++ xtalk.h 9 Apr 2002 12:33:13 -0000 1.2
@@ -278,6 +278,7 @@
/* INTERRUPT MANAGEMENT */
xtalk_intr_alloc_f *intr_alloc;
+ xtalk_intr_alloc_f *intr_alloc_nothd;
xtalk_intr_free_f *intr_free;
xtalk_intr_connect_f *intr_connect;
xtalk_intr_disconnect_f *intr_disconnect;
@@ -308,6 +309,7 @@
extern xtalk_dmaaddr_drain_f xtalk_dmaaddr_drain;
extern xtalk_dmalist_drain_f xtalk_dmalist_drain;
extern xtalk_intr_alloc_f xtalk_intr_alloc;
+extern xtalk_intr_alloc_f xtalk_intr_alloc_nothd;
extern xtalk_intr_free_f xtalk_intr_free;
extern xtalk_intr_connect_f xtalk_intr_connect;
extern xtalk_intr_disconnect_f xtalk_intr_disconnect;
@@ -342,10 +344,6 @@
extern iopaddr_t xtalk_intr_addr_get(xtalk_intr_t xtalk_intr);
extern devfs_handle_t xtalk_intr_cpu_get(xtalk_intr_t xtalk_intr);
extern void *xtalk_intr_sfarg_get(xtalk_intr_t xtalk_intr);
-
-extern int xtalk_intr_flags_get(xtalk_intr_t xtalk_intr);
-/* XTALK_INTR flags */
-#define XTALK_INTR_NOTHREAD 1 /* interrupt handler wants to be called at interrupt level */
/* Generic crosstalk pio interfaces */
extern devfs_handle_t xtalk_pio_dev_get(xtalk_piomap_t xtalk_piomap);
Index: xtalk_private.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/xtalk/xtalk_private.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- xtalk_private.h 14 Jan 2001 17:03:49 -0000 1.1.1.1
+++ xtalk_private.h 9 Apr 2002 12:33:13 -0000 1.2
@@ -10,11 +10,7 @@
#ifndef _ASM_SN_XTALK_XTALK_PRIVATE_H
#define _ASM_SN_XTALK_XTALK_PRIVATE_H
-#ifdef IRIX
-#include <sys/ioerror.h> /* for error function and arg types */
-#else
#include <asm/sn/ioerror.h> /* for error function and arg types */
-#endif
/*
* xtalk_private.h -- private definitions for xtalk
@@ -44,7 +40,6 @@
* All Crosstalk providers set up interrupts using this information.
*/
struct xtalk_intr_s {
- int xi_flags; /* XTALK_INTR flags */
devfs_handle_t xi_dev; /* requestor of this intr */
xwidgetnum_t xi_target; /* master's widget number */
xtalk_intr_vector_t xi_vector; /* 8-bit interrupt vector */
Index: xtalkaddrs.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/xtalk/xtalkaddrs.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- xtalkaddrs.h 14 Jan 2001 17:03:50 -0000 1.1.1.1
+++ xtalkaddrs.h 9 Apr 2002 12:33:13 -0000 1.2
@@ -10,6 +10,8 @@
#ifndef _ASM_SN_XTALK_XTALKADDRS_H
#define _ASM_SN_XTALK_XTALKADDRS_H
+#include <linux/config.h>
+
/*
* CrossTalk to SN0 Hub addressing support
*
@@ -58,8 +60,6 @@
* This looks very much like a REMOTE_HUB access, except the nodeID
* is in a different place, and the highest xtalk bit is set.
*/
-
-#include <linux/config.h>
/* Hub-specific xtalk definitions */
Index: xwidget.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/xtalk/xwidget.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-ia64/sn/pci
Modified Files:
bridge.h pci_bus_cvlink.h pci_defs.h pcibr.h pcibr_private.h
pciio.h pciio_private.h
Added Files:
pciba.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/* $Id: pciba.h,v 1.1 2002/04/09 12:33:12 atp Exp $
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
* Copyright (C) 2000 by Colin Ngam
*/
#ifndef _ASM_SN_PCI_PCIBA_H
#define _ASM_SN_PCI_PCIBA_H
/*
* These are all the HACKS from ioccom.h ..
*/
#define IOCPARM_MASK 0xff /* parameters must be < 256 bytes */
#define IOC_VOID 0x20000000 /* no parameters */
/*
* The above needs to be modified and follow LINUX ...
*/
/* /hw/.../pci/[slot]/config accepts ioctls to read
* and write specific registers as follows:
*
* "t" is the native type (char, short, uint32, uint64)
* to read from CFG space; results will be arranged in
* byte significance (ie. first byte from PCI is lowest
* or last byte in result).
*
* "r" is the byte offset in PCI CFG space of the first
* byte of the register (it's least significant byte,
* in the little-endian PCI numbering). This can actually
* be as much as 16 bits wide, and is intended to match
* the layout of a "Type 1 Configuration Space" address:
* the register number in the low eight bits, then three
* bits for the function number and five bits for the
* slot number.
*/
#define PCIIOCCFGRD(t,r) _IOR(0,(r),t)
#define PCIIOCCFGWR(t,r) _IOW(0,(r),t)
/* Some common config register access commands.
* Use these as examples of how to construct
* values for other registers you want to access.
*/
/* PCIIOCGETID: arg is ptr to 32-bit int,
* returns the 32-bit ID value with VENDOR
* in the bottom 16 bits and DEVICE in the top.
*/
#define PCIIOCGETID PCIIOCCFGRD(uint32_t,PCI_CFG_VENDOR_ID)
/* PCIIOCSETCMD: arg is ptr to a 16-bit short,
* which will be written to the CMD register.
*/
#define PCIIOCSETCMD PCIIOCCFGWR(uint16_t,PCI_CFG_COMMAND)
/* PCIIOCGETREV: arg is ptr to an 8-bit char,
* which will get the 8-bit revision number.
*/
#define PCIIOCGETREV PCIIOCCFGRD(uint8_t,PCI_CFG_REV_ID)
/* PCIIOCGETHTYPE: arg is ptr to an 8-bit char,
* which will get the 8-bit header type.
*/
#define PCIIOCGETHTYPE PCIIOCCFGRD(uint8_t,PCI_CFG_HEADER_TYPE)
/* PCIIOCGETBASE(n): arg is ptr to a 32-bit int,
* which will get the value of the BASE<n> register.
*/
#define PCIIOCGETBASE(n) PCIIOCCFGRD(uint32_t,PCI_CFG_BASE_ADDR(n))
/* /hw/.../pci/[slot]/intr accepts an ioctl to
* set up user level interrupt handling as follows:
*
* "n" is a bitmap of which of the four PCI interrupt
* lines are of interest, using PCIIO_INTR_LINE_[ABCD].
*/
#define PCIIOCSETULI(n) _IOWR(1,n,struct uliargs)
#if _KERNEL
#define PCIIOCSETULI32(n) _IOWR(1,n,struct uliargs32)
#endif
/* /hw/.../pci/[slot]/dma accepts ioctls to allocate
* and free physical memory for use in user-triggered
* DMA operations.
*/
#define PCIIOCDMAALLOC _IOWR(0,1,uint64_t)
#define PCIIOCDMAFREE _IOW(0,1,uint64_t)
/* The parameter for PCIIOCDMAALLOC needs to contain
* both the size of the request and the flag values
* to be used in setting up the DMA.
*
* Any flags normally useful in pciio_dmamap
* or pciio_dmatrans function calls can6 be used here.
*/
#define PCIIOCDMAALLOC_REQUEST_PACK(flags,size) \
((((uint64_t)(flags))<<32)| \
(((uint64_t)(size))&0xFFFFFFFF))
#endif /* _ASM_SN_PCI_PCIBA_H */
Index: bridge.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/bridge.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- bridge.h 14 Jan 2001 17:01:53 -0000 1.1.1.1
+++ bridge.h 9 Apr 2002 12:33:12 -0000 1.2
@@ -373,7 +373,7 @@
ds:2, /* Data size */
gbr:1, /* GBR enable */
vbpm:1, /* VBPM message */
- error:1, /* Error occured */
+ error:1, /* Error occurred */
barr:1, /* Barrier op */
rsvd:8;
} berr_st;
@@ -693,7 +693,7 @@
#define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
#define BRIDGE_INT_VIEW 0x000174 /* Interrupt view */
-#define BRIDGE_MULTIPLE_INT 0x00017c /* Multiple interrupt occured */
+#define BRIDGE_MULTIPLE_INT 0x00017c /* Multiple interrupt occurred */
#define BRIDGE_FORCE_ALWAYS0 0x000184 /* Force an interrupt (always)*/
#define BRIDGE_FORCE_ALWAYS_OFF 0x000008 /* Force Always offset */
Index: pci_bus_cvlink.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/pci_bus_cvlink.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- pci_bus_cvlink.h 14 Jan 2001 17:01:53 -0000 1.1.1.1
+++ pci_bus_cvlink.h 9 Apr 2002 12:33:12 -0000 1.2
@@ -26,4 +26,23 @@
int isa64;
};
+struct sn1_dma_maps_s{
+ struct pcibr_dmamap_s dma_map;
+ dma_addr_t dma_addr;
+};
+
+struct ioports_to_tlbs_s {
+ unsigned long p:1,
+ rv_1:1,
+ ma:3,
+ a:1,
+ d:1,
+ pl:2,
+ ar:3,
+ ppn:38,
+ rv_2:2,
+ ed:1,
+ ig:11;
+};
+
#endif /* _ASM_SN_PCI_CVLINK_H */
Index: pci_defs.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/pci_defs.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
Index: pcibr.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/pcibr.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- pcibr.h 14 Jan 2001 17:01:56 -0000 1.1.1.1
+++ pcibr.h 9 Apr 2002 12:33:12 -0000 1.2
@@ -143,6 +143,14 @@
extern void pcibr_dmamap_done(pcibr_dmamap_t dmamap);
+/*
+ * pcibr_get_dmatrans_node() will return the compact node id to which
+ * all 32-bit Direct Mapping memory accesses will be directed.
+ * (This node id can be different for each PCI bus.)
+ */
+
+extern cnodeid_t pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl);
+
extern iopaddr_t pcibr_dmatrans_addr(devfs_handle_t dev,
device_desc_t dev_desc,
paddr_t paddr,
@@ -215,10 +223,6 @@
pciio_space_t *spacep,
iopaddr_t *addrp);
-extern int pcibr_rrb_alloc(devfs_handle_t pconn_vhdl,
- int *count_vchan0,
- int *count_vchan1);
-
extern int pcibr_wrb_flush(devfs_handle_t pconn_vhdl);
extern int pcibr_rrb_check(devfs_handle_t pconn_vhdl,
int *count_vchan0,
@@ -241,7 +245,7 @@
void pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl,
rrb_alloc_funct_f *func);
-extern void pcibr_device_unregister(devfs_handle_t);
+extern int pcibr_device_unregister(devfs_handle_t);
extern int pcibr_dma_enabled(devfs_handle_t);
/*
* Bridge-specific flags that can be set via pcibr_device_flags_set
@@ -337,7 +341,7 @@
extern void pcibr_hints_fix_rrbs(devfs_handle_t);
extern void pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
-extern void pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, uint64_t);
+extern void pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong);
extern void pcibr_hints_handsoff(devfs_handle_t);
typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t);
@@ -353,8 +357,104 @@
#define PCIBR 'p'
#define _PCIBR(x) ((PCIBR << 8) | (x))
-#define PCIBR_SLOT_POWERUP _PCIBR(1)
-#define PCIBR_SLOT_SHUTDOWN _PCIBR(2)
-#define PCIBR_SLOT_INQUIRY _PCIBR(3)
+#define PCIBR_SLOT_STARTUP _PCIBR(1)
+#define PCIBR_SLOT_SHUTDOWN _PCIBR(2)
+#define PCIBR_SLOT_QUERY _PCIBR(3)
+
+/*
+ * Bit defintions for variable slot_status in struct
+ * pcibr_soft_slot_s. They are here so that both
+ * the pcibr driver and the pciconfig command can
+ * reference them.
+ */
+#define SLOT_STARTUP_CMPLT 0x01
+#define SLOT_STARTUP_INCMPLT 0x02
+#define SLOT_SHUTDOWN_CMPLT 0x04
+#define SLOT_SHUTDOWN_INCMPLT 0x08
+#define SLOT_POWER_UP 0x10
+#define SLOT_POWER_DOWN 0x20
+#define SLOT_IS_SYS_CRITICAL 0x40
+
+#define SLOT_STATUS_MASK (SLOT_STARTUP_CMPLT | SLOT_STARTUP_INCMPLT | \
+ SLOT_SHUTDOWN_CMPLT | SLOT_SHUTDOWN_INCMPLT)
+#define SLOT_POWER_MASK (SLOT_POWER_UP | SLOT_POWER_DOWN)
+
+/*
+ * Bit definitions for variable resp_f_staus.
+ * They are here so that both the pcibr driver
+ * and the pciconfig command can reference them.
+ */
+#define FUNC_IS_VALID 0x01
+#define FUNC_IS_SYS_CRITICAL 0x02
+
+/*
+ * Structures for requesting PCI bridge information and receiving a response
+ */
+typedef struct pcibr_slot_info_req_s *pcibr_slot_info_req_t;
+typedef struct pcibr_slot_info_resp_s *pcibr_slot_info_resp_t;
+typedef struct pcibr_slot_func_info_resp_s *pcibr_slot_func_info_resp_t;
+
+struct pcibr_slot_info_req_s {
+ int req_slot;
+ pcibr_slot_info_resp_t req_respp;
+ int req_size;
+};
+
+struct pcibr_slot_info_resp_s {
+ int resp_has_host;
+ char resp_host_slot;
+ devfs_handle_t resp_slot_conn;
+ char resp_slot_conn_name[MAXDEVNAME];
+ int resp_slot_status;
+ int resp_l1_bus_num;
+ int resp_bss_ninfo;
+ char resp_bss_devio_bssd_space[16];
+ iopaddr_t resp_bss_devio_bssd_base;
+ bridgereg_t resp_bss_device;
+ int resp_bss_pmu_uctr;
+ int resp_bss_d32_uctr;
+ int resp_bss_d64_uctr;
+ iopaddr_t resp_bss_d64_base;
+ unsigned resp_bss_d64_flags;
+ iopaddr_t resp_bss_d32_base;
+ unsigned resp_bss_d32_flags;
+ int resp_bss_ext_ates_active;
+ volatile unsigned *resp_bss_cmd_pointer;
+ unsigned resp_bss_cmd_shadow;
+ int resp_bs_rrb_valid;
+ int resp_bs_rrb_valid_v;
+ int resp_bs_rrb_res;
+ bridgereg_t resp_b_resp;
+ bridgereg_t resp_b_int_device;
+ bridgereg_t resp_b_int_enable;
+ bridgereg_t resp_b_int_host;
+
+ struct pcibr_slot_func_info_resp_s {
+ int resp_f_status;
+ char resp_f_slot_name[MAXDEVNAME];
+ char resp_f_bus;
+ char resp_f_slot;
+ char resp_f_func;
+ char resp_f_master_name[MAXDEVNAME];
+ void *resp_f_pops;
+ error_handler_f *resp_f_efunc;
+ error_handler_arg_t resp_f_einfo;
+ int resp_f_vendor;
+ int resp_f_device;
+
+ struct {
+ char resp_w_space[16];
+ iopaddr_t resp_w_base;
+ size_t resp_w_size;
+ } resp_f_window[6];
+
+ unsigned resp_f_rbase;
+ unsigned resp_f_rsize;
+ int resp_f_ibit[4];
+ int resp_f_att_det_error;
+
+ } resp_func[8];
+
+};
#endif /* _ASM_SN_PCI_PCIBR_H */
Index: pcibr_private.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/pcibr_private.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- pcibr_private.h 14 Jan 2001 17:01:58 -0000 1.1.1.1
+++ pcibr_private.h 9 Apr 2002 12:33:12 -0000 1.2
@@ -17,6 +17,7 @@
*/
#include <asm/sn/pci/pciio_private.h>
+#include <asm/sn/ksys/l1.h>
/*
* convenience typedefs
@@ -31,6 +32,7 @@
typedef struct pcibr_hints_s *pcibr_hints_t;
typedef struct pcibr_intr_list_s *pcibr_intr_list_t;
typedef struct pcibr_intr_wrap_s *pcibr_intr_wrap_t;
+typedef struct pcibr_intr_cbuf_s *pcibr_intr_cbuf_t;
/*
* Bridge sets up PIO using this information.
@@ -50,7 +52,7 @@
xtalk_piomap_t bp_xtalk_pio; /* corresponding xtalk resource */
pcibr_piomap_t bp_next; /* Next piomap on the list */
pcibr_soft_t bp_soft; /* backpointer to bridge soft data */
- int bp_toc[1]; /* PCI timeout counter */
+ atomic_t bp_toc[1]; /* PCI timeout counter */
};
@@ -77,6 +79,18 @@
bridge_ate_t bd_ate_prime; /* value of 1st ATE written */
};
+#define IBUFSIZE 5 /* size of circular buffer (holds 4) */
+
+/*
+ * Circular buffer used for interrupt processing
+ */
+struct pcibr_intr_cbuf_s {
+ spinlock_t ib_lock; /* cbuf 'put' lock */
+ int ib_in; /* index of next free entry */
+ int ib_out; /* index of next full entry */
+ pcibr_intr_wrap_t ib_cbuf[IBUFSIZE]; /* circular buffer of wrap */
+};
+
/*
* Bridge sets up interrupts using this information.
*/
@@ -94,6 +108,7 @@
#define bi_cpu bi_pi.pi_cpu /* cpu assigned. */
unsigned bi_ibits; /* which Bridge interrupt bit(s) */
pcibr_soft_t bi_soft; /* shortcut to soft info */
+ struct pcibr_intr_cbuf_s bi_ibuf; /* circular buffer of wrap ptrs */
};
/*
@@ -121,6 +136,7 @@
/* pcibr-specific connection state */
int f_ibit[4]; /* Bridge bit for each INTx */
pcibr_piomap_t f_piomap;
+ int f_att_det_error;
};
/* =====================================================================
@@ -139,8 +155,11 @@
struct pcibr_intr_wrap_s {
pcibr_soft_t iw_soft; /* which bridge */
volatile bridgereg_t *iw_stat; /* ptr to b_int_status */
- bridgereg_t iw_intr; /* bits in b_int_status */
+ bridgereg_t iw_intr; /* bit in b_int_status */
pcibr_intr_list_t iw_list; /* ghostbusters! */
+ int iw_hdlrcnt; /* running handler count */
+ int iw_shared; /* if Bridge bit is shared */
+ int iw_connected; /* if already connected */
};
#define PCIBR_ISR_ERR_START 8
@@ -175,11 +194,14 @@
unsigned bs_dma_flags; /* revision-implied DMA flags */
+ l1sc_t *bs_l1sc; /* io brick l1 system cntr */
+ moduleid_t bs_moduleid; /* io brick moduleid */
+
/*
* Lock used primarily to get mutual exclusion while managing any
* bridge resources..
*/
- lock_t bs_lock;
+ spinlock_t bs_lock;
devfs_handle_t bs_noslot_conn; /* NO-SLOT connection point */
pcibr_info_t bs_noslot_info;
@@ -199,6 +221,9 @@
int has_host;
pciio_slot_t host_slot;
devfs_handle_t slot_conn;
+
+ int slot_status;
+
/* Potentially several connection points
* for this slot. bss_ninfo is how many,
* and bss_infos is a pointer to
@@ -265,7 +290,7 @@
/* Shadow information used for implementing
* Bridge Hardware WAR #484930
*/
- int bss_ext_ates_active;
+ atomic_t bss_ext_ates_active;
volatile unsigned *bss_cmd_pointer;
unsigned bss_cmd_shadow;
@@ -295,13 +320,10 @@
*/
xtalk_intr_t bsi_xtalk_intr;
/*
- * We do not like sharing PCI interrrupt lines
- * between devices, but the Origin 200 PCI
- * layout forces us to do so.
+ * A wrapper structure is associated with each
+ * Bridge interrupt bit.
*/
- pcibr_intr_list_t bsi_pcibr_intr_list;
- pcibr_intr_wrap_t bsi_pcibr_intr_wrap;
- int bsi_pcibr_wrap_set;
+ struct pcibr_intr_wrap_s bsi_pcibr_intr_wrap;
} bs_intr[8];
@@ -325,10 +347,10 @@
*/
struct br_errintr_info {
int bserr_toutcnt;
-#ifdef IRIX
+#ifdef LATER
toid_t bserr_toutid; /* Timeout started by errintr */
#endif
- iopaddr_t bserr_addr; /* Address where error occured */
+ iopaddr_t bserr_addr; /* Address where error occurred */
bridgereg_t bserr_intstat; /* interrupts active at error time */
} bs_errinfo;
Index: pciio.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/pciio.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- pciio.h 14 Jan 2001 17:02:01 -0000 1.1.1.1
+++ pciio.h 9 Apr 2002 12:33:12 -0000 1.2
@@ -35,15 +35,9 @@
#define PCIIO_DEVICE_ID_NONE -1
-#ifdef colin
-typedef char pciio_bus_t; /* PCI bus number (0..255) */
-typedef char pciio_slot_t; /* PCI slot number (0..31, 255) */
-typedef char pciio_function_t; /* PCI func number (0..7, 255) */
-#else
typedef uint8_t pciio_bus_t; /* PCI bus number (0..255) */
typedef uint8_t pciio_slot_t; /* PCI slot number (0..31, 255) */
typedef uint8_t pciio_function_t; /* PCI func number (0..7, 255) */
-#endif
#define PCIIO_SLOTS ((pciio_slot_t)32)
#define PCIIO_FUNCS ((pciio_function_t)8)
@@ -446,6 +440,24 @@
pciio_space_t *spacep,
iopaddr_t *addrp);
+typedef void
+pciio_driver_reg_callback_f (devfs_handle_t conn,
+ int key1,
+ int key2,
+ int error);
+
+typedef void
+pciio_driver_unreg_callback_f (devfs_handle_t conn, /* pci connection point */
+ int key1,
+ int key2,
+ int error);
+
+typedef int
+pciio_device_unregister_f (devfs_handle_t conn);
+
+typedef int
+pciio_dma_enabled_f (devfs_handle_t conn);
+
/*
* Adapters that provide a PCI interface adhere to this software interface.
*/
@@ -491,6 +503,12 @@
/* Error handling interface */
pciio_error_devenable_f *error_devenable;
pciio_error_extract_f *error_extract;
+
+ /* Callback support */
+ pciio_driver_reg_callback_f *driver_reg_callback;
+ pciio_driver_unreg_callback_f *driver_unreg_callback;
+ pciio_device_unregister_f *device_unregister;
+ pciio_dma_enabled_f *dma_enabled;
} pciio_provider_t;
/* PCI devices use these standard PCI provider interfaces */
@@ -540,13 +558,8 @@
#define PCIIO_WIDGETDEV_SLOT_MASK 0x1f
#define PCIIO_WIDGETDEV_FUNC_MASK 0x7
-#ifdef IRIX
-#define pciio_widgetdev_create(slot,func) \
- ((slot) << PCIIO_WIDGETDEV_SLOT_SHFT + (func))
-#else
#define pciio_widgetdev_create(slot,func) \
(((slot) << PCIIO_WIDGETDEV_SLOT_SHFT) + (func))
-#endif
#define pciio_widgetdev_slot_get(wdev) \
(((wdev) >> PCIIO_WIDGETDEV_SLOT_SHFT) & PCIIO_WIDGETDEV_SLOT_MASK)
@@ -612,8 +625,14 @@
pciio_info_t pciio_info); /* details about conn point */
-extern int pciio_device_attach(devfs_handle_t pcicard); /* vertex created by pciio_device_register */
-extern int pciio_device_detach(devfs_handle_t pcicard); /* vertex created by pciio_device_register */
+extern int
+pciio_device_attach(
+ devfs_handle_t pcicard, /* vertex created by pciio_device_register */
+ int drv_flags);
+extern int
+pciio_device_detach(
+ devfs_handle_t pcicard, /* vertex created by pciio_device_register */
+ int drv_flags);
/*
* Generic PCI interface, for use with all PCI providers
@@ -632,7 +651,7 @@
extern ulong pciio_pio_mapsz_get(pciio_piomap_t pciio_piomap);
extern caddr_t pciio_pio_kvaddr_get(pciio_piomap_t pciio_piomap);
-#ifdef IRIX
+#ifdef LATER
#ifdef USE_PCI_PIO
extern uint8_t pciio_pio_read8(volatile uint8_t *addr);
extern uint16_t pciio_pio_read16(volatile uint16_t *addr);
@@ -676,7 +695,7 @@
*addr = val;
}
#endif /* USE_PCI_PIO */
-#endif
+#endif /* LATER */
/* Generic PCI dma interfaces */
extern devfs_handle_t pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap);
Index: pciio_private.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/pci/pciio_private.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- pciio_private.h 14 Jan 2001 17:02:02 -0000 1.1.1.1
+++ pciio_private.h 9 Apr 2002 12:33:12 -0000 1.2
@@ -10,10 +10,6 @@
#ifndef _ASM_SN_PCI_PCIIO_PRIVATE_H
#define _ASM_SN_PCI_PCIIO_PRIVATE_H
-#ifdef colin
-#include <ksys/xthread.h>
-#endif
-
/*
* pciio_private.h -- private definitions for pciio
* PCI drivers should NOT include this file.
@@ -54,12 +50,12 @@
pciio_intr_line_t pi_lines; /* which interrupt line(s) */
intr_func_t pi_func; /* handler function (when connected) */
intr_arg_t pi_arg; /* handler parameter (when connected) */
-#ifdef IRIX
+#ifdef LATER
thd_int_t pi_tinfo; /* Thread info (when connected) */
#endif
cpuid_t pi_mustruncpu; /* Where we must run. */
- int pi_irq; /* IRQ assigned */
- int pi_cpu; /* cpu assigned */
+ int pi_irq; /* IRQ assigned */
+ int pi_cpu; /* cpu assigned */
};
/* PCIIO_INTR (pi_flags) flags */
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:34:04
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/proc-armv
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/proc-armv
Modified Files:
cache.h pgtable.h system.h uaccess.h
Added Files:
pgalloc.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/*
* linux/include/asm-arm/proc-armv/pgalloc.h
*
* Copyright (C) 2001 Russell King
*
* Page table allocation/freeing primitives for 32-bit ARM processors.
*/
/* unfortunately, this includes linux/mm.h and the rest of the universe. */
#include <linux/slab.h>
extern kmem_cache_t *pte_cache;
/*
* Allocate one PTE table.
*
* Note that we keep the processor copy of the PTE entries separate
* from the Linux copy. The processor copies are offset by -PTRS_PER_PTE
* words from the Linux copy.
*/
static inline pte_t *pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
pte_t *pte;
pte = kmem_cache_alloc(pte_cache, GFP_KERNEL);
if (pte)
pte += PTRS_PER_PTE;
return pte;
}
/*
* Free one PTE table.
*/
static inline void pte_free_slow(pte_t *pte)
{
if (pte) {
pte -= PTRS_PER_PTE;
kmem_cache_free(pte_cache, pte);
}
}
/*
* Populate the pmdp entry with a pointer to the pte. This pmd is part
* of the mm address space.
*
* If 'mm' is the init tasks mm, then we are doing a vmalloc, and we
* need to set stuff up correctly for it.
*/
#define pmd_populate(mm,pmdp,pte) \
do { \
unsigned long __prot; \
if (mm == &init_mm) \
__prot = _PAGE_KERNEL_TABLE; \
else \
__prot = _PAGE_USER_TABLE; \
set_pmd(pmdp, __mk_pmd(pte, __prot)); \
} while (0)
Index: cache.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/proc-armv/cache.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- cache.h 14 Jan 2001 16:58:46 -0000 1.1.1.1
+++ cache.h 9 Apr 2002 12:33:10 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/proc-armv/cache.h
*
- * Copyright (C) 1999-2000 Russell King
+ * Copyright (C) 1999-2001 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -10,6 +10,12 @@
#include <asm/mman.h>
/*
+ * This flag is used to indicate that the page pointed to by a pte
+ * is dirty and requires cleaning before returning it to the user.
+ */
+#define PG_dcache_dirty PG_arch_1
+
+/*
* Cache handling for 32-bit ARM processors.
*
* Note that on ARM, we have a more accurate specification than that
@@ -54,6 +60,33 @@
/*
* This flushes back any buffered write data. We have to clean the entries
* in the cache for this page. This does not invalidate either I or D caches.
+ *
+ * Called from:
+ * 1. mm/filemap.c:filemap_nopage
+ * 2. mm/filemap.c:filemap_nopage
+ * [via do_no_page - ok]
+ *
+ * 3. mm/memory.c:break_cow
+ * [copy_cow_page doesn't do anything to the cache; insufficient cache
+ * handling. Need to add flush_dcache_page() here]
+ *
+ * 4. mm/memory.c:do_swap_page
+ * [read_swap_cache_async doesn't do anything to the cache: insufficient
+ * cache handling. Need to add flush_dcache_page() here]
+ *
+ * 5. mm/memory.c:do_anonymous_page
+ * [zero page, never written by kernel - ok]
+ *
+ * 6. mm/memory.c:do_no_page
+ * [we will be calling update_mmu_cache, which will catch on PG_dcache_dirty]
+ *
+ * 7. mm/shmem.c:shmem_nopage
+ * 8. mm/shmem.c:shmem_nopage
+ * [via do_no_page - ok]
+ *
+ * 9. fs/exec.c:put_dirty_page
+ * [we call flush_dcache_page prior to this, which will flush out the
+ * kernel virtual addresses from the dcache - ok]
*/
static __inline__ void flush_page_to_ram(struct page *page)
{
@@ -69,26 +102,71 @@
#define flush_dcache_range(_s,_e) cpu_cache_clean_invalidate_range((_s),(_e),0)
/*
- * FIXME: We currently clean the dcache for this page. Should we
- * also invalidate the Dcache? And what about the Icache? -- rmk
+ * flush_dcache_page is used when the kernel has written to the page
+ * cache page at virtual address page->virtual.
+ *
+ * If this page isn't mapped (ie, page->mapping = NULL), or it has
+ * userspace mappings (page->mapping->i_mmap or page->mapping->i_mmap_shared)
+ * then we _must_ always clean + invalidate the dcache entries associated
+ * with the kernel mapping.
+ *
+ * Otherwise we can defer the operation, and clean the cache when we are
+ * about to change to user space. This is the same method as used on SPARC64.
+ * See update_mmu_cache for the user space part.
*/
-#define flush_dcache_page(page) cpu_dcache_clean_page(page_address(page))
+static inline void flush_dcache_page(struct page *page)
+{
+ if (page->mapping && !(page->mapping->i_mmap) &&
+ !(page->mapping->i_mmap_shared))
+ set_bit(PG_dcache_dirty, &page->flags);
+ else {
+ unsigned long virt = (unsigned long)page_address(page);
+ cpu_cache_clean_invalidate_range(virt, virt + PAGE_SIZE, 0);
+ }
+}
#define clean_dcache_entry(_s) cpu_dcache_clean_entry((unsigned long)(_s))
/*
- * I cache only
+ * I cache coherency stuff.
+ *
+ * This *is not* just icache. It is to make data written to memory
+ * consistent such that instructions fetched from the region are what
+ * we expect.
+ *
+ * This generally means that we have to clean out the Dcache and write
+ * buffers, and maybe flush the Icache in the specified range.
*/
#define flush_icache_range(_s,_e) \
do { \
cpu_icache_invalidate_range((_s), (_e)); \
} while (0)
-#define flush_icache_page(vma,pg) \
- do { \
- if ((vma)->vm_flags & PROT_EXEC) \
- cpu_icache_invalidate_page(page_address(pg)); \
- } while (0)
+/*
+ * This function is misnamed IMHO. There are three places where it
+ * is called, each of which is preceded immediately by a call to
+ * flush_page_to_ram:
+ *
+ * 1. kernel/ptrace.c:access_one_page
+ * called after we have written to the kernel view of a user page.
+ * The user page has been expundged from the cache by flush_cache_page.
+ * [we don't need to do anything here if we add a call to
+ * flush_dcache_page]
+ *
+ * 2. mm/memory.c:do_swap_page
+ * called after we have (possibly) written to the kernel view of a
+ * user page, which has previously been removed (ie, has been through
+ * the swap cache).
+ * [if the flush_page_to_ram() conditions are satisfied, then ok]
+ *
+ * 3. mm/memory.c:do_no_page
+ * [if the flush_page_to_ram() conditions are satisfied, then ok]
+ *
+ * Invalidating the icache at the kernels virtual page isn't really
+ * going to do us much good, since we wouldn't have executed any
+ * instructions there.
+ */
+#define flush_icache_page(vma,pg) do { } while (0)
/*
* Old ARM MEMC stuff. This supports the reversed mapping handling that
@@ -154,3 +232,10 @@
cpu_tlb_invalidate_page((_page), \
((_vma)->vm_flags & VM_EXEC)); \
} while (0)
+
+/*
+ * if PG_dcache_dirty is set for the page, we need to ensure that any
+ * cache entries for the kernels virtual memory range are written
+ * back to the page.
+ */
+extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/proc-armv/pgtable.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- pgtable.h 25 Feb 2001 23:14:53 -0000 1.1.1.2
+++ pgtable.h 9 Apr 2002 12:33:10 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/proc-armv/pgtable.h
*
- * Copyright (C) 1995-1999 Russell King
+ * Copyright (C) 1995-2001 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -48,7 +48,7 @@
#define pmd_bad(pmd) (pmd_val(pmd) & 2)
#define set_pmd(pmdp,pmd) cpu_set_pmd(pmdp,pmd)
-extern __inline__ pmd_t __mk_pmd(pte_t *ptep, unsigned long prot)
+static inline pmd_t __mk_pmd(pte_t *ptep, unsigned long prot)
{
unsigned long pte_ptr = (unsigned long)ptep;
pmd_t pmd;
@@ -64,11 +64,7 @@
return pmd;
}
-/* these are aliases for the above function */
-#define mk_user_pmd(ptep) __mk_pmd(ptep, _PAGE_USER_TABLE)
-#define mk_kernel_pmd(ptep) __mk_pmd(ptep, _PAGE_KERNEL_TABLE)
-
-extern __inline__ unsigned long pmd_page(pmd_t pmd)
+static inline unsigned long pmd_page(pmd_t pmd)
{
unsigned long ptr;
@@ -149,7 +145,7 @@
#define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG)
#define PTE_BIT_FUNC(fn,op) \
-extern inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
+static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
/*PTE_BIT_FUNC(rdprotect, &= ~L_PTE_USER);*/
/*PTE_BIT_FUNC(mkread, |= L_PTE_USER);*/
@@ -161,7 +157,6 @@
PTE_BIT_FUNC(mkdirty, |= L_PTE_DIRTY);
PTE_BIT_FUNC(mkold, &= ~L_PTE_YOUNG);
PTE_BIT_FUNC(mkyoung, |= L_PTE_YOUNG);
-PTE_BIT_FUNC(nocache, &= ~L_PTE_CACHEABLE);
/*
* Mark the prot value as uncacheable and unbufferable.
Index: system.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/proc-armv/system.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- system.h 14 Jan 2001 16:58:45 -0000 1.1.1.1
+++ system.h 9 Apr 2002 12:33:10 -0000 1.2
@@ -17,9 +17,31 @@
"mcr p15, 0, %0, c1, c0 @ set CR" \
: : "r" (x))
+#define CR_M (1 << 0) /* MMU enable */
+#define CR_A (1 << 1) /* Alignment abort enable */
+#define CR_C (1 << 2) /* Dcache enable */
+#define CR_W (1 << 3) /* Write buffer enable */
+#define CR_P (1 << 4) /* 32-bit exception handler */
+#define CR_D (1 << 5) /* 32-bit data address range */
+#define CR_L (1 << 6) /* Implementation defined */
+#define CD_B (1 << 7) /* Big endian */
+#define CR_S (1 << 8) /* System MMU protection */
+#define CD_R (1 << 9) /* ROM MMU protection */
+#define CR_F (1 << 10) /* Implementation defined */
+#define CR_Z (1 << 11) /* Implementation defined */
+#define CR_I (1 << 12) /* Icache enable */
+#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
+#define CR_RR (1 << 14) /* Round Robin cache replacement */
+
extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
extern unsigned long cr_alignment; /* defined in entry-armv.S */
+#ifdef __ARM_ARCH_4__
+#define vectors_base() ((cr_alignment & CR_V) ? 0xffff0000 : 0)
+#else
+#define vectors_base() (0)
+#endif
+
/*
* A couple of speedups for the ARM
*/
@@ -135,7 +157,7 @@
#define swp_is_buggy
#endif
-extern __inline__ unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
{
extern void __bad_xchg(volatile void *, int);
unsigned long ret;
Index: uaccess.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/proc-armv/uaccess.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- uaccess.h 14 Jan 2001 16:58:46 -0000 1.1.1.1
+++ uaccess.h 9 Apr 2002 12:33:10 -0000 1.2
@@ -14,7 +14,7 @@
#define KERNEL_DS 0x00000000
#define USER_DS PAGE_OFFSET
-extern __inline__ void set_fs (mm_segment_t fs)
+static inline void set_fs (mm_segment_t fs)
{
current->addr_limit = fs;
@@ -24,7 +24,7 @@
/* We use 33-bit arithmetic here... */
#define __range_ok(addr,size) ({ \
unsigned long flag, sum; \
- __asm__ __volatile__("adds %1, %2, %3; sbcccs %1, %1, %0; movcc %0, #0" \
+ __asm__("adds %1, %2, %3; sbcccs %1, %1, %0; movcc %0, #0" \
: "=&r" (flag), "=&r" (sum) \
: "r" (addr), "Ir" (size), "0" (current->addr_limit) \
: "cc"); \
@@ -32,7 +32,7 @@
#define __addr_ok(addr) ({ \
unsigned long flag; \
- __asm__ __volatile__("cmp %2, %0; movlo %0, #0" \
+ __asm__("cmp %2, %0; movlo %0, #0" \
: "=&r" (flag) \
: "0" (current->addr_limit), "r" (addr) \
: "cc"); \
@@ -57,24 +57,9 @@
#define __put_user_asm_half(x,addr,err) \
({ \
unsigned long __temp = (unsigned long)(x); \
- __asm__ __volatile__( \
- "1: strbt %1,[%3],#0\n" \
- "2: strbt %2,[%4],#0\n" \
- "3:\n" \
- " .section .fixup,\"ax\"\n" \
- " .align 2\n" \
- "4: mov %0, %5\n" \
- " b 3b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .align 3\n" \
- " .long 1b, 4b\n" \
- " .long 2b, 4b\n" \
- " .previous" \
- : "=r" (err) \
- : "r" (__temp), "r" (__temp >> 8), \
- "r" (addr), "r" ((int)(addr) + 1), \
- "i" (-EFAULT), "0" (err)); \
+ unsigned long __ptr = (unsigned long)(addr); \
+ __put_user_asm_byte(__temp, __ptr, err); \
+ __put_user_asm_byte(__temp >> 8, __ptr + 1, err); \
})
#define __put_user_asm_word(x,addr,err) \
@@ -107,31 +92,15 @@
" .align 3\n" \
" .long 1b, 3b\n" \
" .previous" \
- : "=r" (err), "=r" (x) \
+ : "=r" (err), "=&r" (x) \
: "r" (addr), "i" (-EFAULT), "0" (err))
#define __get_user_asm_half(x,addr,err) \
({ \
- unsigned long __temp; \
- __asm__ __volatile__( \
- "1: ldrbt %1,[%3],#0\n" \
- "2: ldrbt %2,[%4],#0\n" \
- " orr %1, %1, %2, lsl #8\n" \
- "3:\n" \
- " .section .fixup,\"ax\"\n" \
- " .align 2\n" \
- "4: mov %0, %5\n" \
- " mov %1, #0\n" \
- " b 3b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .align 3\n" \
- " .long 1b, 4b\n" \
- " .long 2b, 4b\n" \
- " .previous" \
- : "=r" (err), "=r" (x), "=&r" (__temp) \
- : "r" (addr), "r" ((int)(addr) + 1), \
- "i" (-EFAULT), "0" (err)); \
+ unsigned long __b1, __b2, __ptr = (unsigned long)addr; \
+ __get_user_asm_byte(__b1, __ptr, err); \
+ __get_user_asm_byte(__b2, __ptr + 1, err); \
+ (x) = __b1 | (__b2 << 8); \
})
@@ -149,7 +118,7 @@
" .align 3\n" \
" .long 1b, 3b\n" \
" .previous" \
- : "=r" (err), "=r" (x) \
+ : "=r" (err), "=&r" (x) \
: "r" (addr), "i" (-EFAULT), "0" (err))
extern unsigned long __arch_copy_from_user(void *to, const void *from, unsigned long n);
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:34:04
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/arc In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-ia64/sn/arc Modified Files: hinv.h Log Message: Synch to 2.4.15 commit 1 Index: hinv.h =================================================================== RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-ia64/sn/arc/hinv.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- hinv.h 14 Jan 2001 17:01:39 -0000 1.1.1.1 +++ hinv.h 9 Apr 2002 12:33:12 -0000 1.2 @@ -89,7 +89,7 @@ PCIAdapter, GIOAdapter, TPUAdapter, - + TernaryCache, Anonymous } CONFIGTYPE; |
|
From: Andy P. <at...@us...> - 2002-04-09 12:34:03
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/proc-armo
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/proc-armo
Modified Files:
cache.h pgtable.h ptrace.h system.h uaccess.h
Added Files:
pgalloc.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/*
* linux/include/asm-arm/proc-armo/pgalloc.h
*
* Copyright (C) 2001 Russell King
*
* Page table allocation/freeing primitives for 26-bit ARM processors.
*/
/* unfortunately, this includes linux/mm.h and the rest of the universe. */
#include <linux/slab.h>
extern kmem_cache_t *pte_cache;
/*
* Allocate one PTE table.
*
* Note that we keep the processor copy of the PTE entries separate
* from the Linux copy. The processor copies are offset by -PTRS_PER_PTE
* words from the Linux copy.
*/
static inline pte_t *pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
return kmem_cache_alloc(pte_cache, GFP_KERNEL);
}
/*
* Free one PTE table.
*/
static inline void pte_free_slow(pte_t *pte)
{
if (pte)
kmem_cache_free(pte_cache, pte);
}
/*
* Populate the pmdp entry with a pointer to the pte. This pmd is part
* of the mm address space.
*
* If 'mm' is the init tasks mm, then we are doing a vmalloc, and we
* need to set stuff up correctly for it.
*/
#define pmd_populate(mm,pmdp,pte) \
do { \
set_pmd(pmdp, __mk_pmd(pte, _PAGE_TABLE)); \
} while (0)
Index: cache.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/proc-armo/cache.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- cache.h 14 Jan 2001 16:58:42 -0000 1.1.1.1
+++ cache.h 9 Apr 2002 12:33:10 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/proc-armo/cache.h
*
- * Copyright (C) 1999-2000 Russell King
+ * Copyright (C) 1999-2001 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -37,14 +37,15 @@
* - flush_tlb_range(mm, start, end) flushes a range of pages
*/
#define flush_tlb_all() memc_update_all()
-#define flush_tlb_mm(mm) do { } while (0)
-#define flush_tlb_range(mm, start, end) do { (void)(start); (void)(end); } while (0)
+#define flush_tlb_mm(mm) memc_update_mm(mm)
+#define flush_tlb_range(mm,start,end) \
+ do { memc_update_mm(mm); (void)(start); (void)(end); } while (0)
#define flush_tlb_page(vma, vmaddr) do { } while (0)
/*
* The following handle the weird MEMC chip
*/
-extern __inline__ void memc_update_all(void)
+static inline void memc_update_all(void)
{
struct task_struct *p;
@@ -57,7 +58,7 @@
processor._set_pgd(current->active_mm->pgd);
}
-extern __inline__ void memc_update_mm(struct mm_struct *mm)
+static inline void memc_update_mm(struct mm_struct *mm)
{
cpu_memc_update_all(mm->pgd);
@@ -65,20 +66,27 @@
processor._set_pgd(mm->pgd);
}
-extern __inline__ void
-memc_update_addr(struct mm_struct *mm, pte_t pte, unsigned long vaddr)
+static inline void
+memc_clear(struct mm_struct *mm, struct page *page)
{
- cpu_memc_update_entry(mm->pgd, pte_val(pte), vaddr);
+ cpu_memc_update_entry(mm->pgd, (unsigned long) page_address(page), 0);
if (mm == current->active_mm)
processor._set_pgd(mm->pgd);
}
-extern __inline__ void
-memc_clear(struct mm_struct *mm, struct page *page)
+static inline void
+memc_update_addr(struct mm_struct *mm, pte_t pte, unsigned long vaddr)
{
- cpu_memc_update_entry(mm->pgd, (unsigned long) page_address(page), 0);
+ cpu_memc_update_entry(mm->pgd, pte_val(pte), vaddr);
if (mm == current->active_mm)
processor._set_pgd(mm->pgd);
+}
+
+static inline void
+update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+{
+ struct mm_struct *mm = vma->vm_mm;
+ memc_update_addr(mm, pte, addr);
}
Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/proc-armo/pgtable.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- pgtable.h 25 Feb 2001 23:14:53 -0000 1.1.1.2
+++ pgtable.h 9 Apr 2002 12:33:10 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/proc-armo/pgtable.h
*
- * Copyright (C) 1995-1999 Russell King
+ * Copyright (C) 1995-2001 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -33,7 +33,7 @@
#define pmd_bad(pmd) ((pmd_val(pmd) & 0xfc000002))
#define set_pmd(pmdp,pmd) ((*(pmdp)) = (pmd))
-extern __inline__ pmd_t __mk_pmd(pte_t *ptep, unsigned long prot)
+static inline pmd_t __mk_pmd(pte_t *ptep, unsigned long prot)
{
unsigned long pte_ptr = (unsigned long)ptep;
pmd_t pmd;
@@ -43,11 +43,7 @@
return pmd;
}
-/* these are aliases for the above function */
-#define mk_user_pmd(ptep) __mk_pmd(ptep, _PAGE_TABLE)
-#define mk_kernel_pmd(ptep) __mk_pmd(ptep, _PAGE_TABLE)
-
-extern __inline__ unsigned long pmd_page(pmd_t pmd)
+static inline unsigned long pmd_page(pmd_t pmd)
{
return __phys_to_virt(pmd_val(pmd) & ~_PAGE_TABLE);
}
@@ -81,18 +77,17 @@
#define pte_dirty(pte) (!(pte_val(pte) & _PAGE_CLEAN))
#define pte_young(pte) (!(pte_val(pte) & _PAGE_OLD))
-extern inline pte_t pte_nocache(pte_t pte) { return pte; }
-extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_READONLY; return pte; }
-extern inline pte_t pte_rdprotect(pte_t pte) { pte_val(pte) |= _PAGE_NOT_USER; return pte; }
-extern inline pte_t pte_exprotect(pte_t pte) { pte_val(pte) |= _PAGE_NOT_USER; return pte; }
-extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) |= _PAGE_CLEAN; return pte; }
-extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) |= _PAGE_OLD; return pte; }
-
-extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) &= ~_PAGE_READONLY; return pte; }
-extern inline pte_t pte_mkread(pte_t pte) { pte_val(pte) &= ~_PAGE_NOT_USER; return pte; }
-extern inline pte_t pte_mkexec(pte_t pte) { pte_val(pte) &= ~_PAGE_NOT_USER; return pte; }
-extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) &= ~_PAGE_CLEAN; return pte; }
-extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) &= ~_PAGE_OLD; return pte; }
+static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_READONLY; return pte; }
+static inline pte_t pte_rdprotect(pte_t pte) { pte_val(pte) |= _PAGE_NOT_USER; return pte; }
+static inline pte_t pte_exprotect(pte_t pte) { pte_val(pte) |= _PAGE_NOT_USER; return pte; }
+static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) |= _PAGE_CLEAN; return pte; }
+static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) |= _PAGE_OLD; return pte; }
+
+static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) &= ~_PAGE_READONLY; return pte; }
+static inline pte_t pte_mkread(pte_t pte) { pte_val(pte) &= ~_PAGE_NOT_USER; return pte; }
+static inline pte_t pte_mkexec(pte_t pte) { pte_val(pte) &= ~_PAGE_NOT_USER; return pte; }
+static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) &= ~_PAGE_CLEAN; return pte; }
+static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) &= ~_PAGE_OLD; return pte; }
#define pte_alloc_kernel pte_alloc
Index: ptrace.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/proc-armo/ptrace.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- ptrace.h 14 Jan 2001 16:58:42 -0000 1.1.1.1
+++ ptrace.h 9 Apr 2002 12:33:10 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/proc-armo/ptrace.h
*
- * Copyright (C) 1996-1999 Russell King
+ * Copyright (C) 1996-2001 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -14,6 +14,10 @@
#define FIQ26_MODE 0x01
#define IRQ26_MODE 0x02
#define SVC26_MODE 0x03
+#define USR_MODE USR26_MODE
+#define FIQ_MODE FIQ26_MODE
+#define IRQ_MODE IRQ26_MODE
+#define SVC_MODE SVC26_MODE
#define MODE_MASK 0x03
#define F_BIT (1 << 26)
#define I_BIT (1 << 27)
Index: system.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/proc-armo/system.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- system.h 14 Jan 2001 16:58:42 -0000 1.1.1.1
+++ system.h 9 Apr 2002 12:33:10 -0000 1.2
@@ -12,7 +12,9 @@
#include <asm/proc-fns.h>
-extern __inline__ unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
+#define vectors_base() (0)
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
{
extern void __bad_xchg(volatile void *, int);
Index: uaccess.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/proc-armo/uaccess.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- uaccess.h 14 Jan 2001 16:58:43 -0000 1.1.1.1
+++ uaccess.h 9 Apr 2002 12:33:10 -0000 1.2
@@ -25,7 +25,7 @@
extern uaccess_t uaccess_user, uaccess_kernel;
-extern __inline__ void set_fs (mm_segment_t fs)
+static inline void set_fs (mm_segment_t fs)
{
current->addr_limit = fs;
current->thread.uaccess = fs == USER_DS ? &uaccess_user : &uaccess_kernel;
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/hardware In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/hardware Modified Files: ioc.h iomd.h pci_v3.h serial_amba.h Added Files: amba_kmi.h clps7111.h ep7211.h ep7212.h Log Message: Synch to 2.4.15 commit 1 --- NEW FILE --- /* * linux/include/asm-arm/hardware/amba_kmi.h * * Internal header file for AMBA KMI ports * * Copyright (C) 2000 Deep Blue Solutions Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * * * --------------------------------------------------------------------------- * From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical * Reference Manual - ARM DDI 0143B - see http://www.arm.com/ * --------------------------------------------------------------------------- */ #ifndef ASM_ARM_HARDWARE_AMBA_KMI_H #define ASM_ARM_HARDWARE_AMBA_KMI_H /* * KMI control register: * KMICR_TYPE 0 = PS2/AT mode, 1 = No line control bit mode * KMICR_RXINTREN 1 = enable RX interrupts * KMICR_TXINTREN 1 = enable TX interrupts * KMICR_EN 1 = enable KMI * KMICR_FD 1 = force KMI data low * KMICR_FC 1 = force KMI clock low */ #define KMICR (KMI_BASE + 0x00) #define KMICR_TYPE (1 << 5) #define KMICR_RXINTREN (1 << 4) #define KMICR_TXINTREN (1 << 3) #define KMICR_EN (1 << 2) #define KMICR_FD (1 << 1) #define KMICR_FC (1 << 0) /* * KMI status register: * KMISTAT_TXEMPTY 1 = transmitter register empty * KMISTAT_TXBUSY 1 = currently sending data * KMISTAT_RXFULL 1 = receiver register ready to be read * KMISTAT_RXBUSY 1 = currently receiving data * KMISTAT_RXPARITY parity of last databyte received * KMISTAT_IC current level of KMI clock input * KMISTAT_ID current level of KMI data input */ #define KMISTAT (KMI_BASE + 0x04) #define KMISTAT_TXEMPTY (1 << 6) #define KMISTAT_TXBUSY (1 << 5) #define KMISTAT_RXFULL (1 << 4) #define KMISTAT_RXBUSY (1 << 3) #define KMISTAT_RXPARITY (1 << 2) #define KMISTAT_IC (1 << 1) #define KMISTAT_ID (1 << 0) /* * KMI data register */ #define KMIDATA (KMI_BASE + 0x08) /* * KMI clock divisor: to generate 8MHz internal clock * div = (ref / 8MHz) - 1; 0 <= div <= 15 */ #define KMICLKDIV (KMI_BASE + 0x0c) /* * KMI interrupt register: * KMIIR_TXINTR 1 = transmit interrupt asserted * KMIIR_RXINTR 1 = receive interrupt asserted */ #define KMIIR (KMI_BASE + 0x10) #define KMIIR_TXINTR (1 << 1) #define KMIIR_RXINTR (1 << 0) /* * The size of the KMI primecell */ #define KMI_SIZE (0x100) #endif --- NEW FILE --- /* * linux/include/asm-arm/hardware/clps7111.h * * This file contains the hardware definitions of the CLPS7111 internal * registers. * * Copyright (C) 2000 Deep Blue Solutions Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_HARDWARE_CLPS7111_H #define __ASM_HARDWARE_CLPS7111_H #define CLPS7111_PHYS_BASE (0x80000000) #ifndef __ASSEMBLY__ #define clps_readb(off) __raw_readb(CLPS7111_BASE + (off)) #define clps_readl(off) __raw_readl(CLPS7111_BASE + (off)) #define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off)) #define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off)) #endif #define PADR (0x0000) #define PBDR (0x0001) #define PDDR (0x0003) #define PADDR (0x0040) #define PBDDR (0x0041) #define PDDDR (0x0043) #define PEDR (0x0080) #define PEDDR (0x00c0) #define SYSCON1 (0x0100) #define SYSFLG1 (0x0140) #define MEMCFG1 (0x0180) #define MEMCFG2 (0x01c0) #define DRFPR (0x0200) #define INTSR1 (0x0240) #define INTMR1 (0x0280) #define LCDCON (0x02c0) #define TC2D (0x0340) #define RTCDR (0x0380) #define RTCMR (0x03c0) #define PMPCON (0x0400) #define CODR (0x0440) #define UARTDR1 (0x0480) #define UBRLCR1 (0x04c0) #define SYNCIO (0x0500) #define PALLSW (0x0540) #define PALMSW (0x0580) #define STFCLR (0x05c0) #define BLEOI (0x0600) #define MCEOI (0x0640) #define TEOI (0x0680) #define TC1EOI (0x06c0) #define TC2EOI (0x0700) #define RTCEOI (0x0740) #define UMSEOI (0x0780) #define COEOI (0x07c0) #define HALT (0x0800) #define STDBY (0x0840) #define FBADDR (0x1000) #define SYSCON2 (0x1100) #define SYSFLG2 (0x1140) #define INTSR2 (0x1240) #define INTMR2 (0x1280) #define UARTDR2 (0x1480) #define UBRLCR2 (0x14c0) #define SS2DR (0x1500) #define SRXEOF (0x1600) #define SS2POP (0x16c0) #define KBDEOI (0x1700) /* common bits: SYSCON1 / SYSCON2 */ #define SYSCON_UARTEN (1 << 8) #define SYSCON1_KBDSCAN(x) ((x) & 15) #define SYSCON1_KBDSCANMASK (15) #define SYSCON1_TC1M (1 << 4) #define SYSCON1_TC1S (1 << 5) #define SYSCON1_TC2M (1 << 6) #define SYSCON1_TC2S (1 << 7) #define SYSCON1_UART1EN SYSCON_UARTEN #define SYSCON1_BZTOG (1 << 9) #define SYSCON1_BZMOD (1 << 10) #define SYSCON1_DBGEN (1 << 11) #define SYSCON1_LCDEN (1 << 12) #define SYSCON1_CDENTX (1 << 13) #define SYSCON1_CDENRX (1 << 14) #define SYSCON1_SIREN (1 << 15) #define SYSCON1_ADCKSEL(x) (((x) & 3) << 16) #define SYSCON1_ADCKSEL_MASK (3 << 16) #define SYSCON1_EXCKEN (1 << 18) #define SYSCON1_WAKEDIS (1 << 19) #define SYSCON1_IRTXM (1 << 20) /* common bits: SYSFLG1 / SYSFLG2 */ #define SYSFLG_UBUSY (1 << 11) #define SYSFLG_URXFE (1 << 22) #define SYSFLG_UTXFF (1 << 23) #define SYSFLG1_MCDR (1 << 0) #define SYSFLG1_DCDET (1 << 1) #define SYSFLG1_WUDR (1 << 2) #define SYSFLG1_WUON (1 << 3) #define SYSFLG1_CTS (1 << 8) #define SYSFLG1_DSR (1 << 9) #define SYSFLG1_DCD (1 << 10) #define SYSFLG1_UBUSY SYSFLG_UBUSY #define SYSFLG1_NBFLG (1 << 12) #define SYSFLG1_RSTFLG (1 << 13) #define SYSFLG1_PFFLG (1 << 14) #define SYSFLG1_CLDFLG (1 << 15) #define SYSFLG1_URXFE SYSFLG_URXFE #define SYSFLG1_UTXFF SYSFLG_UTXFF #define SYSFLG1_CRXFE (1 << 24) #define SYSFLG1_CTXFF (1 << 25) #define SYSFLG1_SSIBUSY (1 << 26) #define SYSFLG1_ID (1 << 29) #define SYSFLG2_SSRXOF (1 << 0) #define SYSFLG2_RESVAL (1 << 1) #define SYSFLG2_RESFRM (1 << 2) #define SYSFLG2_SS2RXFE (1 << 3) #define SYSFLG2_SS2TXFF (1 << 4) #define SYSFLG2_SS2TXUF (1 << 5) #define SYSFLG2_CKMODE (1 << 6) #define SYSFLG2_UBUSY SYSFLG_UBUSY #define SYSFLG2_URXFE SYSFLG_URXFE #define SYSFLG2_UTXFF SYSFLG_UTXFF #define LCDCON_GSEN (1 << 30) #define LCDCON_GSMD (1 << 31) #define SYSCON2_SERSEL (1 << 0) #define SYSCON2_KBD6 (1 << 1) #define SYSCON2_DRAMZ (1 << 2) #define SYSCON2_KBWEN (1 << 3) #define SYSCON2_SS2TXEN (1 << 4) #define SYSCON2_PCCARD1 (1 << 5) #define SYSCON2_PCCARD2 (1 << 6) #define SYSCON2_SS2RXEN (1 << 7) #define SYSCON2_UART2EN SYSCON_UARTEN #define SYSCON2_SS2MAEN (1 << 9) #define SYSCON2_OSTB (1 << 12) #define SYSCON2_CLKENSL (1 << 13) #define SYSCON2_BUZFREQ (1 << 14) /* common bits: UARTDR1 / UARTDR2 */ #define UARTDR_FRMERR (1 << 8) #define UARTDR_PARERR (1 << 9) #define UARTDR_OVERR (1 << 10) /* common bits: UBRLCR1 / UBRLCR2 */ #define UBRLCR_BAUD_MASK ((1 << 12) - 1) #define UBRLCR_BREAK (1 << 12) #define UBRLCR_PRTEN (1 << 13) #define UBRLCR_EVENPRT (1 << 14) #define UBRLCR_XSTOP (1 << 15) #define UBRLCR_FIFOEN (1 << 16) #define UBRLCR_WRDLEN5 (0 << 17) #define UBRLCR_WRDLEN6 (1 << 17) #define UBRLCR_WRDLEN7 (2 << 17) #define UBRLCR_WRDLEN8 (3 << 17) #define UBRLCR_WRDLEN_MASK (3 << 17) #define SYNCIO_SMCKEN (1 << 13) #define SYNCIO_TXFRMEN (1 << 14) #endif /* __ASM_HARDWARE_CLPS7111_H */ --- NEW FILE --- /* * linux/include/asm-arm/hardware/ep7211.h * * This file contains the hardware definitions of the EP7211 internal * registers. * * Copyright (C) 2001 Blue Mug, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_HARDWARE_EP7211_H #define __ASM_HARDWARE_EP7211_H #include <asm/hardware/clps7111.h> /* * define EP7211_BASE to be the base address of the region * you want to access. */ #define EP7211_PHYS_BASE (0x80000000) /* * XXX mi...@bl...: need to introduce EP7211 registers (those not * present in 7212) here. */ #endif /* __ASM_HARDWARE_EP7211_H */ --- NEW FILE --- /* * linux/include/asm-arm/hardware/ep7212.h * * This file contains the hardware definitions of the EP7212 internal * registers. * * Copyright (C) 2000 Deep Blue Solutions Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __ASM_HARDWARE_EP7212_H #define __ASM_HARDWARE_EP7212_H #include <linux/config.h> /* * define EP7212_BASE to be the base address of the region * you want to access. */ #define EP7212_PHYS_BASE (0x80000000) #ifndef __ASSEMBLY__ #define ep_readl(off) __raw_readl(EP7212_BASE + (off)) #define ep_writel(val,off) __raw_writel(val, EP7212_BASE + (off)) #endif /* * These registers are specific to the EP7212 only */ #define DAIR 0x2000 #define DAIR0 0x2040 #define DAIDR1 0x2080 #define DAIDR2 0x20c0 #define DAISR 0x2100 #define SYSCON3 0x2200 #define INTSR3 0x2240 #define INTMR3 0x2280 #define LEDFLSH 0x22c0 #if defined (CONFIG_ARCH_CDB89712) #define SDCONF 0x2300 #define SDRFPR 0x2340 #endif #define DAIR_DAIEN (1 << 16) #define DAIR_ECS (1 << 17) #define DAIR_LCTM (1 << 19) #define DAIR_LCRM (1 << 20) #define DAIR_RCTM (1 << 21) #define DAIR_RCRM (1 << 22) #define DAIR_LBM (1 << 23) #define DAIDR2_FIFOEN (1 << 15) #define DAIDR2_FIFOLEFT (0x0d << 16) #define DAIDR2_FIFORIGHT (0x11 << 16) #define DAISR_RCTS (1 << 0) #define DAISR_RCRS (1 << 1) #define DAISR_LCTS (1 << 2) #define DAISR_LCRS (1 << 3) #define DAISR_RCTU (1 << 4) #define DAISR_RCRO (1 << 5) #define DAISR_LCTU (1 << 6) #define DAISR_LCRO (1 << 7) #define DAISR_RCNF (1 << 8) #define DAISR_RCNE (1 << 9) #define DAISR_LCNF (1 << 10) #define DAISR_LCNE (1 << 11) #define DAISR_FIFO (1 << 12) #define SYSCON3_ADCCON (1 << 0) #define SYSCON3_DAISEL (1 << 3) #define SYSCON3_ADCCKNSEN (1 << 4) #define SYSCON3_FASTWAKE (1 << 8) #define SYSCON3_DAIEN (1 << 9) #if defined (CONFIG_ARCH_CDB89712) #define SDCONF_ACTIVE (1 << 10) #define SDCONF_CLKCTL (1 << 9) #define SDCONF_WIDTH_4 (0 << 7) #define SDCONF_WIDTH_8 (1 << 7) #define SDCONF_WIDTH_16 (2 << 7) #define SDCONF_WIDTH_32 (3 << 7) #define SDCONF_SIZE_16 (0 << 5) #define SDCONF_SIZE_64 (1 << 5) #define SDCONF_SIZE_128 (2 << 5) #define SDCONF_SIZE_256 (3 << 5) #define SDCONF_CASLAT_2 (2) #define SDCONF_CASLAT_3 (3) #endif #endif /* __ASM_HARDWARE_EP7212_H */ Index: ioc.h =================================================================== RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/hardware/ioc.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- ioc.h 14 Jan 2001 16:58:49 -0000 1.1.1.1 +++ ioc.h 9 Apr 2002 12:33:10 -0000 1.2 @@ -10,58 +10,63 @@ * Use these macros to read/write the IOC. All it does is perform the actual * read/write. */ - -#ifndef IOC_CONTROL +#ifndef __ASMARM_HARDWARE_IOC_H +#define __ASMARM_HARDWARE_IOC_H #ifndef __ASSEMBLY__ -#define __IOC(offset) (IOC_BASE + (offset >> 2)) -#else -#define __IOC(offset) offset + +/* + * We use __raw_base variants here so that we give the compiler the + * chance to keep IOC_BASE in a register. + */ +#define ioc_readb(off) __raw_base_readb(IOC_BASE, (off)) +#define ioc_writeb(val,off) __raw_base_writeb(val, IOC_BASE, (off)) + #endif -#define IOC_CONTROL __IOC(0x00) -#define IOC_KARTTX __IOC(0x04) -#define IOC_KARTRX __IOC(0x04) - -#define IOC_IRQSTATA __IOC(0x10) -#define IOC_IRQREQA __IOC(0x14) -#define IOC_IRQCLRA __IOC(0x14) -#define IOC_IRQMASKA __IOC(0x18) - -#define IOC_IRQSTATB __IOC(0x20) -#define IOC_IRQREQB __IOC(0x24) -#define IOC_IRQMASKB __IOC(0x28) - -#define IOC_FIQSTAT __IOC(0x30) -#define IOC_FIQREQ __IOC(0x34) -#define IOC_FIQMASK __IOC(0x38) - -#define IOC_T0CNTL __IOC(0x40) -#define IOC_T0LTCHL __IOC(0x40) -#define IOC_T0CNTH __IOC(0x44) -#define IOC_T0LTCHH __IOC(0x44) -#define IOC_T0GO __IOC(0x48) -#define IOC_T0LATCH __IOC(0x4c) - -#define IOC_T1CNTL __IOC(0x50) -#define IOC_T1LTCHL __IOC(0x50) -#define IOC_T1CNTH __IOC(0x54) -#define IOC_T1LTCHH __IOC(0x54) -#define IOC_T1GO __IOC(0x58) -#define IOC_T1LATCH __IOC(0x5c) - -#define IOC_T2CNTL __IOC(0x60) -#define IOC_T2LTCHL __IOC(0x60) -#define IOC_T2CNTH __IOC(0x64) -#define IOC_T2LTCHH __IOC(0x64) -#define IOC_T2GO __IOC(0x68) -#define IOC_T2LATCH __IOC(0x6c) - -#define IOC_T3CNTL __IOC(0x70) -#define IOC_T3LTCHL __IOC(0x70) -#define IOC_T3CNTH __IOC(0x74) -#define IOC_T3LTCHH __IOC(0x74) -#define IOC_T3GO __IOC(0x78) -#define IOC_T3LATCH __IOC(0x7c) +#define IOC_CONTROL (0x00) +#define IOC_KARTTX (0x04) +#define IOC_KARTRX (0x04) + +#define IOC_IRQSTATA (0x10) +#define IOC_IRQREQA (0x14) +#define IOC_IRQCLRA (0x14) +#define IOC_IRQMASKA (0x18) + +#define IOC_IRQSTATB (0x20) +#define IOC_IRQREQB (0x24) +#define IOC_IRQMASKB (0x28) + +#define IOC_FIQSTAT (0x30) +#define IOC_FIQREQ (0x34) +#define IOC_FIQMASK (0x38) + +#define IOC_T0CNTL (0x40) +#define IOC_T0LTCHL (0x40) +#define IOC_T0CNTH (0x44) +#define IOC_T0LTCHH (0x44) +#define IOC_T0GO (0x48) +#define IOC_T0LATCH (0x4c) + +#define IOC_T1CNTL (0x50) +#define IOC_T1LTCHL (0x50) +#define IOC_T1CNTH (0x54) +#define IOC_T1LTCHH (0x54) +#define IOC_T1GO (0x58) +#define IOC_T1LATCH (0x5c) + +#define IOC_T2CNTL (0x60) +#define IOC_T2LTCHL (0x60) +#define IOC_T2CNTH (0x64) +#define IOC_T2LTCHH (0x64) +#define IOC_T2GO (0x68) +#define IOC_T2LATCH (0x6c) + +#define IOC_T3CNTL (0x70) +#define IOC_T3LTCHL (0x70) +#define IOC_T3CNTH (0x74) +#define IOC_T3LTCHH (0x74) +#define IOC_T3GO (0x78) +#define IOC_T3LATCH (0x7c) #endif Index: iomd.h =================================================================== RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/hardware/iomd.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- iomd.h 14 Jan 2001 16:58:49 -0000 1.1.1.1 +++ iomd.h 9 Apr 2002 12:33:10 -0000 1.2 @@ -1,5 +1,5 @@ /* - * linux/include/asm-arm/iomd.h + * linux/include/asm-arm/hardware/iomd.h * * Copyright (C) 1999 Russell King * @@ -10,111 +10,121 @@ * This file contains information out the IOMD ASIC used in the * Acorn RiscPC and subsequently integrated into the CLPS7500 chips. */ +#ifndef __ASMARM_HARDWARE_IOMD_H +#define __ASMARM_HARDWARE_IOMD_H + #include <linux/config.h> #ifndef __ASSEMBLY__ -#define __IOMD(offset) (IO_IOMD_BASE + (offset >> 2)) -#else -#define __IOMD(offset) offset + +/* + * We use __raw_base variants here so that we give the compiler the + * chance to keep IOC_BASE in a register. + */ +#define iomd_readb(off) __raw_base_readb(IOMD_BASE, (off)) +#define iomd_readl(off) __raw_base_readl(IOMD_BASE, (off)) +#define iomd_writeb(val,off) __raw_base_writeb(val, IOMD_BASE, (off)) +#define iomd_writel(val,off) __raw_base_writel(val, IOMD_BASE, (off)) + #endif -#define IOMD_CONTROL __IOMD(0x000) -#define IOMD_KARTTX __IOMD(0x004) -#define IOMD_KARTRX __IOMD(0x004) -#define IOMD_KCTRL __IOMD(0x008) +#define IOMD_CONTROL (0x000) +#define IOMD_KARTTX (0x004) +#define IOMD_KARTRX (0x004) +#define IOMD_KCTRL (0x008) #ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_IOLINES __IOMD(0x00C) +#define IOMD_IOLINES (0x00C) #endif -#define IOMD_IRQSTATA __IOMD(0x010) -#define IOMD_IRQREQA __IOMD(0x014) -#define IOMD_IRQCLRA __IOMD(0x014) -#define IOMD_IRQMASKA __IOMD(0x018) +#define IOMD_IRQSTATA (0x010) +#define IOMD_IRQREQA (0x014) +#define IOMD_IRQCLRA (0x014) +#define IOMD_IRQMASKA (0x018) #ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_SUSMODE __IOMD(0x01C) +#define IOMD_SUSMODE (0x01C) #endif -#define IOMD_IRQSTATB __IOMD(0x020) -#define IOMD_IRQREQB __IOMD(0x024) -#define IOMD_IRQMASKB __IOMD(0x028) +#define IOMD_IRQSTATB (0x020) +#define IOMD_IRQREQB (0x024) +#define IOMD_IRQMASKB (0x028) -#define IOMD_FIQSTAT __IOMD(0x030) -#define IOMD_FIQREQ __IOMD(0x034) -#define IOMD_FIQMASK __IOMD(0x038) +#define IOMD_FIQSTAT (0x030) +#define IOMD_FIQREQ (0x034) +#define IOMD_FIQMASK (0x038) #ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_CLKCTL __IOMD(0x03C) +#define IOMD_CLKCTL (0x03C) #endif -#define IOMD_T0CNTL __IOMD(0x040) -#define IOMD_T0LTCHL __IOMD(0x040) -#define IOMD_T0CNTH __IOMD(0x044) -#define IOMD_T0LTCHH __IOMD(0x044) -#define IOMD_T0GO __IOMD(0x048) -#define IOMD_T0LATCH __IOMD(0x04c) +#define IOMD_T0CNTL (0x040) +#define IOMD_T0LTCHL (0x040) +#define IOMD_T0CNTH (0x044) +#define IOMD_T0LTCHH (0x044) +#define IOMD_T0GO (0x048) +#define IOMD_T0LATCH (0x04c) -#define IOMD_T1CNTL __IOMD(0x050) -#define IOMD_T1LTCHL __IOMD(0x050) -#define IOMD_T1CNTH __IOMD(0x054) -#define IOMD_T1LTCHH __IOMD(0x054) -#define IOMD_T1GO __IOMD(0x058) -#define IOMD_T1LATCH __IOMD(0x05c) +#define IOMD_T1CNTL (0x050) +#define IOMD_T1LTCHL (0x050) +#define IOMD_T1CNTH (0x054) +#define IOMD_T1LTCHH (0x054) +#define IOMD_T1GO (0x058) +#define IOMD_T1LATCH (0x05c) #ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_IRQSTATC __IOMD(0x060) -#define IOMD_IRQREQC __IOMD(0x064) -#define IOMD_IRQMASKC __IOMD(0x068) +#define IOMD_IRQSTATC (0x060) +#define IOMD_IRQREQC (0x064) +#define IOMD_IRQMASKC (0x068) -#define IOMD_VIDMUX __IOMD(0x06c) +#define IOMD_VIDMUX (0x06c) -#define IOMD_IRQSTATD __IOMD(0x070) -#define IOMD_IRQREQD __IOMD(0x074) -#define IOMD_IRQMASKD __IOMD(0x078) +#define IOMD_IRQSTATD (0x070) +#define IOMD_IRQREQD (0x074) +#define IOMD_IRQMASKD (0x078) #endif -#define IOMD_ROMCR0 __IOMD(0x080) -#define IOMD_ROMCR1 __IOMD(0x084) +#define IOMD_ROMCR0 (0x080) +#define IOMD_ROMCR1 (0x084) #ifdef CONFIG_ARCH_RPC -#define IOMD_DRAMCR __IOMD(0x088) +#define IOMD_DRAMCR (0x088) #endif -#define IOMD_REFCR __IOMD(0x08C) +#define IOMD_REFCR (0x08C) -#define IOMD_FSIZE __IOMD(0x090) -#define IOMD_ID0 __IOMD(0x094) -#define IOMD_ID1 __IOMD(0x098) -#define IOMD_VERSION __IOMD(0x09C) +#define IOMD_FSIZE (0x090) +#define IOMD_ID0 (0x094) +#define IOMD_ID1 (0x098) +#define IOMD_VERSION (0x09C) #ifdef CONFIG_ARCH_RPC -#define IOMD_MOUSEX __IOMD(0x0A0) -#define IOMD_MOUSEY __IOMD(0x0A4) +#define IOMD_MOUSEX (0x0A0) +#define IOMD_MOUSEY (0x0A4) #endif #ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_MSEDAT __IOMD(0x0A8) -#define IOMD_MSECTL __IOMD(0x0Ac) +#define IOMD_MSEDAT (0x0A8) +#define IOMD_MSECTL (0x0Ac) #endif #ifdef CONFIG_ARCH_RPC -#define IOMD_DMATCR __IOMD(0x0C0) +#define IOMD_DMATCR (0x0C0) #endif -#define IOMD_IOTCR __IOMD(0x0C4) -#define IOMD_ECTCR __IOMD(0x0C8) +#define IOMD_IOTCR (0x0C4) +#define IOMD_ECTCR (0x0C8) #ifdef CONFIG_ARCH_RPC -#define IOMD_DMAEXT __IOMD(0x0CC) +#define IOMD_DMAEXT (0x0CC) #endif #ifdef CONFIG_ARCH_CLPS7500 -#define IOMD_ASTCR __IOMD(0x0CC) -#define IOMD_DRAMCR __IOMD(0x0D0) -#define IOMD_SELFREF __IOMD(0x0D4) -#define IOMD_ATODICR __IOMD(0x0E0) -#define IOMD_ATODSR __IOMD(0x0E4) -#define IOMD_ATODCC __IOMD(0x0E8) -#define IOMD_ATODCNT1 __IOMD(0x0EC) -#define IOMD_ATODCNT2 __IOMD(0x0F0) -#define IOMD_ATODCNT3 __IOMD(0x0F4) -#define IOMD_ATODCNT4 __IOMD(0x0F8) +#define IOMD_ASTCR (0x0CC) +#define IOMD_DRAMCR (0x0D0) +#define IOMD_SELFREF (0x0D4) +#define IOMD_ATODICR (0x0E0) +#define IOMD_ATODSR (0x0E4) +#define IOMD_ATODCC (0x0E8) +#define IOMD_ATODCNT1 (0x0EC) +#define IOMD_ATODCNT2 (0x0F0) +#define IOMD_ATODCNT3 (0x0F4) +#define IOMD_ATODCNT4 (0x0F8) #endif #ifdef CONFIG_ARCH_RPC @@ -123,63 +133,63 @@ #define DMA_EXT_IO2 4 #define DMA_EXT_IO3 8 -#define IOMD_IO0CURA __IOMD(0x100) -#define IOMD_IO0ENDA __IOMD(0x104) -#define IOMD_IO0CURB __IOMD(0x108) -#define IOMD_IO0ENDB __IOMD(0x10C) -#define IOMD_IO0CR __IOMD(0x110) -#define IOMD_IO0ST __IOMD(0x114) - -#define IOMD_IO1CURA __IOMD(0x120) -#define IOMD_IO1ENDA __IOMD(0x124) -#define IOMD_IO1CURB __IOMD(0x128) -#define IOMD_IO1ENDB __IOMD(0x12C) -#define IOMD_IO1CR __IOMD(0x130) -#define IOMD_IO1ST __IOMD(0x134) - -#define IOMD_IO2CURA __IOMD(0x140) -#define IOMD_IO2ENDA __IOMD(0x144) -#define IOMD_IO2CURB __IOMD(0x148) -#define IOMD_IO2ENDB __IOMD(0x14C) -#define IOMD_IO2CR __IOMD(0x150) -#define IOMD_IO2ST __IOMD(0x154) - -#define IOMD_IO3CURA __IOMD(0x160) -#define IOMD_IO3ENDA __IOMD(0x164) -#define IOMD_IO3CURB __IOMD(0x168) -#define IOMD_IO3ENDB __IOMD(0x16C) -#define IOMD_IO3CR __IOMD(0x170) -#define IOMD_IO3ST __IOMD(0x174) -#endif - -#define IOMD_SD0CURA __IOMD(0x180) -#define IOMD_SD0ENDA __IOMD(0x184) -#define IOMD_SD0CURB __IOMD(0x188) -#define IOMD_SD0ENDB __IOMD(0x18C) -#define IOMD_SD0CR __IOMD(0x190) -#define IOMD_SD0ST __IOMD(0x194) - -#ifdef CONFIG_ARCH_RPC -#define IOMD_SD1CURA __IOMD(0x1A0) -#define IOMD_SD1ENDA __IOMD(0x1A4) -#define IOMD_SD1CURB __IOMD(0x1A8) -#define IOMD_SD1ENDB __IOMD(0x1AC) -#define IOMD_SD1CR __IOMD(0x1B0) -#define IOMD_SD1ST __IOMD(0x1B4) -#endif - -#define IOMD_CURSCUR __IOMD(0x1C0) -#define IOMD_CURSINIT __IOMD(0x1C4) - -#define IOMD_VIDCUR __IOMD(0x1D0) -#define IOMD_VIDEND __IOMD(0x1D4) -#define IOMD_VIDSTART __IOMD(0x1D8) -#define IOMD_VIDINIT __IOMD(0x1DC) -#define IOMD_VIDCR __IOMD(0x1E0) - -#define IOMD_DMASTAT __IOMD(0x1F0) -#define IOMD_DMAREQ __IOMD(0x1F4) -#define IOMD_DMAMASK __IOMD(0x1F8) +#define IOMD_IO0CURA (0x100) +#define IOMD_IO0ENDA (0x104) +#define IOMD_IO0CURB (0x108) +#define IOMD_IO0ENDB (0x10C) +#define IOMD_IO0CR (0x110) +#define IOMD_IO0ST (0x114) + +#define IOMD_IO1CURA (0x120) +#define IOMD_IO1ENDA (0x124) +#define IOMD_IO1CURB (0x128) +#define IOMD_IO1ENDB (0x12C) +#define IOMD_IO1CR (0x130) +#define IOMD_IO1ST (0x134) + +#define IOMD_IO2CURA (0x140) +#define IOMD_IO2ENDA (0x144) +#define IOMD_IO2CURB (0x148) +#define IOMD_IO2ENDB (0x14C) +#define IOMD_IO2CR (0x150) +#define IOMD_IO2ST (0x154) + +#define IOMD_IO3CURA (0x160) +#define IOMD_IO3ENDA (0x164) +#define IOMD_IO3CURB (0x168) +#define IOMD_IO3ENDB (0x16C) +#define IOMD_IO3CR (0x170) +#define IOMD_IO3ST (0x174) +#endif + +#define IOMD_SD0CURA (0x180) +#define IOMD_SD0ENDA (0x184) +#define IOMD_SD0CURB (0x188) +#define IOMD_SD0ENDB (0x18C) +#define IOMD_SD0CR (0x190) +#define IOMD_SD0ST (0x194) + +#ifdef CONFIG_ARCH_RPC +#define IOMD_SD1CURA (0x1A0) +#define IOMD_SD1ENDA (0x1A4) +#define IOMD_SD1CURB (0x1A8) +#define IOMD_SD1ENDB (0x1AC) +#define IOMD_SD1CR (0x1B0) +#define IOMD_SD1ST (0x1B4) +#endif + +#define IOMD_CURSCUR (0x1C0) +#define IOMD_CURSINIT (0x1C4) + +#define IOMD_VIDCUR (0x1D0) +#define IOMD_VIDEND (0x1D4) +#define IOMD_VIDSTART (0x1D8) +#define IOMD_VIDINIT (0x1DC) +#define IOMD_VIDCR (0x1E0) + +#define IOMD_DMASTAT (0x1F0) +#define IOMD_DMAREQ (0x1F4) +#define IOMD_DMAMASK (0x1F8) #define DMA_END_S (1 << 31) #define DMA_END_L (1 << 30) @@ -192,39 +202,6 @@ #define DMA_ST_INT 2 #define DMA_ST_AB 1 -#ifndef IOC_CONTROL -/* - * IOC compatability - */ -#define IOC_CONTROL IOMD_CONTROL -#define IOC_IRQSTATA IOMD_IRQSTATA -#define IOC_IRQREQA IOMD_IRQREQA -#define IOC_IRQCLRA IOMD_IRQCLRA -#define IOC_IRQMASKA IOMD_IRQMASKA - -#define IOC_IRQSTATB IOMD_IRQSTATB -#define IOC_IRQREQB IOMD_IRQREQB -#define IOC_IRQMASKB IOMD_IRQMASKB - -#define IOC_FIQSTAT IOMD_FIQSTAT -#define IOC_FIQREQ IOMD_FIQREQ -#define IOC_FIQMASK IOMD_FIQMASK - -#define IOC_T0CNTL IOMD_T0CNTL -#define IOC_T0LTCHL IOMD_T0LTCHL -#define IOC_T0CNTH IOMD_T0CNTH -#define IOC_T0LTCHH IOMD_T0LTCHH -#define IOC_T0GO IOMD_T0GO -#define IOC_T0LATCH IOMD_T0LATCH - -#define IOC_T1CNTL IOMD_T1CNTL -#define IOC_T1LTCHL IOMD_T1LTCHL -#define IOC_T1CNTH IOMD_T1CNTH -#define IOC_T1LTCHH IOMD_T1LTCHH -#define IOC_T1GO IOMD_T1GO -#define IOC_T1LATCH IOMD_T1LATCH -#endif - /* * DMA (MEMC) compatability */ @@ -247,3 +224,4 @@ } while (0) #endif +#endif Index: pci_v3.h =================================================================== RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/hardware/pci_v3.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- pci_v3.h 14 Jan 2001 16:58:50 -0000 1.1.1.1 +++ pci_v3.h 9 Apr 2002 12:33:10 -0000 1.2 @@ -4,7 +4,7 @@ * Internal header file PCI V3 chip * * Copyright (C) ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd. + * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -88,61 +88,99 @@ /* PCI COMMAND REGISTER bits */ -#define V3_COMMAND_M_FBB_EN BIT9 -#define V3_COMMAND_M_SERR_EN BIT8 -#define V3_COMMAND_M_PAR_EN BIT6 -#define V3_COMMAND_M_MASTER_EN BIT2 -#define V3_COMMAND_M_MEM_EN BIT1 -#define V3_COMMAND_M_IO_EN BIT0 +#define V3_COMMAND_M_FBB_EN (1 << 9) +#define V3_COMMAND_M_SERR_EN (1 << 8) +#define V3_COMMAND_M_PAR_EN (1 << 6) +#define V3_COMMAND_M_MASTER_EN (1 << 2) +#define V3_COMMAND_M_MEM_EN (1 << 1) +#define V3_COMMAND_M_IO_EN (1 << 0) /* SYSTEM REGISTER bits */ -#define V3_SYSTEM_M_RST_OUT BIT15 -#define V3_SYSTEM_M_LOCK BIT14 +#define V3_SYSTEM_M_RST_OUT (1 << 15) +#define V3_SYSTEM_M_LOCK (1 << 14) /* PCI_CFG bits */ -#define V3_PCI_CFG_M_RETRY_EN BIT10 -#define V3_PCI_CFG_M_AD_LOW1 BIT9 -#define V3_PCI_CFG_M_AD_LOW0 BIT8 +#define V3_PCI_CFG_M_I2O_EN (1 << 15) +#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) +#define V3_PCI_CFG_M_IO_DIS (1 << 13) +#define V3_PCI_CFG_M_EN3V (1 << 12) +#define V3_PCI_CFG_M_RETRY_EN (1 << 10) +#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) +#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) /* PCI_BASE register bits (PCI -> Local Bus) */ #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 -#define V3_PCI_BASE_M_PREFETCH BIT3 -#define V3_PCI_BASE_M_TYPE BIT2+BIT1 -#define V3_PCI_BASE_M_IO BIT0 +#define V3_PCI_BASE_M_PREFETCH (1 << 3) +#define V3_PCI_BASE_M_TYPE (3 << 1) +#define V3_PCI_BASE_M_IO (1 << 0) /* PCI MAP register bits (PCI -> Local bus) */ #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH BIT15 -#define V3_PCI_MAP_M_ROM_SIZE BIT11+BIT10 -#define V3_PCI_MAP_M_SWAP BIT9+BIT8 +#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) +#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) +#define V3_PCI_MAP_M_SWAP (3 << 8) #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN BIT1 -#define V3_PCI_MAP_M_ENABLE BIT0 +#define V3_PCI_MAP_M_REG_EN (1 << 1) +#define V3_PCI_MAP_M_ENABLE (1 << 0) -/* 9 => 512M window size +/* + * LB_BASE0,1 register bits (Local bus -> PCI) */ -#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 -/* A => 1024M window size - */ -#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 +#define V3_LB_BASE_ADR_BASE 0xfff00000 +#define V3_LB_BASE_SWAP (3 << 8) +#define V3_LB_BASE_ADR_SIZE (15 << 4) +#define V3_LB_BASE_PREFETCH (1 << 3) +#define V3_LB_BASE_ENABLE (1 << 0) + +#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) +#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) +#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) +#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) +#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) +#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) +#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) +#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) +#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) +#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) +#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) +#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) + +#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) + +/* + * LB_MAP0,1 register bits (Local bus -> PCI) + */ +#define V3_LB_MAP_MAP_ADR 0xfff0 +#define V3_LB_MAP_TYPE (7 << 1) +#define V3_LB_MAP_AD_LOW_EN (1 << 0) + +#define V3_LB_MAP_TYPE_IACK (0 << 1) +#define V3_LB_MAP_TYPE_IO (1 << 1) +#define V3_LB_MAP_TYPE_MEM (3 << 1) +#define V3_LB_MAP_TYPE_CONFIG (5 << 1) +#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) + +#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) + +/* + * LB_BASE2 register bits (Local bus -> PCI IO) + */ +#define V3_LB_BASE2_ADR_BASE 0xff00 +#define V3_LB_BASE2_SWAP (3 << 6) +#define V3_LB_BASE2_ENABLE (1 << 0) -/* LB_BASE register bits (Local bus -> PCI) - */ -#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 -#define V3_LB_BASE_M_SWAP BIT9+BIT8 -#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 -#define V3_LB_BASE_M_PREFETCH BIT3 -#define V3_LB_BASE_M_ENABLE BIT0 +#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) -/* LB_MAP register bits (Local bus -> PCI) +/* + * LB_MAP2 register bits (Local bus -> PCI IO) */ -#define V3_LB_MAP_M_MAP_ADR 0xFFF0 -#define V3_LB_MAP_M_TYPE 0x000E -#define V3_LB_MAP_M_AD_LOW_EN BIT0 +#define V3_LB_MAP2_MAP_ADR 0xff00 + +#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) #endif Index: serial_amba.h =================================================================== RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/hardware/serial_amba.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- serial_amba.h 14 Jan 2001 16:58:51 -0000 1.1.1.1 +++ serial_amba.h 9 Apr 2002 12:33:10 -0000 1.2 @@ -88,4 +88,7 @@ #define ARM_BAUD_2400 383 #define ARM_BAUD_1200 767 +#define AMBA_UARTRSR_ANY (AMBA_UARTRSR_OE|AMBA_UARTRSR_BE|AMBA_UARTRSR_PE|AMBA_UARTRSR_FE) +#define AMBA_UARTFR_MODEM_ANY (AMBA_UARTFR_DCD|AMBA_UARTFR_DSR|AMBA_UARTFR_CTS) + #endif |
|
From: Andy P. <at...@us...> - 2002-04-09 12:34:02
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/mach
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/mach
Modified Files:
arch.h pci.h
Added Files:
amba_kmi.h serial_sa1100.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/*
* linux/include/asm-arm/mach/amba_kmi.h
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
struct kmi_info {
u_int base;
u_int irq;
u_char divisor;
u_char type;
u_char state;
u_char prev_rx;
u_char last_tx;
u_char resend_count;
u_short res;
u_char present;
wait_queue_head_t wait_q;
void (*rx)(struct kmi_info *, u_int val,
struct pt_regs *regs);
char name[8];
};
#define KMI_KEYBOARD 0
#define KMI_MOUSE 1
int register_kmi(struct kmi_info *kmi);
--- NEW FILE ---
/*
* linux/include/asm-arm/mach/serial_sa1100.h
*
* Author: Nicolas Pitre
*
* Moved to include/asm-arm/mach and changed lots, Russell King
*
* Low level machine dependent UART functions.
*/
#include <linux/config.h>
struct uart_port;
struct uart_info;
/*
* This is a temporary structure for registering these
* functions; it is intended to be discarded after boot.
*/
struct sa1100_port_fns {
void (*set_mctrl)(struct uart_port *, u_int);
int (*get_mctrl)(struct uart_port *);
void (*enable_ms)(struct uart_port *);
void (*pm)(struct uart_port *, u_int, u_int);
int (*open)(struct uart_port *, struct uart_info *);
void (*close)(struct uart_port *, struct uart_info *);
};
#if defined(CONFIG_SERIAL_SA1100) && !defined(CONFIG_SERIAL_SA1100_OLD)
void sa1100_register_uart_fns(struct sa1100_port_fns *fns);
void sa1100_register_uart(int idx, int port);
#else
#define sa1100_register_uart_fns(fns) do { } while (0)
#define sa1100_register_uart(idx,port) do { } while (0)
#endif
void sa1100_uart1_altgpio(void);
Index: arch.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/mach/arch.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- arch.h 25 Feb 2001 23:14:53 -0000 1.1.1.2
+++ arch.h 9 Apr 2002 12:33:10 -0000 1.2
@@ -12,15 +12,13 @@
* The size of struct machine_desc
* (for assembler code)
*/
-#define SIZEOF_MACHINE_DESC 56
+#define SIZEOF_MACHINE_DESC 48
#ifndef __ASSEMBLY__
extern void setup_initrd(unsigned int start, unsigned int size);
extern void setup_ramdisk(int doload, int prompt, int start, unsigned int rd_sz);
-struct tagtable;
-
struct machine_desc {
/*
* Note! The first four elements are used
@@ -29,7 +27,8 @@
unsigned int nr; /* architecture number */
unsigned int phys_ram; /* start of physical ram */
unsigned int phys_io; /* start of physical io */
- unsigned int virt_io; /* start of virtual io */
+ unsigned int io_pg_offst; /* byte offset for io
+ * page tabe entry */
const char *name; /* architecture name */
unsigned int param_offset; /* parameter page */
@@ -41,8 +40,6 @@
unsigned int reserve_lp1 :1; /* never has lp1 */
unsigned int reserve_lp2 :1; /* never has lp2 */
unsigned int soft_reboot :1; /* soft reboot */
- const struct tagtable * tagtable; /* tag table */
- int tagsize; /* tag table size */
void (*fixup)(struct machine_desc *,
struct param_struct *, char **,
struct meminfo *);
@@ -63,9 +60,9 @@
#define MAINTAINER(n)
#define BOOT_MEM(_pram,_pio,_vio) \
- phys_ram: _pram, \
- phys_io: _pio, \
- virt_io: _vio,
+ phys_ram: _pram, \
+ phys_io: _pio, \
+ io_pg_offst: ((_vio)>>18)&0xfffc,
#define BOOT_PARAMS(_params) \
param_offset: _params,
Index: pci.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/mach/pci.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- pci.h 14 Jan 2001 16:58:51 -0000 1.1.1.1
+++ pci.h 9 Apr 2002 12:33:10 -0000 1.2
@@ -7,36 +7,28 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-#define MAX_NR_BUS 2
+struct hw_pci {
+ /* Initialise the hardware */
+ void (*init)(void *);
+
+ /* Setup bus resources */
+ void (*setup_resources)(struct resource **);
-struct arm_bus_sysdata {
- /*
- * bitmask of features we can turn.
- * See PCI command register for more info.
- */
- u16 features;
- /*
- * Maximum devsel for this bus.
- */
- u16 maxdevsel;
/*
- * The maximum latency that devices on this
- * bus can withstand.
+ * This is the offset of PCI memory base registers
+ * to physical memory.
*/
- u8 max_lat;
-};
-
-struct arm_pci_sysdata {
- struct arm_bus_sysdata bus[MAX_NR_BUS];
-};
+ unsigned long mem_offset;
-struct hw_pci {
- void (*init)(struct arm_pci_sysdata *);
+ /* IRQ swizzle */
u8 (*swizzle)(struct pci_dev *dev, u8 *pin);
+
+ /* IRQ mapping */
int (*map_irq)(struct pci_dev *dev, u8 slot, u8 pin);
};
extern u8 no_swizzle(struct pci_dev *dev, u8 *pin);
+extern void __init dc21285_setup_resources(struct resource **resource);
+extern void __init dc21285_init(void *sysdata);
+extern void __init via82c505_init(void *sysdata);
-void __init dc21285_init(struct arm_pci_sysdata *);
-void __init plx90x0_init(struct arm_pci_sysdata *);
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:56
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-rpc
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/arch-rpc
Modified Files:
hardware.h io.h irq.h keyboard.h memory.h system.h time.h
Log Message:
Synch to 2.4.15 commit 1
Index: hardware.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-rpc/hardware.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- hardware.h 14 Jan 2001 16:58:32 -0000 1.1.1.1
+++ hardware.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -43,66 +43,27 @@
#define FLUSH_BASE 0xdf000000
#define UNCACHEABLE_ADDR 0xdf010000
-
-#ifndef __ASSEMBLY__
-
-/*
- * for use with inb/outb
- */
-#define IO_VIDC_AUDIO_BASE 0x80140000
-#define IO_VIDC_BASE 0x80100000
-#define IO_IOMD_BASE 0x80080000
-#define IOC_BASE 0x80080000
-
-#define IO_EC_EASI_BASE 0x81400000
-#define IO_EC_IOC4_BASE 0x8009c000
-#define IO_EC_IOC_BASE 0x80090000
-#define IO_EC_MEMC8_BASE 0x8000ac00
-#define IO_EC_MEMC_BASE 0x80000000
-
-/*
- * IO definitions
- */
-#define EXPMASK_BASE ((volatile unsigned char *)0xe0360000)
-#define IOEB_BASE ((volatile unsigned char *)0xe0350050)
-#define PCIO_FLOPPYDMABASE ((volatile unsigned char *)0xe002a000)
-#define PCIO_BASE 0xe0010000
-
/*
- * Offsets from RAM base
+ * IO Addresses
*/
-#define PARAMS_OFFSET 0x0100
-
-/*
- * RAM definitions
- */
-#define GET_MEMORY_END(p) (PAGE_OFFSET + p->u1.s.page_size * \
- (p->u1.s.pages_in_bank[0] + \
- p->u1.s.pages_in_bank[1] + \
- p->u1.s.pages_in_bank[2] + \
- p->u1.s.pages_in_bank[3]))
-
-#define Z_PARAMS_BASE (RAM_START + PARAMS_OFFSET)
-#define FLUSH_BASE_PHYS 0x00000000 /* ROM */
-
-#else
-
-#define VIDC_SND_BASE 0xe0500000
#define VIDC_BASE 0xe0400000
+#define EXPMASK_BASE 0xe0360000
#define IOMD_BASE 0xe0200000
#define IOC_BASE 0xe0200000
-#define PCIO_FLOPPYDMABASE 0xe002a000
#define PCIO_BASE 0xe0010000
+#define FLOPPYDMA_BASE 0xe002a000
-#endif
+#define FLUSH_BASE_PHYS 0x00000000 /* ROM */
+
+#define vidc_writel(val) __raw_writel(val, VIDC_BASE)
-#ifndef __ASSEMBLY__
-#define __EXPMASK(offset) (((volatile unsigned char *)EXPMASK_BASE)[offset])
-#else
-#define __EXPMASK(offset) offset
-#endif
+#define IO_EC_EASI_BASE 0x81400000
+#define IO_EC_IOC4_BASE 0x8009c000
+#define IO_EC_IOC_BASE 0x80090000
+#define IO_EC_MEMC8_BASE 0x8000ac00
+#define IO_EC_MEMC_BASE 0x80000000
-#define EXPMASK_STATUS __EXPMASK(0x00)
-#define EXPMASK_ENABLE __EXPMASK(0x04)
+#define EXPMASK_STATUS (EXPMASK_BASE + 0x00)
+#define EXPMASK_ENABLE (EXPMASK_BASE + 0x04)
#endif
Index: io.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-rpc/io.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- io.h 25 Feb 2001 23:14:53 -0000 1.1.1.2
+++ io.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -70,7 +70,7 @@
/*
* Dynamic IO functions.
*/
-extern __inline__ void __outb (unsigned int value, unsigned int port)
+static inline void __outb (unsigned int value, unsigned int port)
{
unsigned long temp;
__asm__ __volatile__(
@@ -83,7 +83,7 @@
: "cc");
}
-extern __inline__ void __outw (unsigned int value, unsigned int port)
+static inline void __outw (unsigned int value, unsigned int port)
{
unsigned long temp;
__asm__ __volatile__(
@@ -96,7 +96,7 @@
: "cc");
}
-extern __inline__ void __outl (unsigned int value, unsigned int port)
+static inline void __outl (unsigned int value, unsigned int port)
{
unsigned long temp;
__asm__ __volatile__(
@@ -110,7 +110,7 @@
}
#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
-extern __inline__ unsigned sz __in##fnsuffix (unsigned int port) \
+static inline unsigned sz __in##fnsuffix (unsigned int port) \
{ \
unsigned long temp, value; \
__asm__ __volatile__( \
@@ -124,7 +124,7 @@
return (unsigned sz)value; \
}
-extern __inline__ unsigned int __ioaddr (unsigned int port) \
+static inline unsigned int __ioaddr (unsigned int port) \
{ \
if (__PORT_PCIO(port)) \
return (unsigned int)(PCIO_BASE + (port << 2)); \
Index: irq.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-rpc/irq.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- irq.h 14 Jan 2001 16:58:32 -0000 1.1.1.1
+++ irq.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -12,129 +12,100 @@
* 22-08-1998 RMK Restructured IRQ routines
*/
#include <asm/hardware/iomd.h>
+#include <asm/io.h>
#define fixup_irq(x) (x)
static void rpc_mask_irq_ack_a(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]\n"
-" strb %1, [%3]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKA)),
- "r" (ioaddr(IOMD_IRQCLRA)));
+ mask = 1 << irq;
+ val = iomd_readb(IOMD_IRQMASKA);
+ iomd_writeb(val & ~mask, IOMD_IRQMASKA);
+ iomd_writeb(mask, IOMD_IRQCLRA);
}
static void rpc_mask_irq_a(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKA)));
+ mask = 1 << irq;
+ val = iomd_readb(IOMD_IRQMASKA);
+ iomd_writeb(val & ~mask, IOMD_IRQMASKA);
}
static void rpc_unmask_irq_a(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" orr %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKA)));
+ mask = 1 << irq;
+ val = iomd_readb(IOMD_IRQMASKA);
+ iomd_writeb(val | mask, IOMD_IRQMASKA);
}
static void rpc_mask_irq_b(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKB)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_IRQMASKB);
+ iomd_writeb(val & ~mask, IOMD_IRQMASKB);
}
static void rpc_unmask_irq_b(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" orr %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKB)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_IRQMASKB);
+ iomd_writeb(val | mask, IOMD_IRQMASKB);
}
static void rpc_mask_irq_dma(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_DMAMASK)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_DMAMASK);
+ iomd_writeb(val & ~mask, IOMD_DMAMASK);
}
static void rpc_unmask_irq_dma(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" orr %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_DMAMASK)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_DMAMASK);
+ iomd_writeb(val | mask, IOMD_DMAMASK);
}
static void rpc_mask_irq_fiq(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_FIQMASK)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_FIQMASK);
+ iomd_writeb(val & ~mask, IOMD_FIQMASK);
}
static void rpc_unmask_irq_fiq(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" orr %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_FIQMASK)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_FIQMASK);
+ iomd_writeb(val | mask, IOMD_FIQMASK);
}
static __inline__ void irq_init_irq(void)
{
- extern void ecard_disableirq(unsigned int irq);
- extern void ecard_enableirq(unsigned int irq);
int irq;
- outb(0, IOMD_IRQMASKA);
- outb(0, IOMD_IRQMASKB);
- outb(0, IOMD_FIQMASK);
- outb(0, IOMD_DMAMASK);
+ iomd_writeb(0, IOMD_IRQMASKA);
+ iomd_writeb(0, IOMD_IRQMASKB);
+ iomd_writeb(0, IOMD_FIQMASK);
+ iomd_writeb(0, IOMD_DMAMASK);
for (irq = 0; irq < NR_IRQS; irq++) {
switch (irq) {
@@ -156,19 +127,14 @@
irq_desc[irq].unmask = rpc_unmask_irq_b;
break;
- case 16 ... 21:
- irq_desc[irq].valid = 1;
+ case 16 ... 19:
+ case 21:
irq_desc[irq].noautoenable = 1;
+ case 20:
+ irq_desc[irq].valid = 1;
irq_desc[irq].mask_ack = rpc_mask_irq_dma;
irq_desc[irq].mask = rpc_mask_irq_dma;
irq_desc[irq].unmask = rpc_unmask_irq_dma;
- break;
-
- case 32 ... 39:
- irq_desc[irq].valid = 1;
- irq_desc[irq].mask_ack = ecard_disableirq;
- irq_desc[irq].mask = ecard_disableirq;
- irq_desc[irq].unmask = ecard_enableirq;
break;
case 64 ... 71:
Index: keyboard.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-rpc/keyboard.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- keyboard.h 14 Jan 2001 16:58:33 -0000 1.1.1.1
+++ keyboard.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/arch-rpc/keyboard.h
*
- * Copyright (C) 1998 Russell King
+ * Copyright (C) 1998-2001 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -13,19 +13,8 @@
#define NR_SCANCODES 128
-extern void ps2kbd_leds(unsigned char leds);
-extern void ps2kbd_init_hw(void);
-extern unsigned char ps2kbd_sysrq_xlate[NR_SCANCODES];
+extern int ps2kbd_init_hw(void);
-#define kbd_setkeycode(sc,kc) (-EINVAL)
-#define kbd_getkeycode(sc) (-EINVAL)
-
-#define kbd_translate(sc, kcp, rm) ({ *(kcp) = (sc); 1; })
-#define kbd_unexpected_up(kc) (0200)
-#define kbd_leds(leds) ps2kbd_leds(leds)
-#define kbd_init_hw() ps2kbd_init_hw()
-#define kbd_sysrq_xlate ps2kbd_sysrq_xlate
-#define kbd_disable_irq() disable_irq(IRQ_KEYBOARDRX)
-#define kbd_enable_irq() enable_irq(IRQ_KEYBOARDRX)
-
-#define SYSRQ_KEY 13
+#define kbd_disable_irq() disable_irq(IRQ_KEYBOARDRX)
+#define kbd_enable_irq() enable_irq(IRQ_KEYBOARDRX)
+#define kbd_init_hw() ps2kbd_init_hw()
Index: memory.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-rpc/memory.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- memory.h 14 Jan 2001 16:58:33 -0000 1.1.1.1
+++ memory.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -50,4 +50,6 @@
#define __bus_to_virt__is_a_macro
#define __bus_to_virt(x) __phys_to_virt(x)
+#define PHYS_TO_NID(addr) (0)
+
#endif
Index: system.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-rpc/system.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- system.h 14 Jan 2001 16:58:35 -0000 1.1.1.1
+++ system.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -33,13 +33,9 @@
slow_out:
}
-extern __inline__ void arch_reset(char mode)
+static inline void arch_reset(char mode)
{
- extern void ecard_reset(int card);
-
- ecard_reset(-1);
-
- outb(0, IOMD_ROMCR0);
+ iomd_writeb(0, IOMD_ROMCR0);
/*
* Jump into the ROM
Index: time.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-rpc/time.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- time.h 14 Jan 2001 16:58:35 -0000 1.1.1.1
+++ time.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -24,7 +24,7 @@
/*
* Set up timer interrupt.
*/
-extern __inline__ void setup_timer(void)
+static inline void setup_timer(void)
{
ioctime_init();
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:56
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/arch-shark
Modified Files:
dma.h hardware.h ide.h io.h irq.h irqs.h keyboard.h memory.h
param.h system.h time.h timex.h uncompress.h
Log Message:
Synch to 2.4.15 commit 1
Index: dma.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark/dma.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- dma.h 14 Jan 2001 16:58:55 -0000 1.1.1.1
+++ dma.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/arch-shark/dma.h
*
- * by Ale...@st...
+ * by Alexander Schulz
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
@@ -13,6 +13,18 @@
#define MAX_DMA_ADDRESS 0xC0400000
#define MAX_DMA_CHANNELS 8
#define DMA_ISA_CASCADE 4
+
+static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsigned long *zhole_size)
+{
+ if (node != 0) return;
+ /* Only the first 4 MB (=1024 Pages) are usable for DMA */
+ zone_size[1] = zone_size[0] - 1024;
+ zone_size[0] = 1024;
+ zhole_size[1] = zhole_size[0];
+ zhole_size[0] = 0;
+}
+
+#define arch_adjust_zones(node,size,holes) __arch_adjust_zones(node,size,holes)
#endif /* _ASM_ARCH_DMA_H */
Index: hardware.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark/hardware.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- hardware.h 14 Jan 2001 16:58:55 -0000 1.1.1.1
+++ hardware.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/arch-shark/hardware.h
*
- * by Ale...@st...
+ * by Alexander Schulz
*
* derived from:
* linux/include/asm-arm/arch-ebsa110/hardware.h
@@ -40,14 +40,16 @@
/* defines for the Framebuffer */
#define FB_START 0x06000000
-/* Registers for Framebuffer */
-/*#define FBREG_START 0x06800000*/
-
#define UNCACHEABLE_ADDR 0xdf010000
#define SEQUOIA_LED_GREEN (1<<6)
#define SEQUOIA_LED_AMBER (1<<5)
#define SEQUOIA_LED_BACK (1<<7)
+
+#define pcibios_assign_all_busses() 1
+
+#define PCIBIOS_MIN_IO 0x6000
+#define PCIBIOS_MIN_MEM 0x50000000
#endif
Index: ide.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark/ide.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- ide.h 14 Jan 2001 16:58:55 -0000 1.1.1.1
+++ ide.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/arch-shark/ide.h
*
- * by Ale...@st...
+ * by Alexander Schulz
*
* derived from:
* linux/include/asm-arm/arch-ebsa285/ide.h
Index: io.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark/io.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- io.h 25 Feb 2001 23:14:53 -0000 1.1.1.2
+++ io.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/arch-shark/io.h
*
- * by Ale...@st...
+ * by Alexander Schulz
*
* derived from:
* linux/include/asm-arm/arch-ebsa110/io.h
@@ -11,7 +11,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
-#define __arch_ioremap(off,size,nocache) __ioremap(off,size,0)
+#define iomem_valid_addr(off,sz) (1)
+#define iomem_to_phys(off) (off)
#define IO_SPACE_LIMIT 0xffffffff
@@ -28,7 +29,7 @@
* optimize the expressions
*/
#define DECLARE_DYN_OUT(fnsuffix,instr) \
-extern __inline__ void __out##fnsuffix (unsigned int value, unsigned int port) \
+static inline void __out##fnsuffix (unsigned int value, unsigned int port) \
{ \
unsigned long temp; \
__asm__ __volatile__( \
@@ -42,7 +43,7 @@
}
#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
-extern __inline__ unsigned sz __in##fnsuffix (unsigned int port) \
+static inline unsigned sz __in##fnsuffix (unsigned int port) \
{ \
unsigned long temp, value; \
__asm__ __volatile__( \
@@ -56,7 +57,7 @@
return (unsigned sz)value; \
}
-extern __inline__ unsigned int __ioaddr (unsigned int port) \
+static inline unsigned int __ioaddr (unsigned int port) \
{ \
if (__PORT_PCIO(port)) \
return (unsigned int)(PCIO_BASE + (port)); \
Index: irq.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark/irq.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- irq.h 14 Jan 2001 16:58:56 -0000 1.1.1.1
+++ irq.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,13 +1,14 @@
/*
* linux/include/asm-arm/arch-shark/irq.h
*
- * by Ale...@st...
+ * by Alexander Schulz
*
* derived from linux/arch/ppc/kernel/i8259.c and:
* include/asm-arm/arch-ebsa110/irq.h
* Copyright (C) 1996-1998 Russell King
*/
+#include <asm/io.h>
#define fixup_irq(x) (x)
/*
Index: irqs.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark/irqs.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- irqs.h 14 Jan 2001 16:58:56 -0000 1.1.1.1
+++ irqs.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/arch-shark/irqs.h
*
- * by Ale...@st...
+ * by Alexander Schulz
*/
#define NR_IRQS 16
Index: keyboard.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark/keyboard.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- keyboard.h 14 Jan 2001 16:58:57 -0000 1.1.1.1
+++ keyboard.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,6 +1,6 @@
/*
* linux/include/asm-arm/arch-shark/keyboard.h
- * by Ale...@st...
+ * by Alexander Schulz
*
* Derived from linux/include/asm-arm/arch-ebsa285/keyboard.h
* (C) 1998 Russell King
@@ -11,6 +11,12 @@
#include <asm/io.h>
#include <asm/system.h>
+#define KEYBOARD_IRQ IRQ_ISA_KEYBOARD
+#define NR_SCANCODES 128
+
+#define kbd_disable_irq() do { } while (0)
+#define kbd_enable_irq() do { } while (0)
+
extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
extern int pckbd_getkeycode(unsigned int scancode);
extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
@@ -20,22 +26,25 @@
extern void pckbd_init_hw(void);
extern unsigned char pckbd_sysrq_xlate[128];
-#define KEYBOARD_IRQ IRQ_ISA_KEYBOARD
-
-#define NR_SCANCODES 128
-
-#define kbd_setkeycode(sc,kc) pckbd_setkeycode(sc,kc)
-#define kbd_getkeycode(sc) pckbd_getkeycode(sc)
-#define kbd_translate(sc, kcp, rm) pckbd_translate(sc, kcp, rm)
-#define kbd_unexpected_up pckbd_unexpected_up
-#define kbd_leds(leds) pckbd_leds(leds)
-#define kbd_init_hw() pckbd_init_hw()
-#define kbd_sysrq_xlate pckbd_sysrq_xlate
+static inline void kbd_init_hw(void)
+{
+ if (have_isa_bridge) {
+ k_setkeycode = pckbd_setkeycode;
+ k_getkeycode = pckbd_getkeycode;
+ k_translate = pckbd_translate;
+ k_unexpected_up = pckbd_unexpected_up;
+ k_leds = pckbd_leds;
+#ifdef CONFIG_MAGIC_SYSRQ
+ k_sysrq_key = 0x54;
+ k_sysrq_xlate = pckbd_sysrq_xlate;
+#endif
+ pckbd_init_hw();
+ }
+}
-#define kbd_disable_irq()
-#define kbd_enable_irq()
-
-#define SYSRQ_KEY 0x54
+/*
+ * PC Keyboard specifics
+ */
/* resource allocation */
#define kbd_request_region() request_region(0x60, 16, "keyboard")
Index: memory.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark/memory.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- memory.h 14 Jan 2001 16:58:57 -0000 1.1.1.1
+++ memory.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/arch-shark/memory.h
*
- * by Ale...@st...
+ * by Alexander Schulz
*
* derived from:
* linux/include/asm-arm/arch-ebsa110/memory.h
@@ -37,5 +37,7 @@
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt__is_a_macro
#define __bus_to_virt(x) __phys_to_virt(x)
+
+#define PHYS_TO_NID(addr) (0)
#endif
Index: param.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark/param.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- param.h 14 Jan 2001 16:58:57 -0000 1.1.1.1
+++ param.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,10 +1,12 @@
/*
* linux/include/asm-arm/arch-shark/param.h
*
- * by Ale...@st...
+ * by Alexander Schulz
*/
/* This must be a power of 2 because the RTC
* can't use anything else.
*/
#define HZ 64
+
+#define hz_to_std(a) ((a * HZ)/100)
Index: system.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark/system.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- system.h 14 Jan 2001 16:58:57 -0000 1.1.1.1
+++ system.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/arch-shark/system.h
*
- * Copyright (c) 1996-1998 Russell King.
+ * by Alexander Schulz
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
Index: time.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark/time.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- time.h 14 Jan 2001 16:58:57 -0000 1.1.1.1
+++ time.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/arch-shark/time.h
*
- * by Ale...@st...
+ * by Alexander Schulz
*
* Uses the real time clock because you can't run
* the timer with level triggered interrupts and
@@ -46,7 +46,7 @@
/*
* Set up timer interrupt, and return the current time in seconds.
*/
-extern __inline__ void setup_timer(void)
+static inline void setup_timer(void)
{
struct rtc_time r_time;
unsigned long flags;
Index: timex.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark/timex.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- timex.h 14 Jan 2001 16:58:57 -0000 1.1.1.1
+++ timex.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,5 +1,5 @@
/*
* linux/include/asm-arm/arch-shark/timex.h
*
- * by Ale...@st...
+ * by Alexander Schulz
*/
Index: uncompress.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-shark/uncompress.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- uncompress.h 14 Jan 2001 16:58:57 -0000 1.1.1.1
+++ uncompress.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,31 +1,57 @@
/*
- * linux/include/asm-arm/arch-ebsa110/uncompress.h
+ * linux/include/asm-arm/arch-shark/uncompress.h
+ * by Alexander Schulz
*
+ * derived from:
+ * linux/include/asm-arm/arch-ebsa285/uncompress.h
* Copyright (C) 1996,1997,1998 Russell King
*/
+#define SERIAL_BASE ((volatile unsigned char *)0x400003f8)
+
+static __inline__ void putc(char c)
+{
+ int t;
+
+ SERIAL_BASE[0] = c;
+ t=0x10000;
+ while (t--);
+}
+
/*
* This does not append a newline
*/
static void puts(const char *s)
{
- __asm__ __volatile__("
- ldrb %0, [%2], #1
- teq %0, #0
- beq 3f
-1: strb %0, [%3]
-2: ldrb %1, [%3, #0x14]
- and %1, %1, #0x60
- teq %1, #0x60
- bne 2b
- teq %0, #'\n'
- moveq %0, #'\r'
- beq 1b
- ldrb %0, [%2], #1
- teq %0, #0
- bne 1b
-3: " : : "r" (0), "r" (0), "r" (s), "r" (0xf0000be0) : "cc");
+ while (*s) {
+ putc(*s);
+ if (*s == '\n')
+ putc('\r');
+ s++;
+ }
+}
+
+#ifdef DEBUG
+static void putn(unsigned long z)
+{
+ int i;
+ char x;
+
+ putc('0');
+ putc('x');
+ for (i=0;i<8;i++) {
+ x='0'+((z>>((7-i)*4))&0xf);
+ if (x>'9') x=x-'0'+'A'-10;
+ putc(x);
+ }
+}
+
+static void putr()
+{
+ putc('\n');
+ putc('\r');
}
+#endif
/*
* nothing to do
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:56
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-l7200
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/arch-l7200
Modified Files:
dma.h hardware.h io.h irq.h irqs.h memory.h param.h system.h
time.h
Added Files:
aux_reg.h gp_timers.h gpio.h keyboard.h pmpcon.h pmu.h
serial.h sib.h sys-clock.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-l7200/aux_reg.h
*
* Copyright (C) 2000 Steve Hill (sj...@co...)
*
* Changelog:
* 08-02-2000 SJH Created file
*/
#ifndef _ASM_ARCH_AUXREG_H
#define _ASM_ARCH_AUXREG_H
#include <asm/arch/hardware.h>
#define l7200aux_reg *((volatile unsigned int *) (AUX_BASE))
/*
* Auxillary register values
*/
#define AUX_CLEAR 0x00000000
#define AUX_DIAG_LED_ON 0x00000002
#define AUX_RTS_UART1 0x00000004
#define AUX_DTR_UART1 0x00000008
#define AUX_KBD_COLUMN_12_HIGH 0x00000010
#define AUX_KBD_COLUMN_12_OFF 0x00000020
#define AUX_KBD_COLUMN_13_HIGH 0x00000040
#define AUX_KBD_COLUMN_13_OFF 0x00000080
#endif
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-l7200/gp_timers.h
*
* Copyright (C) 2000 Steve Hill (sj...@co...)
*
* Changelog:
* 07-28-2000 SJH Created file
* 08-02-2000 SJH Used structure for registers
*/
#ifndef _ASM_ARCH_GPTIMERS_H
#define _ASM_ARCH_GPTIMERS_H
#include <asm/arch/hardware.h>
/*
* Layout of L7200 general purpose timer registers
*/
struct GPT_Regs {
unsigned int TIMERLOAD;
unsigned int TIMERVALUE;
unsigned int TIMERCONTROL;
unsigned int TIMERCLEAR;
};
#define GPT_BASE (IO_BASE_2 + 0x3000)
#define l7200_timer1_regs ((volatile struct GPT_Regs *) (GPT_BASE))
#define l7200_timer2_regs ((volatile struct GPT_Regs *) (GPT_BASE + 0x20))
/*
* General register values
*/
#define GPT_PRESCALE_1 0x00000000
#define GPT_PRESCALE_16 0x00000004
#define GPT_PRESCALE_256 0x00000008
#define GPT_MODE_FREERUN 0x00000000
#define GPT_MODE_PERIODIC 0x00000040
#define GPT_ENABLE 0x00000080
#define GPT_BZTOG 0x00000100
#define GPT_BZMOD 0x00000200
#define GPT_LOAD_MASK 0x0000ffff
#endif
--- NEW FILE ---
/****************************************************************************/
/*
* linux/include/asm-arm/arch-l7200/gpio.h
*
* Registers and helper functions for the L7200 Link-Up Systems
* GPIO.
*
* (C) Copyright 2000, S A McConnell (sam...@co...)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
/****************************************************************************/
#define GPIO_OFF 0x00005000 /* Offset from IO_START to the GPIO reg's. */
/* IO_START and IO_BASE are defined in hardware.h */
#define GPIO_START (IO_START_2 + GPIO_OFF) /* Physical addr of the GPIO reg. */
#define GPIO_BASE (IO_BASE_2 + GPIO_OFF) /* Virtual addr of the GPIO reg. */
/* Offsets from the start of the GPIO for all the registers. */
#define PADR_OFF 0x000
#define PADDR_OFF 0x004
#define PASBSR_OFF 0x008
#define PAEENR_OFF 0x00c
#define PAESNR_OFF 0x010
#define PAESTR_OFF 0x014
#define PAIMR_OFF 0x018
#define PAINT_OFF 0x01c
#define PBDR_OFF 0x020
#define PBDDR_OFF 0x024
#define PBSBSR_OFF 0x028
#define PBIMR_OFF 0x038
#define PBINT_OFF 0x03c
#define PCDR_OFF 0x040
#define PCDDR_OFF 0x044
#define PCSBSR_OFF 0x048
#define PCIMR_OFF 0x058
#define PCINT_OFF 0x05c
#define PDDR_OFF 0x060
#define PDDDR_OFF 0x064
#define PDSBSR_OFF 0x068
#define PDEENR_OFF 0x06c
#define PDESNR_OFF 0x070
#define PDESTR_OFF 0x074
#define PDIMR_OFF 0x078
#define PDINT_OFF 0x07c
#define PEDR_OFF 0x080
#define PEDDR_OFF 0x084
#define PESBSR_OFF 0x088
#define PEEENR_OFF 0x08c
#define PEESNR_OFF 0x090
#define PEESTR_OFF 0x094
#define PEIMR_OFF 0x098
#define PEINT_OFF 0x09c
/* Define the GPIO registers for use by device drivers and the kernel. */
#define PADR (*(volatile unsigned long *)(GPIO_BASE+PADR_OFF))
#define PADDR (*(volatile unsigned long *)(GPIO_BASE+PADDR_OFF))
#define PASBSR (*(volatile unsigned long *)(GPIO_BASE+PASBSR_OFF))
#define PAEENR (*(volatile unsigned long *)(GPIO_BASE+PAEENR_OFF))
#define PAESNR (*(volatile unsigned long *)(GPIO_BASE+PAESNR_OFF))
#define PAESTR (*(volatile unsigned long *)(GPIO_BASE+PAESTR_OFF))
#define PAIMR (*(volatile unsigned long *)(GPIO_BASE+PAIMR_OFF))
#define PAINT (*(volatile unsigned long *)(GPIO_BASE+PAINT_OFF))
#define PBDR (*(volatile unsigned long *)(GPIO_BASE+PBDR_OFF))
#define PBDDR (*(volatile unsigned long *)(GPIO_BASE+PBDDR_OFF))
#define PBSBSR (*(volatile unsigned long *)(GPIO_BASE+PBSBSR_OFF))
#define PBIMR (*(volatile unsigned long *)(GPIO_BASE+PBIMR_OFF))
#define PBINT (*(volatile unsigned long *)(GPIO_BASE+PBINT_OFF))
#define PCDR (*(volatile unsigned long *)(GPIO_BASE+PCDR_OFF))
#define PCDDR (*(volatile unsigned long *)(GPIO_BASE+PCDDR_OFF))
#define PCSBSR (*(volatile unsigned long *)(GPIO_BASE+PCSBSR_OFF))
#define PCIMR (*(volatile unsigned long *)(GPIO_BASE+PCIMR_OFF))
#define PCINT (*(volatile unsigned long *)(GPIO_BASE+PCINT_OFF))
#define PDDR (*(volatile unsigned long *)(GPIO_BASE+PDDR_OFF))
#define PDDDR (*(volatile unsigned long *)(GPIO_BASE+PDDDR_OFF))
#define PDSBSR (*(volatile unsigned long *)(GPIO_BASE+PDSBSR_OFF))
#define PDEENR (*(volatile unsigned long *)(GPIO_BASE+PDEENR_OFF))
#define PDESNR (*(volatile unsigned long *)(GPIO_BASE+PDESNR_OFF))
#define PDESTR (*(volatile unsigned long *)(GPIO_BASE+PDESTR_OFF))
#define PDIMR (*(volatile unsigned long *)(GPIO_BASE+PDIMR_OFF))
#define PDINT (*(volatile unsigned long *)(GPIO_BASE+PDINT_OFF))
#define PEDR (*(volatile unsigned long *)(GPIO_BASE+PEDR_OFF))
#define PEDDR (*(volatile unsigned long *)(GPIO_BASE+PEDDR_OFF))
#define PESBSR (*(volatile unsigned long *)(GPIO_BASE+PESBSR_OFF))
#define PEEENR (*(volatile unsigned long *)(GPIO_BASE+PEEENR_OFF))
#define PEESNR (*(volatile unsigned long *)(GPIO_BASE+PEESNR_OFF))
#define PEESTR (*(volatile unsigned long *)(GPIO_BASE+PEESTR_OFF))
#define PEIMR (*(volatile unsigned long *)(GPIO_BASE+PEIMR_OFF))
#define PEINT (*(volatile unsigned long *)(GPIO_BASE+PEINT_OFF))
#define VEE_EN 0x02
#define BACKLIGHT_EN 0x04
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-l7200/keyboard.h
*
* Keyboard driver definitions for LinkUp Systems L7200 architecture
*
* Copyright (C) 2000 Scott A McConnell (sam...@co...)
* Steve Hill (sj...@co...)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Changelog:
* 07-18-2000 SAM Created file
* 07-28-2000 SJH Complete rewrite
*/
#include <asm/irq.h>
/*
* Layout of L7200 keyboard registers
*/
struct KBD_Port {
unsigned int KBDR;
unsigned int KBDMR;
unsigned int KBSBSR;
unsigned int Reserved;
unsigned int KBKSR;
};
#define KBD_BASE IO_BASE_2 + 0x4000
#define l7200kbd_hwregs ((volatile struct KBD_Port *) (KBD_BASE))
extern void l7200kbd_init_hw(void);
extern int l7200kbd_translate(unsigned char scancode, unsigned char *keycode,
char raw_mode);
#define kbd_setkeycode(sc,kc) (-EINVAL)
#define kbd_getkeycode(sc) (-EINVAL)
#define kbd_translate(sc, kcp, rm) ({ *(kcp) = (sc); 1; })
#define kbd_unexpected_up(kc) (0200)
#define kbd_leds(leds) do {} while (0)
#define kbd_init_hw() l7200kbd_init_hw()
#define kbd_sysrq_xlate ((unsigned char *)NULL)
#define kbd_disable_irq() disable_irq(IRQ_GCTC2)
#define kbd_enable_irq() enable_irq(IRQ_GCTC2)
#define SYSRQ_KEY 13
--- NEW FILE ---
/****************************************************************************/
/*
* linux/include/asm-arm/arch-l7200/pmpcon.h
*
* Registers and helper functions for the L7200 Link-Up Systems
* DC/DC converter register.
*
* (C) Copyright 2000, S A McConnell (sam...@co...)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
/****************************************************************************/
#define PMPCON_OFF 0x00006000 /* Offset from IO_START_2. */
/* IO_START_2 and IO_BASE_2 are defined in hardware.h */
#define PMPCON_START (IO_START_2 + PMPCON_OFF) /* Physical address of reg. */
#define PMPCON_BASE (IO_BASE_2 + PMPCON_OFF) /* Virtual address of reg. */
#define PMPCON (*(volatile unsigned int *)(PMPCON_BASE))
#define PWM2_50CYCLE 0x800
#define CONTRAST 0x9
#define PWM1H (CONTRAST)
#define PWM1L (CONTRAST << 4)
#define PMPCON_VALUE (PWM2_50CYCLE | PWM1L | PWM1H)
/* PMPCON = 0x811; // too light and fuzzy
* PMPCON = 0x844;
* PMPCON = 0x866; // better color poor depth
* PMPCON = 0x888; // Darker but better depth
* PMPCON = 0x899; // Darker even better depth
* PMPCON = 0x8aa; // too dark even better depth
* PMPCON = 0X8cc; // Way too dark
*/
/* As CONTRAST value increases the greater the depth perception and
* the darker the colors.
*/
--- NEW FILE ---
/****************************************************************************/
/*
* linux/include/asm-arm/arch-l7200/pmu.h
*
* Registers and helper functions for the L7200 Link-Up Systems
* Power Management Unit (PMU).
*
* (C) Copyright 2000, S A McConnell (sam...@co...)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
/****************************************************************************/
#define PMU_OFF 0x00050000 /* Offset from IO_START to the PMU registers. */
/* IO_START and IO_BASE are defined in hardware.h */
#define PMU_START (IO_START + PMU_OFF) /* Physical addr. of the PMU reg. */
#define PMU_BASE (IO_BASE + PMU_OFF) /* Virtual addr. of the PMU reg. */
/* Define the PMU registers for use by device drivers and the kernel. */
typedef struct {
unsigned int CURRENT; /* Current configuration register */
unsigned int NEXT; /* Next configuration register */
unsigned int reserved;
unsigned int RUN; /* Run configuration register */
unsigned int COMM; /* Configuration command register */
unsigned int SDRAM; /* SDRAM configuration bypass register */
} pmu_interface;
#define PMU ((volatile pmu_interface *)(PMU_BASE))
/* Macro's for reading the common register fields. */
#define GET_TRANSOP(reg) ((reg >> 25) & 0x03) /* Bits 26-25 */
#define GET_OSCEN(reg) ((reg >> 16) & 0x01)
#define GET_OSCMUX(reg) ((reg >> 15) & 0x01)
#define GET_PLLMUL(reg) ((reg >> 9) & 0x3f) /* Bits 14-9 */
#define GET_PLLEN(reg) ((reg >> 8) & 0x01)
#define GET_PLLMUX(reg) ((reg >> 7) & 0x01)
#define GET_BCLK_DIV(reg) ((reg >> 3) & 0x03) /* Bits 4-3 */
#define GET_SDRB_SEL(reg) ((reg >> 2) & 0x01)
#define GET_SDRF_SEL(reg) ((reg >> 1) & 0x01)
#define GET_FASTBUS(reg) (reg & 0x1)
/* CFG_NEXT register */
#define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f) /* Bits 24-18 */
#define CFG_NEXT_INTRET ((PMU->NEXT >> 17) & 0x01)
#define CFG_NEXT_SDR_STOP ((PMU->NEXT >> 6) & 0x01)
#define CFG_NEXT_SYSCLKEN ((PMU->NEXT >> 5) & 0x01)
/* Useful field values that can be used to construct the
* CFG_NEXT and CFG_RUN registers.
*/
#define TRANSOP_NOP 0<<25 /* NOCHANGE_NOSTALL */
#define NOCHANGE_STALL 1<<25
#define CHANGE_NOSTALL 2<<25
#define CHANGE_STALL 3<<25
#define INTRET 1<<17
#define OSCEN 1<<16
#define OSCMUX 1<<15
/* PLL frequencies */
#define PLLMUL_0 0<<9 /* 3.6864 MHz */
#define PLLMUL_1 1<<9 /* ?????? MHz */
#define PLLMUL_5 5<<9 /* 18.432 MHz */
#define PLLMUL_10 10<<9 /* 36.864 MHz */
#define PLLMUL_18 18<<9 /* ?????? MHz */
#define PLLMUL_20 20<<9 /* 73.728 MHz */
#define PLLMUL_32 32<<9 /* ?????? MHz */
#define PLLMUL_35 35<<9 /* 129.024 MHz */
#define PLLMUL_36 36<<9 /* ?????? MHz */
#define PLLMUL_39 39<<9 /* ?????? MHz */
#define PLLMUL_40 40<<9 /* 147.456 MHz */
/* Clock recovery times */
#define CRCLOCK_1 1<<18
#define CRCLOCK_2 2<<18
#define CRCLOCK_4 4<<18
#define CRCLOCK_8 8<<18
#define CRCLOCK_16 16<<18
#define CRCLOCK_32 32<<18
#define CRCLOCK_63 63<<18
#define CRCLOCK_127 127<<18
#define PLLEN 1<<8
#define PLLMUX 1<<7
#define SDR_STOP 1<<6
#define SYSCLKEN 1<<5
#define BCLK_DIV_4 2<<3
#define BCLK_DIV_2 1<<3
#define BCLK_DIV_1 0<<3
#define SDRB_SEL 1<<2
#define SDRF_SEL 1<<1
#define FASTBUS 1<<0
/* CFG_SDRAM */
#define SDRREFFQ 1<<0 /* Only if SDRSTOPRQ is not set. */
#define SDRREFACK 1<<1 /* Read-only */
#define SDRSTOPRQ 1<<2 /* Only if SDRREFFQ is not set. */
#define SDRSTOPACK 1<<3 /* Read-only */
#define PICEN 1<<4 /* Enable Co-procesor */
#define PICTEST 1<<5
#define GET_SDRREFFQ ((PMU->SDRAM >> 0) & 0x01)
#define GET_SDRREFACK ((PMU->SDRAM >> 1) & 0x01) /* Read-only */
#define GET_SDRSTOPRQ ((PMU->SDRAM >> 2) & 0x01)
#define GET_SDRSTOPACK ((PMU->SDRAM >> 3) & 0x01) /* Read-only */
#define GET_PICEN ((PMU->SDRAM >> 4) & 0x01)
#define GET_PICTEST ((PMU->SDRAM >> 5) & 0x01)
--- NEW FILE ---
/*
* linux/include/asm-arm/arch-l7200/serial.h
*
* Copyright (c) 2000 Rob Scott (rs...@mt...)
* Steve Hill (sj...@co...)
*
* Changelog:
* 03-20-2000 SJH Created
* 03-26-2000 SJH Added flags for serial ports
* 03-27-2000 SJH Corrected BASE_BAUD value
* 04-14-2000 RS Made register addr dependent on IO_BASE
* 05-03-2000 SJH Complete rewrite
* 05-09-2000 SJH Stripped out architecture specific serial stuff
* and placed it in a separate file
* 07-28-2000 SJH Moved base baud rate variable
*/
#ifndef __ASM_ARCH_SERIAL_H
#define __ASM_ARCH_SERIAL_H
/*
* This assumes you have a 3.6864 MHz clock for your UART.
*/
#define BASE_BAUD 3686400
/*
* Standard COM flags
*/
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
#define RS_TABLE_SIZE 2
#define STD_SERIAL_PORT_DEFNS \
/* MAGIC UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, UART1_BASE, IRQ_UART_1, STD_COM_FLAGS }, /* ttyLU0 */ \
{ 0, BASE_BAUD, UART2_BASE, IRQ_UART_2, STD_COM_FLAGS }, /* ttyLU1 */ \
#define EXTRA_SERIAL_PORT_DEFNS
#endif
--- NEW FILE ---
/****************************************************************************/
/*
* linux/include/asm-arm/arch-l7200/sib.h
*
* Registers and helper functions for the Serial Interface Bus.
*
* (C) Copyright 2000, S A McConnell (sam...@co...)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
/****************************************************************************/
#define SIB_OFF 0x00040000 /* Offset from IO_START to the SIB reg's. */
/* IO_START and IO_BASE are defined in hardware.h */
#define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */
#define SIB_BASE (IO_BASE + SIB_OFF) /* Virtual addr of the SIB reg. */
/* Offsets from the start of the SIB for all the registers. */
/* Define the SIB registers for use by device drivers and the kernel. */
typedef struct
{
unsigned int MCCR; /* SIB Control Register Offset: 0x00 */
unsigned int RES1; /* Reserved Offset: 0x04 */
unsigned int MCDR0; /* SIB Data Register 0 Offset: 0x08 */
unsigned int MCDR1; /* SIB Data Register 1 Offset: 0x0c */
unsigned int MCDR2; /* SIB Data Register 2 (UCB1x00) Offset: 0x10 */
unsigned int RES2; /* Reserved Offset: 0x14 */
unsigned int MCSR; /* SIB Status Register Offset: 0x18 */
} SIB_Interface;
#define SIB ((volatile SIB_Interface *) (SIB_BASE))
/* MCCR */
#define INTERNAL_FREQ 9216000 /* Hertz */
#define AUDIO_FREQ 5000 /* Hertz */
#define TELECOM_FREQ 5000 /* Hertz */
#define AUDIO_DIVIDE (INTERNAL_FREQ / (32 * AUDIO_FREQ))
#define TELECOM_DIVIDE (INTERNAL_FREQ / (32 * TELECOM_FREQ))
#define MCCR_ASD57 AUDIO_DIVIDE
#define MCCR_TSD57 (TELECOM_DIVIDE << 8)
#define MCCR_MCE (1 << 16) /* SIB enable */
#define MCCR_ECS (1 << 17) /* External Clock Select */
#define MCCR_ADM (1 << 18) /* A/D Data Sampling */
#define MCCR_PMC (1 << 26) /* PIN Multiplexer Control */
#define GET_ASD ((SIB->MCCR >> 0) & 0x3f) /* Audio Sample Rate Div. */
#define GET_TSD ((SIB->MCCR >> 8) & 0x3f) /* Telcom Sample Rate Div. */
#define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */
#define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */
#define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */
#define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */
#define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */
#define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */
#define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */
#define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */
#define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */
#define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */
#define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */
#define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */
/* MCDR0 */
#define AUDIO_RECV ((SIB->MCDR0 >> 4) & 0xfff)
#define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4))
/* MCDR1 */
#define TELECOM_RECV ((SIB->MCDR1 >> 2) & 032fff)
#define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2))
/* MCSR */
#define MCSR_ATU (1 << 4) /* Audio Transmit FIFO Underrun */
#define MCSR_ARO (1 << 5) /* Audio Receive FIFO Underrun */
#define MCSR_TTU (1 << 6) /* TELECOM Transmit FIFO Underrun */
#define MCSR_TRO (1 << 7) /* TELECOM Receive FIFO Underrun */
#define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO)
#define GET_ATS ((SIB->MCSR >> 0) & 0x01) /* Audio Transmit FIFO Service Req*/
#define GET_ARS ((SIB->MCSR >> 1) & 0x01) /* Audio Recv FIFO Service Request*/
#define GET_TTS ((SIB->MCSR >> 2) & 0x01) /* TELECOM Transmit FIFO Flag */
#define GET_TRS ((SIB->MCSR >> 3) & 0x01) /* TELECOM Recv FIFO Service Req. */
#define GET_ATU ((SIB->MCSR >> 4) & 0x01) /* Audio Transmit FIFO Underrun */
#define GET_ARO ((SIB->MCSR >> 5) & 0x01) /* Audio Receive FIFO Underrun */
#define GET_TTU ((SIB->MCSR >> 6) & 0x01) /* TELECOM Transmit FIFO Underrun */
#define GET_TRO ((SIB->MCSR >> 7) & 0x01) /* TELECOM Receive FIFO Underrun */
#define GET_ANF ((SIB->MCSR >> 8) & 0x01) /* Audio Transmit FIFO not full */
#define GET_ANE ((SIB->MCSR >> 9) & 0x01) /* Audio Receive FIFO not empty */
#define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */
#define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */
#define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */
#define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */
#define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */
#define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */
/* MCDR2 */
#define MCDR2_rW (1 << 16)
#define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff)))
#define MCDR2_WRITE_COMPLETE GET_CWC
#define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17))
#define MCDR2_READ_COMPLETE GET_CRC
#define MCDR2_READ (SIB->MCDR2 & 0xffff)
--- NEW FILE ---
/****************************************************************************/
/*
* linux/include/asm-arm/arch-l7200/sys-clock.h
*
* Registers and helper functions for the L7200 Link-Up Systems
* System clocks.
*
* (C) Copyright 2000, S A McConnell (sam...@co...)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
/****************************************************************************/
#define SYS_CLOCK_OFF 0x00050030 /* Offset from IO_START. */
/* IO_START and IO_BASE are defined in hardware.h */
#define SYS_CLOCK_START (IO_START + SYS_CLCOK_OFF) /* Physical address */
#define SYS_CLOCK_BASE (IO_BASE + SYS_CLOCK_OFF) /* Virtual address */
/* Define the interface to the SYS_CLOCK */
typedef struct
{
unsigned int ENABLE;
unsigned int ESYNC;
unsigned int SELECT;
} sys_clock_interface;
#define SYS_CLOCK ((volatile sys_clock_interface *)(SYS_CLOCK_BASE))
//#define CLOCK_EN (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF))
//#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF))
//#define CLOCK_SEL (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF))
/* SYS_CLOCK -> ENABLE */
#define SYN_EN 1<<0
#define B18M_EN 1<<1
#define CLK3M6_EN 1<<2
#define BUART_EN 1<<3
#define CLK18MU_EN 1<<4
#define FIR_EN 1<<5
#define MIRN_EN 1<<6
#define UARTM_EN 1<<7
#define SIBADC_EN 1<<8
#define ALTD_EN 1<<9
#define CLCLK_EN 1<<10
/* SYS_CLOCK -> SELECT */
#define CLK18M_DIV 1<<0
#define MIR_SEL 1<<1
#define SSP_SEL 1<<4
#define MM_DIV 1<<5
#define MM_SEL 1<<6
#define ADC_SEL_2 0<<7
#define ADC_SEL_4 1<<7
#define ADC_SEL_8 3<<7
#define ADC_SEL_16 7<<7
#define ADC_SEL_32 0x0f<<7
#define ADC_SEL_64 0x1f<<7
#define ADC_SEL_128 0x3f<<7
#define ALTD_SEL 1<<13
Index: dma.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-l7200/dma.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- dma.h 14 Jan 2001 16:58:58 -0000 1.1.1.1
+++ dma.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -1,26 +1,24 @@
/*
* linux/include/asm-arm/arch-l7200/dma.h
+ *
+ * Copyright (C) 2000 Steve Hill (sj...@co...)
+ *
+ * Changelog:
+ * 08-29-2000 SJH Created
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
+/* DMA is not yet implemented! It should be the same as acorn, copy over.. */
+
/*
* This is the maximum DMA address that can be DMAd to.
* There should not be more than (0xd0000000 - 0xc0000000)
* bytes of RAM.
*/
-#define MAX_DMA_ADDRESS 0xd0000000
-#define MAX_DMA_CHANNELS 8
-
-#define DMA_0 0
-#define DMA_1 1
-#define DMA_2 2
-#define DMA_3 3
-#define DMA_S0 4
-#define DMA_S1 5
-#define DMA_VIRTUAL_FLOPPY 6
-#define DMA_VIRTUAL_SOUND 7
+#define MAX_DMA_ADDRESS 0xd0000000
+#define MAX_DMA_CHANNELS 0
-#define DMA_FLOPPY DMA_VIRTUAL_FLOPPY
+#define DMA_S0 0
-#endif
+#endif /* _ASM_ARCH_DMA_H */
Index: hardware.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-l7200/hardware.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- hardware.h 14 Jan 2001 16:58:58 -0000 1.1.1.1
+++ hardware.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -13,6 +13,8 @@
* 04-21-2000 RS Changed mapping of I/O in virtual space
* 04-25-2000 SJH Removed unused symbols and such
* 05-05-2000 SJH Complete rewrite
+ * 07-31-2000 SJH Added undocumented debug auxillary port to
+ * get at last two columns for keyboard driver
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
@@ -33,6 +35,18 @@
#define IO_START_2 0x90000000 /* I/O */
#define IO_SIZE_2 0x01000000
#define IO_BASE_2 0xd1000000
+
+#define AUX_START 0x1a000000 /* AUX PORT */
+#define AUX_SIZE 0x01000000
+#define AUX_BASE 0xd2000000
+
+#define FLASH1_START 0x00000000 /* FLASH BANK 1 */
+#define FLASH1_SIZE 0x01000000
+#define FLASH1_BASE 0xd3000000
+
+#define FLASH2_START 0x10000000 /* FLASH BANK 2 */
+#define FLASH2_SIZE 0x01000000
+#define FLASH2_BASE 0xd4000000
#define ISA_START 0x20000000 /* ISA */
#define ISA_SIZE 0x20000000
Index: io.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-l7200/io.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- io.h 14 Jan 2001 16:58:58 -0000 1.1.1.1
+++ io.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -3,8 +3,9 @@
*
* Copyright (C) 2000 Steve Hill (sj...@co...)
*
- * Modifications:
+ * Changelog:
* 03-21-2000 SJH Created from linux/include/asm-arm/arch-nexuspci/io.h
+ * 08-31-2000 SJH Added in IO functions necessary for new drivers
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
@@ -14,16 +15,49 @@
#define IO_SPACE_LIMIT 0xffffffff
/*
+ * There are not real ISA nor PCI buses, so we fake it.
+ */
+#define __io_pci(a) (PCIO_BASE + (a))
+#define __mem_pci(a) ((unsigned long)(a))
+#define __mem_isa(a) ((unsigned long)(a))
+
+#define __ioaddr(p) __io_pci(p)
+
+/*
+ * Generic virtual read/write
+ */
+#define __arch_getb(a) (*(volatile unsigned char *)(a))
+#define __arch_getl(a) (*(volatile unsigned int *)(a))
+
+static inline unsigned int __arch_getw(unsigned long a)
+{
+ unsigned int value;
+ __asm__ __volatile__("ldr%?h %0, [%1, #0] @ getw"
+ : "=&r" (value)
+ : "r" (a));
+ return value;
+}
+
+#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
+#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
+
+static inline void __arch_putw(unsigned int value, unsigned long a)
+{
+ __asm__ __volatile__("str%?h %0, [%1, #0] @ putw"
+ : : "r" (value), "r" (a));
+}
+
+/*
* Translated address IO functions
*
* IO address has already been translated to a virtual address
*/
-#define outb_t(v,p) (*(volatile unsigned char *)(p) = (v))
-#define inb_t(p) (*(volatile unsigned char *)(p))
-#define outw_t(v,p) (*(volatile unsigned int *)(p) = (v))
-#define inw_t(p) (*(volatile unsigned int *)(p))
-#define outl_t(v,p) (*(volatile unsigned long *)(p) = (v))
-#define inl_t(p) (*(volatile unsigned long *)(p))
+#define outb_t(v,p) (*(volatile unsigned char *)(p) = (v))
+#define inb_t(p) (*(volatile unsigned char *)(p))
+#define outw_t(v,p) (*(volatile unsigned int *)(p) = (v))
+#define inw_t(p) (*(volatile unsigned int *)(p))
+#define outl_t(v,p) (*(volatile unsigned long *)(p) = (v))
+#define inl_t(p) (*(volatile unsigned long *)(p))
/*
* FIXME - These are to allow for linking. On all the other
@@ -32,11 +66,13 @@
* macros will eventually become more involved. Use
* with caution and don't be surprised by kernel oopses!!!
*/
-#define inb(p) inb_t(p)
-#define inw(p) inw_t(p)
-#define inl(p) inl_t(p)
-#define outb(v,p) outb_t(v,p)
-#define outw(v,p) outw_t(v,p)
-#define outl(v,p) outl_t(v,p)
+#define inb(p) inb_t(p)
+#define inw(p) inw_t(p)
+#define inl(p) inl_t(p)
+#define outb(v,p) outb_t(v,p)
+#define outw(v,p) outw_t(v,p)
+#define outl(v,p) outl_t(v,p)
+
+#define __arch_ioremap __ioremap
#endif
Index: irq.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-l7200/irq.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- irq.h 14 Jan 2001 16:58:59 -0000 1.1.1.1
+++ irq.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -10,6 +10,8 @@
* 05-05-2000 SJH Complete rewrite
*/
+#include <asm/arch/hardware.h>
+
/*
* IRQ base register
*/
Index: irqs.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-l7200/irqs.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- irqs.h 14 Jan 2001 16:58:59 -0000 1.1.1.1
+++ irqs.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -7,6 +7,12 @@
* Changelog:
* 01-02-2000 RS Create l7200 version
* 03-28-2000 SJH Removed unused interrupt
+ * 07-28-2000 SJH Added pseudo-keyboard interrupt
+ */
+
+/*
+ * NOTE: The second timer (Timer 2) is used as the keyboard
+ * interrupt when the keyboard driver is enabled.
*/
#define NR_IRQS 32
@@ -16,7 +22,7 @@
#define IRQ_DEBUG_RX 2 /* Comm Rx debug */
#define IRQ_DEBUG_TX 3 /* Comm Tx debug */
#define IRQ_GCTC1 4 /* Timer 1 */
-#define IRQ_GCTC2 5 /* Timer 2 */
+#define IRQ_GCTC2 5 /* Timer 2 / Keyboard */
#define IRQ_DMA 6 /* DMA controller */
#define IRQ_CLCD 7 /* Color LCD controller */
#define IRQ_SM_RX 8 /* Smart card */
@@ -40,6 +46,11 @@
#define IRQ_INT0 26 /* External active low interrupt */
#define IRQ_INT1 27 /* External active low interrupt */
#define IRQ_INT2 28 /* External active low interrupt */
-#define IRQ_INT3 29 /* External active low interrupt */
+#define IRQ_UCB1200 29 /* Interrupt generated by UCB1200*/
#define IRQ_BAT_LO 30 /* Low batery or external power */
#define IRQ_MEDIA_CHG 31 /* Media change interrupt */
+
+/*
+ * This is the offset of the FIQ "IRQ" numbers
+ */
+#define FIQ_START 64
Index: memory.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-l7200/memory.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- memory.h 14 Jan 2001 16:58:59 -0000 1.1.1.1
+++ memory.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -47,4 +47,6 @@
#define __bus_to_virt__is_a_macro
#define __bus_to_virt(x) __phys_to_virt(x)
+#define PHYS_TO_NID(addr) (0)
+
#endif
Index: param.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-l7200/param.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- param.h 14 Jan 2001 16:58:59 -0000 1.1.1.1
+++ param.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -20,4 +20,13 @@
*/
#define HZ 128
+/*
+ * Define hz_to_std, since we have a non 100Hz define
+ * (see include/asm-arm/param.h)
+ */
+
+#if defined(__KERNEL__)
+#define hz_to_std(a) ((a * HZ)/100)
+#endif
+
#endif
Index: system.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-l7200/system.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- system.h 14 Jan 2001 16:59:00 -0000 1.1.1.1
+++ system.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -14,12 +14,11 @@
static void arch_idle(void)
{
- while (!current->need_resched && !hlt_counter) {
- cpu_do_idle(IDLE_WAIT_SLOW);
- }
+ /* fixme: this needs to be cleaned up (converted from ASM code) --rmk */
+ *(unsigned long *)(IO_BASE + 0x50004) = 1; /* idle mode */
}
-extern inline void arch_reset(char mode)
+static inline void arch_reset(char mode)
{
if (mode == 's') {
cpu_reset(0);
Index: time.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-l7200/time.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- time.h 14 Jan 2001 16:59:00 -0000 1.1.1.1
+++ time.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -40,7 +40,7 @@
#define RTC_EN_STWDOG 0x08 /* Enable watchdog */
/*
- * Handler for timer interrupt
+ * Handler for RTC timer interrupt
*/
static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
@@ -50,9 +50,9 @@
}
/*
- * Set up timer interrupt, and return the current time in seconds.
+ * Set up RTC timer interrupt, and return the current time in seconds.
*/
-extern __inline__ void setup_timer(void)
+static inline void setup_timer(void)
{
RTC_RTCC = 0; /* Clear interrupt */
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:55
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-tbox
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/arch-tbox
Modified Files:
io.h keyboard.h memory.h time.h
Log Message:
Synch to 2.4.15 commit 1
Index: io.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-tbox/io.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- io.h 25 Feb 2001 23:14:53 -0000 1.1.1.2
+++ io.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -15,7 +15,7 @@
/*
* Generic virtual read/write
*/
-extern __inline__ unsigned int __arch_getw(unsigned long a)
+static inline unsigned int __arch_getw(unsigned long a)
{
unsigned int value;
__asm__ __volatile__("ldr%?h %0, [%1, #0] @ getw"
@@ -24,7 +24,7 @@
return value;
}
-extern __inline__ void __arch_putw(unsigned int value, unsigned long a)
+static inline void __arch_putw(unsigned int value, unsigned long a)
{
__asm__ __volatile__("str%?h %0, [%1, #0] @ putw"
: : "r" (value), "r" (a));
Index: keyboard.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-tbox/keyboard.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- keyboard.h 14 Jan 2001 16:59:01 -0000 1.1.1.1
+++ keyboard.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -3,27 +3,12 @@
*
* Driver definitions for Tbox dummy keyboard.
*
- * Copyright (C) 1998 Russell King
+ * Copyright (C) 1998-2001 Russell King
* Copyright (C) 1998 Philip Blundell
*/
#define NR_SCANCODES 128
-#define kbd_setkeycode(sc,kc) (-EINVAL)
-#define kbd_getkeycode(sc) (-EINVAL)
-
-/* Prototype: int kbd_pretranslate(scancode, raw_mode)
- * Returns : 0 to ignore scancode
- */
-#define kbd_pretranslate(sc,rm) (1)
-
-/* Prototype: int kbd_translate(scancode, *keycode, *up_flag, raw_mode)
- * Returns : 0 to ignore scancode, *keycode set to keycode, *up_flag
- * set to 0200 if scancode indicates release
- */
-#define kbd_translate(sc, kcp, rm) 0
-#define kbd_unexpected_up(kc) (0200)
-#define kbd_leds(leds) do { } while (0)
-#define kbd_init_hw() do { } while (0)
-#define kbd_disable_irq() do { } while (0)
-#define kbd_enable_irq() do { } while (0)
+#define kbd_init_hw() do { } while (0)
+#define kbd_disable_irq() do { } while (0)
+#define kbd_enable_irq() do { } while (0)
Index: memory.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-tbox/memory.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- memory.h 14 Jan 2001 16:59:01 -0000 1.1.1.1
+++ memory.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -41,4 +41,6 @@
#define __bus_to_virt__is_a_macro
#define __bus_to_virt(x) __phys_to_virt(x)
+#define PHYS_TO_NID(addr) (0)
+
#endif
Index: time.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-tbox/time.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- time.h 14 Jan 2001 16:59:01 -0000 1.1.1.1
+++ time.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -8,6 +8,13 @@
* our soft copy.
*/
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
#include <asm/io.h>
#include <asm/hardware.h>
@@ -22,7 +29,7 @@
do_timer(regs);
}
-extern __inline__ void setup_timer (void)
+static inline void setup_timer (void)
{
/*
* Default the date to 1 Jan 1970 0:0:0
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa110
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/arch-ebsa110
Modified Files:
hardware.h io.h irq.h memory.h time.h uncompress.h
Removed Files:
processor.h
Log Message:
Synch to 2.4.15 commit 1
Index: hardware.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa110/hardware.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- hardware.h 14 Jan 2001 16:58:27 -0000 1.1.1.1
+++ hardware.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -12,41 +12,55 @@
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
-#ifndef __ASSEMBLY__
-
/*
- * IO definitions
+ * The EBSA110 has a weird "ISA IO" region:
+ *
+ * Region 0 (addr = 0xf0000000 + io << 2)
+ * --------------------------------------------------------
+ * Physical region IO region
+ * f0000fe0 - f0000ffc 3f8 - 3ff ttyS0
+ * f0000e60 - f0000e64 398 - 399
+ * f0000de0 - f0000dfc 378 - 37f lp0
+ * f0000be0 - f0000bfc 2f8 - 2ff ttyS1
+ *
+ * Region 1 (addr = 0xf0000000 + (io & ~1) << 1 + (io & 1))
+ * --------------------------------------------------------
+ * Physical region IO region
+ * f00014f1 a79 pnp write data
+ * f00007c0 - f00007c1 3e0 - 3e1 pcmcia
+ * f00004f1 279 pnp address
+ * f0000440 - f000046c 220 - 236 eth0
+ * f0000405 203 pnp read data
*/
-#define PIT_CTRL ((volatile unsigned char *)0xf200000d)
-#define PIT_T2 ((volatile unsigned char *)0xf2000009)
-#define PIT_T1 ((volatile unsigned char *)0xf2000005)
-#define PIT_T0 ((volatile unsigned char *)0xf2000001)
-/*
- * Mapping areas
- */
-#define IO_BASE 0xe0000000
+#define ISAMEM_PHYS 0xe0000000
+#define ISAMEM_SIZE 0x10000000
-/*
- * RAM definitions
- */
-#define FLUSH_BASE_PHYS 0x40000000
+#define ISAIO_PHYS 0xf0000000
+#define ISAIO_SIZE PGDIR_SIZE
-#else /* __ASSEMBLY__ */
+#define TRICK0_PHYS 0xf2000000
+#define TRICK1_PHYS 0xf2400000
+#define TRICK2_PHYS 0xf2800000
+#define TRICK3_PHYS 0xf2c00000
+#define TRICK4_PHYS 0xf3000000
+#define TRICK5_PHYS 0xf3400000
+#define TRICK6_PHYS 0xf3800000
+#define TRICK7_PHYS 0xf3c00000
-#define IO_BASE 0
+#define ISAMEM_BASE 0xe0000000
+#define ISAIO_BASE 0xf0000000
-#endif /* __ASSEMBLY__ */
-
-#define IO_SIZE 0x20000000
-#define IO_START 0xe0000000
+#define PIT_BASE 0xfc000000
+#define SOFT_BASE 0xfd000000
+/*
+ * RAM definitions
+ */
+#define FLUSH_BASE_PHYS 0x40000000
#define FLUSH_BASE 0xdf000000
-#define PCIO_BASE 0xf0000000
-
-#define UNCACHEABLE_ADDR 0xf3000000
-#define PARAMS_OFFSET 0x400
+#define UNCACHEABLE_ADDR 0xff000000 /* IRQ_STAT */
#endif
Index: io.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa110/io.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- io.h 25 Feb 2001 23:14:53 -0000 1.1.1.2
+++ io.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -13,7 +13,7 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
-#define IO_SPACE_LIMIT 0xffffffff
+#define IO_SPACE_LIMIT 0xffff
/*
* Generic virtual read/write
@@ -21,6 +21,39 @@
#define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
-#define __io(p) (ISAIO_BASE + ((p) << 2))
+u8 __inb(int port);
+u16 __inw(int port);
+u32 __inl(int port);
+
+#define inb(p) __inb(p)
+#define inw(p) __inw(p)
+#define inl(p) __inl(p)
+
+void __outb(u8 val, int port);
+void __outw(u16 val, int port);
+void __outl(u32 val, int port);
+
+#define outb(v,p) __outb(v,p)
+#define outw(v,p) __outw(v,p)
+#define outl(v,p) __outl(v,p)
+
+u8 __readb(void *addr);
+u16 __readw(void *addr);
+u32 __readl(void *addr);
+
+#define readb(b) __readb(b)
+#define readw(b) __readw(b)
+#define readl(b) __readl(b)
+
+void __writeb(u8 val, void *addr);
+void __writew(u16 val, void *addr);
+void __writel(u32 val, void *addr);
+
+#define writeb(v,b) __writeb(v,b)
+#define writew(v,b) __writew(v,b)
+#define writel(v,b) __writel(v,b)
+
+#define __arch_ioremap(off,sz,c) ((void *)(off))
+#define __arch_iounmap(virt) do { } while (0)
#endif
Index: irq.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa110/irq.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- irq.h 14 Jan 2001 16:58:28 -0000 1.1.1.1
+++ irq.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -10,47 +10,4 @@
* Changelog:
* 22-08-1998 RMK Restructured IRQ routines
*/
-
-#define IRQ_MCLR ((volatile unsigned char *)0xf3000000)
-#define IRQ_MSET ((volatile unsigned char *)0xf2c00000)
-#define IRQ_MASK ((volatile unsigned char *)0xf2c00000)
-
-#define fixup_irq(x) (x)
-
-static void ebsa110_mask_and_ack_irq(unsigned int irq)
-{
- *IRQ_MCLR = 1 << irq;
-}
-
-static void ebsa110_mask_irq(unsigned int irq)
-{
- *IRQ_MCLR = 1 << irq;
-}
-
-static void ebsa110_unmask_irq(unsigned int irq)
-{
- *IRQ_MSET = 1 << irq;
-}
-
-static __inline__ void irq_init_irq(void)
-{
- unsigned long flags;
- int irq;
-
- save_flags_cli (flags);
- *IRQ_MCLR = 0xff;
- *IRQ_MSET = 0x55;
- *IRQ_MSET = 0x00;
- if (*IRQ_MASK != 0x55)
- while (1);
- *IRQ_MCLR = 0xff; /* clear all interrupt enables */
- restore_flags (flags);
-
- for (irq = 0; irq < NR_IRQS; irq++) {
- irq_desc[irq].valid = 1;
- irq_desc[irq].probe_ok = 1;
- irq_desc[irq].mask_ack = ebsa110_mask_and_ack_irq;
- irq_desc[irq].mask = ebsa110_mask_irq;
- irq_desc[irq].unmask = ebsa110_unmask_irq;
- }
-}
+#define fixup_irq(i) (i)
Index: memory.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa110/memory.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- memory.h 25 Feb 2001 23:14:53 -0000 1.1.1.2
+++ memory.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -35,13 +35,19 @@
#define PHYS_OFFSET (0x00000000UL)
#define __virt_to_phys__is_a_macro
-#define __virt_to_phys(vpage) ((vpage) - PAGE_OFFSET)
+#define __virt_to_phys(vpage) ((vpage) - PAGE_OFFSET)
#define __phys_to_virt__is_a_macro
-#define __phys_to_virt(ppage) ((ppage) + PAGE_OFFSET)
+#define __phys_to_virt(ppage) ((ppage) + PAGE_OFFSET)
+/*
+ * We keep this 1:1 so that we don't interfere
+ * with the PCMCIA memory regions
+ */
#define __virt_to_bus__is_a_macro
-#define __virt_to_bus(x) __virt_to_phys(x)
+#define __virt_to_bus(x) (x)
#define __bus_to_virt__is_a_macro
-#define __bus_to_virt(x) __phys_to_virt(x)
+#define __bus_to_virt(x) (x)
+
+#define PHYS_TO_NID(addr) (0)
#endif
Index: time.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa110/time.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- time.h 14 Jan 2001 16:58:28 -0000 1.1.1.1
+++ time.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -18,57 +18,24 @@
#include <asm/leds.h>
-#define MCLK_47_8
-
-#if defined(MCLK_42_3)
-#define PIT1_COUNT 0xecbe
-#elif defined(MCLK_47_8)
-/*
- * This should be 0x10B43, but that doesn't exactly fit.
- * We run the timer interrupt at 5ms, and then divide it by
- * two in software... This is so that the user processes
- * see exactly the same model whichever ARM processor they're
- * running on.
- */
-#define PIT1_COUNT 0x85A1
-#define DIVISOR 2
-#endif
+extern int ebsa110_reset_timer(void);
+extern void ebsa110_setup_timer(void);
static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
- *PIT_T1 = (PIT1_COUNT) & 0xff;
- *PIT_T1 = (PIT1_COUNT) >> 8;
-
-#ifdef DIVISOR
- {
- static unsigned int divisor;
-
- if (divisor--)
- return;
- divisor = DIVISOR - 1;
+ if (ebsa110_reset_timer()) {
+ do_leds();
+ do_timer(regs);
+ do_profile(regs);
}
-#endif
- do_leds();
- do_timer(regs);
- do_profile(regs);
}
/*
* Set up timer interrupt.
*/
-extern __inline__ void setup_timer(void)
+static inline void setup_timer(void)
{
- /*
- * Timer 1, mode 0, 16-bit, autoreload
- */
- *PIT_CTRL = 0x70;
-
- /*
- * Refresh counter clocked at 47.8MHz/7 = 146.4ns
- * We want centi-second interrupts
- */
- *PIT_T1 = (PIT1_COUNT) & 0xff;
- *PIT_T1 = (PIT1_COUNT) >> 8;
+ ebsa110_setup_timer();
timer_irq.handler = timer_interrupt;
Index: uncompress.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa110/uncompress.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- uncompress.h 14 Jan 2001 16:58:29 -0000 1.1.1.1
+++ uncompress.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -28,7 +28,11 @@
ldrb %0, [%2], #1
teq %0, #0
bne 1b
-3: " : : "r" (0), "r" (0), "r" (s), "r" (0xf0000be0) : "cc");
+3: ldrb %1, [%3, #0x14]
+ and %1, %1, #0x60
+ teq %1, #0x60
+ bne 3b
+ " : : "r" (0), "r" (0), "r" (s), "r" (0xf0000be0) : "cc");
}
/*
--- processor.h DELETED ---
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:54
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-nexuspci
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/arch-nexuspci
Modified Files:
io.h keyboard.h memory.h time.h
Log Message:
Synch to 2.4.15 commit 1
Index: io.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-nexuspci/io.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- io.h 25 Feb 2001 23:14:53 -0000 1.1.1.2
+++ io.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -18,7 +18,7 @@
#define __mem_isa(a) (PCIMEM_BASE + (unsigned long)(a))
#else
-extern __inline__ unsigned long ___mem_pci(unsigned long a)
+static inline unsigned long ___mem_pci(unsigned long a)
{
/* PCI addresses must have been ioremapped */
if (a <= 0xc0000000 || a >= 0xe0000000)
@@ -26,7 +26,7 @@
return a;
}
-extern __inline__ unsigned long ___mem_isa(unsigned long a)
+static inline unsigned long ___mem_isa(unsigned long a)
{
if (a >= 16*1048576)
BUG();
Index: keyboard.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-nexuspci/keyboard.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- keyboard.h 14 Jan 2001 16:58:31 -0000 1.1.1.1
+++ keyboard.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -3,27 +3,12 @@
*
* Driver definitions for PCI card dummy keyboard.
*
- * Copyright (C) 1998 Russell King
+ * Copyright (C) 1998-2001 Russell King
* Copyright (C) 1998 Philip Blundell
*/
#define NR_SCANCODES 128
-#define kbd_setkeycode(sc,kc) (-EINVAL)
-#define kbd_getkeycode(sc) (-EINVAL)
-
-/* Prototype: int kbd_pretranslate(scancode, raw_mode)
- * Returns : 0 to ignore scancode
- */
-#define kbd_pretranslate(sc,rm) (1)
-
-/* Prototype: int kbd_translate(scancode, *keycode, *up_flag, raw_mode)
- * Returns : 0 to ignore scancode, *keycode set to keycode, *up_flag
- * set to 0200 if scancode indicates release
- */
-#define kbd_translate(sc, kcp, rm) 0
-#define kbd_unexpected_up(kc) (0200)
-#define kbd_leds(leds) do { } while (0)
-#define kbd_init_hw() do { } while (0)
-#define kbd_disable_irq() do { } while (0)
-#define kbd_enable_irq() do { } while (0)
+#define kbd_init_hw() do { } while (0)
+#define kbd_disable_irq() do { } while (0)
+#define kbd_enable_irq() do { } while (0)
Index: memory.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-nexuspci/memory.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- memory.h 14 Jan 2001 16:58:30 -0000 1.1.1.1
+++ memory.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -43,4 +43,6 @@
#define __bus_to_virt__is_a_macro
#define __bus_to_virt(x) ((unsigned long)(x) + PAGE_OFFSET - BUS_OFFSET)
+#define PHYS_TO_NID(addr) (0)
+
#endif
Index: time.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-nexuspci/time.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- time.h 14 Jan 2001 16:58:30 -0000 1.1.1.1
+++ time.h 9 Apr 2002 12:33:09 -0000 1.2
@@ -43,7 +43,7 @@
do_timer(regs);
}
-extern __inline__ void setup_timer(void)
+static inline void setup_timer(void)
{
int tick = 3686400 / 16 / 2 / 100;
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:53
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-cl7500
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/arch-cl7500
Modified Files:
hardware.h io.h irq.h irqs.h keyboard.h memory.h system.h
time.h uncompress.h
Removed Files:
shmparam.h
Log Message:
Synch to 2.4.15 commit 1
Index: hardware.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-cl7500/hardware.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- hardware.h 14 Jan 2001 16:58:52 -0000 1.1.1.1
+++ hardware.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -49,47 +49,18 @@
#define FLUSH_BASE 0xdf000000
-
-#ifndef __ASSEMBLY__
-
-/*
- * for use with inb/outb
- */
-#define IO_VIDC_AUDIO_BASE 0x80140000
-#define IO_VIDC_BASE 0x80100000
-#define IO_IOMD_BASE 0x80080000
-#define IOC_BASE 0x80080000
-
-/*
- * IO definitions
- */
-#define EXPMASK_BASE ((volatile unsigned char *)0xe0360000)
-#define IOEB_BASE ((volatile unsigned char *)0xe0350050)
-#define PCIO_FLOPPYDMABASE ((volatile unsigned char *)0xe002a000)
+#define VIDC_BASE 0xe0400000
+#define IOMD_BASE 0xe0200000
+#define IOC_BASE 0xe0200000
+#define FLOPPYDMA_BASE 0xe002a000
#define PCIO_BASE 0xe0010000
-/* in/out bias for the ISA slot region */
-#define ISASLOT_IO 0x80400000
-
-/*
- * RAM definitions
- */
-#define GET_MEMORY_END(p) (PAGE_OFFSET + p->u1.s.page_size * \
- (p->u1.s.pages_in_bank[0] + \
- p->u1.s.pages_in_bank[1] + \
- p->u1.s.pages_in_bank[2] + \
- p->u1.s.pages_in_bank[3]))
#define FLUSH_BASE_PHYS 0x00000000 /* ROM */
-#else
+#define vidc_writel(val) __raw_writel(val, VIDC_BASE)
-#define VIDC_SND_BASE 0xe0500000
-#define VIDC_BASE 0xe0400000
-#define IOMD_BASE 0xe0200000
-#define IOC_BASE 0xe0200000
-#define PCIO_FLOPPYDMABASE 0xe002a000
-#define PCIO_BASE 0xe0010000
+/* in/out bias for the ISA slot region */
+#define ISASLOT_IO 0x80400000
-#endif
#endif
Index: io.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-cl7500/io.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- io.h 25 Feb 2001 23:14:53 -0000 1.1.1.2
+++ io.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -68,7 +68,7 @@
* Dynamic IO functions - let the compiler
* optimize the expressions
*/
-extern __inline__ void __outb (unsigned int value, unsigned int port)
+static inline void __outb (unsigned int value, unsigned int port)
{
unsigned long temp;
__asm__ __volatile__(
@@ -81,7 +81,7 @@
: "cc");
}
-extern __inline__ void __outw (unsigned int value, unsigned int port)
+static inline void __outw (unsigned int value, unsigned int port)
{
unsigned long temp;
__asm__ __volatile__(
@@ -94,7 +94,7 @@
: "cc");
}
-extern __inline__ void __outl (unsigned int value, unsigned int port)
+static inline void __outl (unsigned int value, unsigned int port)
{
unsigned long temp;
__asm__ __volatile__(
@@ -108,7 +108,7 @@
}
#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
-extern __inline__ unsigned sz __in##fnsuffix (unsigned int port) \
+static inline unsigned sz __in##fnsuffix (unsigned int port) \
{ \
unsigned long temp, value; \
__asm__ __volatile__( \
@@ -122,7 +122,7 @@
return (unsigned sz)value; \
}
-extern __inline__ unsigned int __ioaddr (unsigned int port) \
+static inline unsigned int __ioaddr (unsigned int port) \
{ \
if (__PORT_PCIO(port)) \
return (unsigned int)(PCIO_BASE + (port << 2)); \
Index: irq.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-cl7500/irq.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- irq.h 14 Jan 2001 16:58:54 -0000 1.1.1.1
+++ irq.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -2,14 +2,16 @@
* include/asm-arm/arch-cl7500/irq.h
*
* Copyright (C) 1996 Russell King
- * Copyright (C) 1999 Nexus Electronics Ltd.
+ * Copyright (C) 1999, 2001 Nexus Electronics Ltd.
*
* Changelog:
* 10-10-1996 RMK Brought up to date with arch-sa110eval
* 22-08-1998 RMK Restructured IRQ routines
* 11-08-1999 PJB Created ARM7500 version, derived from RiscPC code
*/
+
#include <asm/hardware/iomd.h>
+#include <asm/io.h>
static inline int fixup_irq(unsigned int irq)
{
@@ -19,7 +21,7 @@
printk("Spurious ISA IRQ!\n");
return irq;
}
- irq = 40;
+ irq = IRQ_ISA_BASE;
while (!(isabits & 1)) {
irq++;
isabits >>= 1;
@@ -31,161 +33,121 @@
static void cl7500_mask_irq_ack_a(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]\n"
-" strb %1, [%3]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKA)),
- "r" (ioaddr(IOMD_IRQCLRA)));
+ mask = 1 << irq;
+ val = iomd_readb(IOMD_IRQMASKA);
+ iomd_writeb(val & ~mask, IOMD_IRQMASKA);
+ iomd_writeb(mask, IOMD_IRQCLRA);
}
static void cl7500_mask_irq_a(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKA)));
+ mask = 1 << irq;
+ val = iomd_readb(IOMD_IRQMASKA);
+ iomd_writeb(val & ~mask, IOMD_IRQMASKA);
}
static void cl7500_unmask_irq_a(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" orr %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKA)));
+ mask = 1 << irq;
+ val = iomd_readb(IOMD_IRQMASKA);
+ iomd_writeb(val | mask, IOMD_IRQMASKA);
}
static void cl7500_mask_irq_b(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKB)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_IRQMASKB);
+ iomd_writeb(val & ~mask, IOMD_IRQMASKB);
}
static void cl7500_unmask_irq_b(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" orr %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKB)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_IRQMASKB);
+ iomd_writeb(val | mask, IOMD_IRQMASKB);
}
static void cl7500_mask_irq_c(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKC)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_IRQMASKC);
+ iomd_writeb(val & ~mask, IOMD_IRQMASKC);
}
static void cl7500_unmask_irq_c(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" orr %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKC)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_IRQMASKC);
+ iomd_writeb(val | mask, IOMD_IRQMASKC);
}
static void cl7500_mask_irq_d(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKD)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_IRQMASKD);
+ iomd_writeb(val & ~mask, IOMD_IRQMASKD);
}
static void cl7500_unmask_irq_d(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" orr %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_IRQMASKD)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_IRQMASKD);
+ iomd_writeb(val | mask, IOMD_IRQMASKD);
}
static void cl7500_mask_irq_dma(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_DMAMASK)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_DMAMASK);
+ iomd_writeb(val & ~mask, IOMD_DMAMASK);
}
static void cl7500_unmask_irq_dma(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" orr %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_DMAMASK)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_DMAMASK);
+ iomd_writeb(val | mask, IOMD_DMAMASK);
}
static void cl7500_mask_irq_fiq(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_FIQMASK)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_FIQMASK);
+ iomd_writeb(val & ~mask, IOMD_FIQMASK);
}
static void cl7500_unmask_irq_fiq(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" orr %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOMD_FIQMASK)));
+ mask = 1 << (irq & 7);
+ val = iomd_readb(IOMD_FIQMASK);
+ iomd_writeb(val | mask, IOMD_FIQMASK);
}
static void no_action(int cpl, void *dev_id, struct pt_regs *regs)
@@ -196,14 +158,12 @@
static __inline__ void irq_init_irq(void)
{
- extern void ecard_disableirq(unsigned int irq);
- extern void ecard_enableirq(unsigned int irq);
int irq;
- outb(0, IOMD_IRQMASKA);
- outb(0, IOMD_IRQMASKB);
- outb(0, IOMD_FIQMASK);
- outb(0, IOMD_DMAMASK);
+ iomd_writeb(0, IOMD_IRQMASKA);
+ iomd_writeb(0, IOMD_IRQMASKB);
+ iomd_writeb(0, IOMD_FIQMASK);
+ iomd_writeb(0, IOMD_DMAMASK);
for (irq = 0; irq < NR_IRQS; irq++) {
switch (irq) {
@@ -239,14 +199,14 @@
irq_desc[irq].unmask = cl7500_unmask_irq_c;
break;
- case 32 ... 39:
+ case 40 ... 47:
irq_desc[irq].valid = 1;
irq_desc[irq].mask_ack = cl7500_mask_irq_d;
irq_desc[irq].mask = cl7500_mask_irq_d;
irq_desc[irq].unmask = cl7500_unmask_irq_d;
break;
- case 40 ... 47:
+ case 48 ... 55:
irq_desc[irq].valid = 1;
irq_desc[irq].probe_ok = 1;
irq_desc[irq].mask_ack = no_action;
Index: irqs.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-cl7500/irqs.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- irqs.h 25 Feb 2001 23:14:53 -0000 1.1.1.2
+++ irqs.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -35,20 +35,22 @@
#define IRQ_IOP5 29
#define IRQ_IOP6 30
#define IRQ_IOP7 31
-#define IRQ_MOUSERX 32
-#define IRQ_MOUSETX 33
-#define IRQ_ADC 34
-#define IRQ_EVENT1 35
-#define IRQ_EVENT2 36
-#define IRQ_ISA_3 40
-#define IRQ_ISA_4 41
-#define IRQ_ISA_5 42
-#define IRQ_ISA_7 43
-#define IRQ_ISA_9 44
-#define IRQ_ISA_10 45
-#define IRQ_ISA_11 46
-#define IRQ_ISA_14 47
+#define IRQ_MOUSERX 40
+#define IRQ_MOUSETX 41
+#define IRQ_ADC 42
+#define IRQ_EVENT1 43
+#define IRQ_EVENT2 44
+
+#define IRQ_ISA_BASE 48
+#define IRQ_ISA_3 48
+#define IRQ_ISA_4 49
+#define IRQ_ISA_5 50
+#define IRQ_ISA_7 51
+#define IRQ_ISA_9 52
+#define IRQ_ISA_10 53
+#define IRQ_ISA_11 54
+#define IRQ_ISA_14 55
#define FIQ_INT9 0
#define FIQ_INT5 1
Index: keyboard.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-cl7500/keyboard.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- keyboard.h 14 Jan 2001 16:58:54 -0000 1.1.1.1
+++ keyboard.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -4,26 +4,12 @@
*
* Keyboard driver definitions for CL7500 architecture
*
- * (C) 1998 Russell King
+ * Copyright (C) 1998-2001 Russell King
*/
-
-#include <asm/irq.h>
-
#define NR_SCANCODES 128
-extern void ps2kbd_leds(unsigned char leds);
-extern void ps2kbd_init_hw(void);
-extern unsigned char ps2kbd_sysrq_xlate[NR_SCANCODES];
-
-#define kbd_setkeycode(sc,kc) (-EINVAL)
-#define kbd_getkeycode(sc) (-EINVAL)
-
-#define kbd_translate(sc, kcp, rm) ({ *(kcp) = (sc); 1; })
-#define kbd_unexpected_up(kc) (0200)
-#define kbd_leds(leds) ps2kbd_leds(leds)
-#define kbd_init_hw() ps2kbd_init_hw()
-#define kbd_sysrq_xlate ps2kbd_sysrq_xlate
-#define kbd_disable_irq() disable_irq(IRQ_KEYBOARDRX)
-#define kbd_enable_irq() enable_irq(IRQ_KEYBOARDRX)
+extern int ps2kbd_init_hw(void);
-#define SYSRQ_KEY 13
+#define kbd_disable_irq() disable_irq(IRQ_KEYBOARDRX)
+#define kbd_enable_irq() enable_irq(IRQ_KEYBOARDRX)
+#define kbd_init_hw() ps2kbd_init_hw()
Index: memory.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-cl7500/memory.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- memory.h 14 Jan 2001 16:58:54 -0000 1.1.1.1
+++ memory.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -46,4 +46,6 @@
#define __bus_to_virt__is_a_macro
#define __bus_to_virt(x) __phys_to_virt(x)
+#define PHYS_TO_NID(addr) (0)
+
#endif
Index: system.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-cl7500/system.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- system.h 14 Jan 2001 16:58:55 -0000 1.1.1.1
+++ system.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -11,12 +11,12 @@
static void arch_idle(void)
{
while (!current->need_resched && !hlt_counter)
- outb(0, IOMD_SUSMODE);
+ iomd_writeb(0, IOMD_SUSMODE);
}
#define arch_reset(mode) \
do { \
- outb (0, IOMD_ROMCR0); \
+ iomd_writeb(0, IOMD_ROMCR0); \
cpu_reset(0); \
} while (0);
Index: time.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-cl7500/time.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- time.h 14 Jan 2001 16:58:55 -0000 1.1.1.1
+++ time.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -13,25 +13,27 @@
{
do_timer(regs);
do_set_rtc();
+ do_profile(regs);
{
/* Twinkle the lights. */
- static int count, state = 0xff;
+ static int count, state = 0xff00;
if (count-- == 0) {
- state ^= 1;
+ state ^= 0x100;
count = 25;
- *((volatile unsigned int *)(0xe002ba00)) = state;
+ *((volatile unsigned int *)LED_ADDRESS) = state;
}
}
-
- do_profile(regs);
}
/*
* Set up timer interrupt.
*/
-extern __inline__ void setup_timer(void)
+static inline void setup_timer(void)
{
+ extern void ioctime_init(void);
+ ioctime_init();
+
timer_irq.handler = timer_interrupt;
setup_arm_irq(IRQ_TIMER, &timer_irq);
Index: uncompress.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-cl7500/uncompress.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- uncompress.h 14 Jan 2001 16:58:55 -0000 1.1.1.1
+++ uncompress.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -1,11 +1,11 @@
/*
* linux/include/asm-arm/arch-cl7500/uncompress.h
*
- * Copyright (C) 1999 Nexus Electronics Ltd.
+ * Copyright (C) 1999, 2000 Nexus Electronics Ltd.
*/
#define BASE 0x03010000
-#define SERBASE (BASE + (0x3f8 << 2))
+#define SERBASE (BASE + (0x2f8 << 2))
static __inline__ void putc(char c)
{
--- shmparam.h DELETED ---
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:51
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-arc
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/arch-arc
Modified Files:
hardware.h io.h irq.h keyboard.h memory.h system.h time.h
Log Message:
Synch to 2.4.15 commit 1
Index: hardware.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-arc/hardware.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- hardware.h 14 Jan 2001 16:58:25 -0000 1.1.1.1
+++ hardware.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -46,23 +46,29 @@
#define SCREEN_BASE 0x02000000
+#define EXPMASK_BASE 0x03360000
+#define IOEB_BASE 0x03350000
+#define VIDC_BASE 0x03400000
+#define LATCHA_BASE 0x03250040
+#define LATCHB_BASE 0x03250018
+#define IOC_BASE 0x03200000
+#define FLOPPYDMA_BASE 0x0302a000
+#define PCIO_BASE 0x03010000
+
+#define vidc_writel(val) __raw_writel(val, VIDC_BASE)
+
#ifndef __ASSEMBLY__
/*
* for use with inb/outb
*/
-#define IO_VIDC_BASE 0x80100000
#ifdef CONFIG_ARCH_A5K
-#define IOEB_VID_CTL 0x800d4012
-#define IOEB_PRESENT 0x800d4014
-#define IOEB_PSCLR 0x800d4016
-#define IOEB_MONTYPE 0x800d401c
+#define IOEB_VID_CTL (IOEB_BASE + 0x48)
+#define IOEB_PRESENT (IOEB_BASE + 0x50)
+#define IOEB_PSCLR (IOEB_BASE + 0x58)
+#define IOEB_MONTYPE (IOEB_BASE + 0x70)
#endif
-#define LATCHAADDR 0x80094010
-#define LATCHBADDR 0x80094006
-#define IOC_BASE 0x80080000
-#define IO_EC_IOC4_BASE 0x8009c000
#define IO_EC_IOC_BASE 0x80090000
#define IO_EC_MEMC_BASE 0x80000000
@@ -74,36 +80,9 @@
#define SCSI_BASE 0x03100000
#endif
-/*
- * IO definitions
- */
-#define EXPMASK_BASE ((volatile unsigned char *)0x03360000)
-#define IOEB_BASE ((volatile unsigned char *)0x03350050)
-#define PCIO_FLOPPYDMABASE ((volatile unsigned char *)0x0302a000)
-#define PCIO_BASE 0x03010000
-
-/*
- * RAM definitions
- */
-#define GET_MEMORY_END(p) (PAGE_OFFSET + (p->u1.s.page_size) * (p->u1.s.nr_pages))
-#define PARAMS_OFFSET 0x7c000
-
-#else
-
-#define IOEB_BASE 0x03350050
-#define IOC_BASE 0x03200000
-#define PCIO_FLOPPYDMABASE 0x0302a000
-#define PCIO_BASE 0x03010000
-
-#endif
-
-#ifndef __ASSEMBLY__
-#define __EXPMASK(offset) (((volatile unsigned char *)EXPMASK_BASE)[offset])
-#else
-#define __EXPMASK(offset) offset
#endif
-#define EXPMASK_STATUS __EXPMASK(0x00)
-#define EXPMASK_ENABLE __EXPMASK(0x04)
+#define EXPMASK_STATUS (EXPMASK_BASE + 0x00)
+#define EXPMASK_ENABLE (EXPMASK_BASE + 0x04)
#endif
Index: io.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-arc/io.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- io.h 25 Feb 2001 23:14:53 -0000 1.1.1.2
+++ io.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -71,7 +71,7 @@
* Dynamic IO functions - let the compiler
* optimize the expressions
*/
-extern __inline__ void __outb (unsigned int value, unsigned int port)
+static inline void __outb (unsigned int value, unsigned int port)
{
unsigned long temp;
__asm__ __volatile__(
@@ -84,7 +84,7 @@
: "cc");
}
-extern __inline__ void __outw (unsigned int value, unsigned int port)
+static inline void __outw (unsigned int value, unsigned int port)
{
unsigned long temp;
__asm__ __volatile__(
@@ -97,7 +97,7 @@
: "cc");
}
-extern __inline__ void __outl (unsigned int value, unsigned int port)
+static inline void __outl (unsigned int value, unsigned int port)
{
unsigned long temp;
__asm__ __volatile__(
@@ -111,7 +111,7 @@
}
#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
-extern __inline__ unsigned sz __in##fnsuffix (unsigned int port) \
+static inline unsigned sz __in##fnsuffix (unsigned int port) \
{ \
unsigned long temp, value; \
__asm__ __volatile__( \
@@ -125,7 +125,7 @@
return (unsigned sz)value; \
}
-extern __inline__ unsigned int __ioaddr (unsigned int port) \
+static inline unsigned int __ioaddr (unsigned int port) \
{ \
if (__PORT_PCIO(port)) \
return (unsigned int)(PCIO_BASE + (port << 2)); \
Index: irq.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-arc/irq.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- irq.h 14 Jan 2001 16:58:26 -0000 1.1.1.1
+++ irq.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -16,6 +16,7 @@
*/
#include <linux/config.h>
#include <asm/hardware/ioc.h>
+#include <asm/io.h>
#ifdef CONFIG_ARCH_ARC
#define a_clf() clf()
@@ -29,105 +30,81 @@
static void arc_mask_irq_ack_a(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
+ mask = 1 << irq;
a_clf();
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]\n"
-" strb %1, [%3]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOC_IRQMASKA)),
- "r" (ioaddr(IOC_IRQCLRA)));
+ val = ioc_readb(IOC_IRQMASKA);
+ ioc_writeb(val & ~mask, IOC_IRQMASKA);
+ ioc_writeb(mask, IOC_IRQCLRA);
a_stf();
}
static void arc_mask_irq_a(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
+ mask = 1 << irq;
a_clf();
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOC_IRQMASKA)));
+ val = ioc_readb(IOC_IRQMASKA);
+ ioc_writeb(val & ~mask, IOC_IRQMASKA);
a_stf();
}
static void arc_unmask_irq_a(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
+ mask = 1 << irq;
a_clf();
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" orr %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOC_IRQMASKA)));
+ val = ioc_readb(IOC_IRQMASKA);
+ ioc_writeb(val | mask, IOC_IRQMASKA);
a_stf();
}
static void arc_mask_irq_b(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOC_IRQMASKB)));
+ mask = 1 << (irq & 7);
+ val = ioc_readb(IOC_IRQMASKB);
+ ioc_writeb(val & ~mask, IOC_IRQMASKB);
}
static void arc_unmask_irq_b(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" orr %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOC_IRQMASKB)));
+ mask = 1 << (irq & 7);
+ val = ioc_readb(IOC_IRQMASKB);
+ ioc_writeb(val | mask, IOC_IRQMASKB);
}
static void arc_mask_irq_fiq(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" bic %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOC_FIQMASK)));
+ mask = 1 << (irq & 7);
+ val = ioc_readb(IOC_FIQMASK);
+ ioc_writeb(val & ~mask, IOC_FIQMASK);
}
static void arc_unmask_irq_fiq(unsigned int irq)
{
- unsigned int temp;
+ unsigned int val, mask;
- __asm__ __volatile__(
- "ldrb %0, [%2]\n"
-" orr %0, %0, %1\n"
-" strb %0, [%2]"
- : "=&r" (temp)
- : "r" (1 << (irq & 7)), "r" (ioaddr(IOC_FIQMASK)));
+ mask = 1 << (irq & 7);
+ val = ioc_readb(IOC_FIQMASK);
+ ioc_writeb(val | mask, IOC_FIQMASK);
}
static __inline__ void irq_init_irq(void)
{
- extern void ecard_disableirq(unsigned int irq);
- extern void ecard_enableirq(unsigned int irq);
int irq;
- outb(0, IOC_IRQMASKA);
- outb(0, IOC_IRQMASKB);
- outb(0, IOC_FIQMASK);
+ ioc_writeb(0, IOC_IRQMASKA);
+ ioc_writeb(0, IOC_IRQMASKB);
+ ioc_writeb(0, IOC_FIQMASK);
for (irq = 0; irq < NR_IRQS; irq++) {
switch (irq) {
@@ -154,13 +131,6 @@
irq_desc[irq].mask_ack = arc_mask_irq_b;
irq_desc[irq].mask = arc_mask_irq_b;
irq_desc[irq].unmask = arc_unmask_irq_b;
- break;
-
- case 32 ... 40:
- irq_desc[irq].valid = 1;
- irq_desc[irq].mask_ack = ecard_disableirq;
- irq_desc[irq].mask = ecard_disableirq;
- irq_desc[irq].unmask = ecard_enableirq;
break;
case 64 ... 72:
Index: keyboard.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-arc/keyboard.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- keyboard.h 14 Jan 2001 16:58:26 -0000 1.1.1.1
+++ keyboard.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -1,7 +1,7 @@
/*
* linux/include/asm-arm/arch-arc/keyboard.h
*
- * Copyright (C) 1998 Russell King
+ * Copyright (C) 1998-2001 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -10,24 +10,12 @@
* Keyboard driver definitions for Acorn Archimedes/A5000
* architecture
*/
-
#include <asm/irq.h>
#define NR_SCANCODES 128
-extern void a5kkbd_leds(unsigned char leds);
extern void a5kkbd_init_hw(void);
-extern unsigned char a5kkbd_sysrq_xlate[NR_SCANCODES];
-
-#define kbd_setkeycode(sc,kc) (-EINVAL)
-#define kbd_getkeycode(sc) (-EINVAL)
-
-#define kbd_translate(sc, kcp, rm) ({ *(kcp) = (sc); 1; })
-#define kbd_unexpected_up(kc) (0200)
-#define kbd_leds(leds) a5kkbd_leds(leds)
-#define kbd_init_hw() a5kkbd_init_hw()
-#define kbd_sysrq_xlate a5kkbd_sysrq_xlate
-#define kbd_disable_irq() disable_irq(IRQ_KEYBOARDRX)
-#define kbd_enable_irq() enable_irq(IRQ_KEYBOARDRX)
-#define SYSRQ_KEY 13
+#define kbd_disable_irq() disable_irq(IRQ_KEYBOARDRX)
+#define kbd_enable_irq() enable_irq(IRQ_KEYBOARDRX)
+#define kbd_init_hw() a5kkbd_init_hw()
Index: memory.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-arc/memory.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- memory.h 14 Jan 2001 16:58:26 -0000 1.1.1.1
+++ memory.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -50,4 +50,6 @@
#define __bus_to_virt__is_a_macro
#define __bus_to_virt(x) (x)
+#define PHYS_TO_NID(addr) (0)
+
#endif
Index: system.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-arc/system.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- system.h 14 Jan 2001 16:58:24 -0000 1.1.1.1
+++ system.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -13,15 +13,8 @@
while (!current->need_resched && !hlt_counter);
}
-extern __inline__ void arch_reset(char mode)
+static inline void arch_reset(char mode)
{
- extern void ecard_reset(int card);
-
- /*
- * Reset all expansion cards.
- */
- ecard_reset(-1);
-
/*
* copy branch instruction to reset location and call it
*/
Index: time.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-arc/time.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- time.h 14 Jan 2001 16:58:26 -0000 1.1.1.1
+++ time.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -24,7 +24,7 @@
/*
* Set up timer interrupt.
*/
-extern __inline__ void setup_timer(void)
+static inline void setup_timer(void)
{
ioctime_init();
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:50
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa285
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-arm/arch-ebsa285
Modified Files:
io.h irq.h keyboard.h memory.h system.h time.h
Log Message:
Synch to 2.4.15 commit 1
Index: io.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa285/io.h,v
retrieving revision 1.1.1.2
retrieving revision 1.2
diff -u -r1.1.1.2 -r1.2
--- io.h 25 Feb 2001 23:14:53 -0000 1.1.1.2
+++ io.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -25,14 +25,14 @@
#define __mem_isa(a) (PCIMEM_BASE + (unsigned long)(a))
#else
-extern __inline__ unsigned long ___mem_pci(unsigned long a)
+static inline unsigned long ___mem_pci(unsigned long a)
{
if (a <= 0xc0000000 || a >= 0xe0000000)
BUG();
return a;
}
-extern __inline__ unsigned long ___mem_isa(unsigned long a)
+static inline unsigned long ___mem_isa(unsigned long a)
{
if (a >= 16*1048576)
BUG();
@@ -48,16 +48,7 @@
#define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
-#include <asm/hardware/dec21285.h>
-
-/*
- * ioremap support - validate a PCI memory address,
- * and convert a PCI memory address to a physical
- * address for the page tables.
- */
-#define iomem_valid_addr(iomem,sz) \
- ((iomem) < 0x80000000 && (iomem) + (sz) <= 0x80000000)
-
-#define iomem_to_phys(iomem) ((iomem) + DC21285_PCI_MEM)
+#define iomem_valid_addr(iomem,sz) (1)
+#define iomem_to_phys(iomem) (iomem)
#endif
Index: irq.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa285/irq.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- irq.h 14 Jan 2001 16:58:38 -0000 1.1.1.1
+++ irq.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -19,34 +19,7 @@
#include <asm/irq.h>
#include <asm/mach-types.h>
-/*
- * Footbridge IRQ translation table
- * Converts from our IRQ numbers into FootBridge masks
- */
-static const int dc21285_irq_mask[] = {
- IRQ_MASK_UART_RX, /* 0 */
- IRQ_MASK_UART_TX, /* 1 */
- IRQ_MASK_TIMER1, /* 2 */
- IRQ_MASK_TIMER2, /* 3 */
- IRQ_MASK_TIMER3, /* 4 */
- IRQ_MASK_IN0, /* 5 */
- IRQ_MASK_IN1, /* 6 */
- IRQ_MASK_IN2, /* 7 */
- IRQ_MASK_IN3, /* 8 */
- IRQ_MASK_DOORBELLHOST, /* 9 */
- IRQ_MASK_DMA1, /* 10 */
- IRQ_MASK_DMA2, /* 11 */
- IRQ_MASK_PCI, /* 12 */
- IRQ_MASK_SDRAMPARITY, /* 13 */
- IRQ_MASK_I2OINPOST, /* 14 */
- IRQ_MASK_PCI_ABORT, /* 15 */
- IRQ_MASK_PCI_SERR, /* 16 */
- IRQ_MASK_DISCARD_TIMER, /* 17 */
- IRQ_MASK_PCI_DPERR, /* 18 */
- IRQ_MASK_PCI_PERR, /* 19 */
-};
-
-static int isa_irq = -1;
+int isa_irq = -1;
static inline int fixup_irq(unsigned int irq)
{
@@ -58,166 +31,3 @@
return irq;
}
-static void dc21285_mask_irq(unsigned int irq)
-{
- *CSR_IRQ_DISABLE = dc21285_irq_mask[_DC21285_INR(irq)];
-}
-
-static void dc21285_unmask_irq(unsigned int irq)
-{
- *CSR_IRQ_ENABLE = dc21285_irq_mask[_DC21285_INR(irq)];
-}
-
-static void isa_mask_pic_lo_irq(unsigned int irq)
-{
- unsigned int mask = 1 << (irq & 7);
-
- outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO);
-}
-
-static void isa_mask_ack_pic_lo_irq(unsigned int irq)
-{
- unsigned int mask = 1 << (irq & 7);
-
- outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO);
- outb(0x20, PIC_LO);
-}
-
-static void isa_unmask_pic_lo_irq(unsigned int irq)
-{
- unsigned int mask = 1 << (irq & 7);
-
- outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO);
-}
-
-static void isa_mask_pic_hi_irq(unsigned int irq)
-{
- unsigned int mask = 1 << (irq & 7);
-
- outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI);
-}
-
-static void isa_mask_ack_pic_hi_irq(unsigned int irq)
-{
- unsigned int mask = 1 << (irq & 7);
-
- outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI);
- outb(0x62, PIC_LO);
- outb(0x20, PIC_HI);
-}
-
-static void isa_unmask_pic_hi_irq(unsigned int irq)
-{
- unsigned int mask = 1 << (irq & 7);
-
- outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI);
-}
-
-static void no_action(int cpl, void *dev_id, struct pt_regs *regs)
-{
-}
-
-static struct irqaction irq_cascade = { no_action, 0, 0, "cascade", NULL, NULL };
-static struct resource pic1_resource = { "pic1", 0x20, 0x3f };
-static struct resource pic2_resource = { "pic2", 0xa0, 0xbf };
-
-static __inline__ void irq_init_irq(void)
-{
- int irq;
-
- /*
- * setup DC21285 IRQs
- */
- *CSR_IRQ_DISABLE = -1;
- *CSR_FIQ_DISABLE = -1;
-
- for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
- irq_desc[irq].valid = 1;
- irq_desc[irq].probe_ok = 1;
- irq_desc[irq].mask_ack = dc21285_mask_irq;
- irq_desc[irq].mask = dc21285_mask_irq;
- irq_desc[irq].unmask = dc21285_unmask_irq;
- }
-
- /*
- * Determine the ISA settings for
- * the machine we're running on.
- */
- isa_irq = -1;
-
- if (footbridge_cfn_mode()) {
- if (machine_is_ebsa285())
- /* The following is dependent on which slot
- * you plug the Southbridge card into. We
- * currently assume that you plug it into
- * the right-hand most slot.
- */
- isa_irq = IRQ_PCI;
-
- if (machine_is_cats())
- isa_irq = IRQ_IN2;
-
- if (machine_is_netwinder())
- isa_irq = IRQ_IN3;
- }
-
- if (isa_irq != -1) {
- /*
- * Setup, and then probe for an ISA PIC
- * If the PIC is not there, then we
- * ignore the PIC.
- */
- outb(0x11, PIC_LO);
- outb(_ISA_IRQ(0), PIC_MASK_LO); /* IRQ number */
- outb(0x04, PIC_MASK_LO); /* Slave on Ch2 */
- outb(0x01, PIC_MASK_LO); /* x86 */
- outb(0xf5, PIC_MASK_LO); /* pattern: 11110101 */
-
- outb(0x11, PIC_HI);
- outb(_ISA_IRQ(8), PIC_MASK_HI); /* IRQ number */
- outb(0x02, PIC_MASK_HI); /* Slave on Ch1 */
- outb(0x01, PIC_MASK_HI); /* x86 */
- outb(0xfa, PIC_MASK_HI); /* pattern: 11111010 */
-
- outb(0x0b, PIC_LO);
- outb(0x0b, PIC_HI);
-
- if (inb(PIC_MASK_LO) == 0xf5 && inb(PIC_MASK_HI) == 0xfa) {
- outb(0xff, PIC_MASK_LO);/* mask all IRQs */
- outb(0xff, PIC_MASK_HI);/* mask all IRQs */
- } else
- isa_irq = -1;
- }
-
- if (isa_irq != -1) {
- for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
- irq_desc[irq].valid = 1;
- irq_desc[irq].probe_ok = 1;
- irq_desc[irq].mask_ack = isa_mask_ack_pic_lo_irq;
- irq_desc[irq].mask = isa_mask_pic_lo_irq;
- irq_desc[irq].unmask = isa_unmask_pic_lo_irq;
- }
-
- for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
- irq_desc[irq].valid = 1;
- irq_desc[irq].probe_ok = 1;
- irq_desc[irq].mask_ack = isa_mask_ack_pic_hi_irq;
- irq_desc[irq].mask = isa_mask_pic_hi_irq;
- irq_desc[irq].unmask = isa_unmask_pic_hi_irq;
- }
-
- request_resource(&ioport_resource, &pic1_resource);
- request_resource(&ioport_resource, &pic2_resource);
- setup_arm_irq(IRQ_ISA_CASCADE, &irq_cascade);
- setup_arm_irq(isa_irq, &irq_cascade);
-
- /*
- * On the NetWinder, don't automatically
- * enable ISA IRQ11 when it is requested.
- * There appears to be a missing pull-up
- * resistor on this line.
- */
- if (machine_is_netwinder())
- irq_desc[_ISA_IRQ(11)].noautoenable = 1;
- }
-}
Index: keyboard.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa285/keyboard.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- keyboard.h 14 Jan 2001 16:58:36 -0000 1.1.1.1
+++ keyboard.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -3,13 +3,19 @@
*
* Keyboard driver definitions for EBSA285 architecture
*
- * (C) 1998 Russell King
+ * Copyright (C) 1998-2001 Russell King
* (C) 1998 Phil Blundell
*/
#include <linux/ioport.h>
#include <asm/irq.h>
#include <asm/system.h>
+#define KEYBOARD_IRQ IRQ_ISA_KEYBOARD
+#define NR_SCANCODES 128
+
+#define kbd_disable_irq() do { } while (0)
+#define kbd_enable_irq() do { } while (0)
+
extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
extern int pckbd_getkeycode(unsigned int scancode);
extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
@@ -19,55 +25,26 @@
extern void pckbd_init_hw(void);
extern unsigned char pckbd_sysrq_xlate[128];
-#define KEYBOARD_IRQ IRQ_ISA_KEYBOARD
-
-#define NR_SCANCODES 128
+static inline void kbd_init_hw(void)
+{
+ if (have_isa_bridge) {
+ k_setkeycode = pckbd_setkeycode;
+ k_getkeycode = pckbd_getkeycode;
+ k_translate = pckbd_translate;
+ k_unexpected_up = pckbd_unexpected_up;
+ k_leds = pckbd_leds;
+#ifdef CONFIG_MAGIC_SYSRQ
+ k_sysrq_key = 0x54;
+ k_sysrq_xlate = pckbd_sysrq_xlate;
+#endif
+ pckbd_init_hw();
+ }
+}
-#define kbd_setkeycode(sc,kc) \
- ({ \
- int __ret; \
- if (have_isa_bridge) \
- __ret = pckbd_setkeycode(sc,kc);\
- else \
- __ret = -EINVAL; \
- __ret; \
- })
-
-#define kbd_getkeycode(sc) \
- ({ \
- int __ret; \
- if (have_isa_bridge) \
- __ret = pckbd_getkeycode(sc); \
- else \
- __ret = -EINVAL; \
- __ret; \
- })
-
-#define kbd_translate(sc, kcp, rm) \
- ({ \
- pckbd_translate(sc, kcp, rm); \
- })
-
-#define kbd_unexpected_up pckbd_unexpected_up
-
-#define kbd_leds(leds) \
- do { \
- if (have_isa_bridge) \
- pckbd_leds(leds); \
- } while (0)
-
-#define kbd_init_hw() \
- do { \
- if (have_isa_bridge) \
- pckbd_init_hw(); \
- } while (0)
-#define kbd_sysrq_xlate pckbd_sysrq_xlate
-
-#define kbd_disable_irq()
-#define kbd_enable_irq()
-
-#define SYSRQ_KEY 0x54
+/*
+ * The rest of this file is to do with supporting pc_keyb.c
+ */
/* resource allocation */
#define kbd_request_region() request_region(0x60, 16, "keyboard")
Index: memory.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa285/memory.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- memory.h 14 Jan 2001 16:58:40 -0000 1.1.1.1
+++ memory.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -80,4 +80,6 @@
#define __phys_to_virt__is_a_macro
#define __phys_to_virt(ppage) ((unsigned long)(ppage) + PAGE_OFFSET)
+#define PHYS_TO_NID(addr) (0)
+
#endif
Index: system.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa285/system.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- system.h 14 Jan 2001 16:58:37 -0000 1.1.1.1
+++ system.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -35,7 +35,7 @@
slow_out:
}
-extern __inline__ void arch_reset(char mode)
+static inline void arch_reset(char mode)
{
if (mode == 's') {
/*
@@ -63,14 +63,24 @@
*/
outb(0xc4, 0x338);
} else {
- /* To reboot, we set up the 21285 watchdog and
- * enable it. We then wait for it to timeout.
+ /*
+ * Force the watchdog to do a CPU reset.
+ *
+ * After making sure that the watchdog is disabled
+ * (so we can change the timer registers) we first
+ * enable the timer to autoreload itself. Next, the
+ * timer interval is set really short and any
+ * current interrupt request is cleared (so we can
+ * see an edge transition). Finally, TIMER4 is
+ * enabled as the watchdog.
*/
- *CSR_TIMER4_LOAD = 0x8000;
+ *CSR_SA110_CNTL &= ~(1 << 13);
*CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
TIMER_CNTL_AUTORELOAD |
TIMER_CNTL_DIV16;
- *CSR_SA110_CNTL |= 1 << 13;
+ *CSR_TIMER4_LOAD = 0x2;
+ *CSR_TIMER4_CLR = 0;
+ *CSR_SA110_CNTL |= (1 << 13);
}
}
}
Index: time.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-arm/arch-ebsa285/time.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -r1.1.1.1 -r1.2
--- time.h 14 Jan 2001 16:58:39 -0000 1.1.1.1
+++ time.h 9 Apr 2002 12:33:08 -0000 1.2
@@ -199,7 +199,7 @@
/*
* Set up timer interrupt.
*/
-extern __inline__ void setup_timer(void)
+static inline void setup_timer(void)
{
int irq;
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:37
|
Update of /cvsroot/linux-vax/kernel-2.4/drivers/scsi/sym53c8xx_2 In directory usw-pr-cvs1:/tmp/cvs-serv14745/drivers/scsi/sym53c8xx_2 Log Message: Directory /cvsroot/linux-vax/kernel-2.4/drivers/scsi/sym53c8xx_2 added to the repository |
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:35
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-vax/mm
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-vax/mm
Modified Files:
pagelet.h pagelet_pgd.h pagelet_pmd.h pagelet_pte.h pgalloc.h
pgtable.h task.h
Log Message:
Synch to 2.4.15 commit 1
Index: pagelet.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-vax/mm/pagelet.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -r1.3 -r1.4
--- pagelet.h 31 Jul 2001 17:33:26 -0000 1.3
+++ pagelet.h 9 Apr 2002 12:33:20 -0000 1.4
@@ -5,7 +5,9 @@
* the upper layers idea of the PAGE_SIZE (4k) and the Hardware's
* idea of PAGE_SIZE (512bytes).
*
- * Copyright atp 1998-2001. Integrated with 2.4 tree Jan 2001
+ * Copyright atp 1998-2002.
+ * Jan 2001 atp Integrated with 2.4 tree
+ * Mar 2002 atp Updates to deal with pmd_populate/pgd_populate in 2.4.3
*/
@@ -69,26 +71,35 @@
* as a pseudo pgd.
* note, the length register here is 1/8th of the real (processor)
* length register
+ *
+ * IMPORTANT NOTE
+ * --------------
+ * if you change this structure, you will need to recalculate
+ * the offsets in asm/mm/pgtable.h which are used in
+ * arch/vax/boot/head.S (ASM_SBR_OFFSET and ASM_SLR_OFFSET)
*/
-struct vax_pgd_descriptor {
+
+/* definition of pmd_t - needed for pgd_t */
+typedef struct {
+ unsigned long pmd;
+} pmd_t;
+
+
+struct pgd_descriptor {
unsigned long br;
unsigned long lr;
- unsigned long pmd; /* first four pages of the task PTE slot are the pmds
- * There are two pmd's one for p0 and one for p1 */
- unsigned long pmd2; /* This is just a place holder, as we pretend that
- * our pmds hold 2048 entries and are 2 pages long */
+ pmd_t *pmd; /* first four pages of the task PTE slot are the pmds
+ * Our pmds hold 2048 entries and are 2 pages long */
unsigned long slot; /* the base address of this slot */
unsigned long segment; /* The segment index - used in pgd_clear */
};
/* pgd_t definitions */
-typedef struct vax_pgd_descriptor pgd_t;
+typedef struct pgd_descriptor pgd_t;
/* the .pmd is not a typo */
#define pgd_val(x) ((x).pmd)
#define __pgd(x) ((pgd_t) { (x) } )
-/* definition of pmd_t */
-typedef struct { unsigned long pmd; } pmd_t;
#define pmd_val(x) ((x).pmd)
#define __pmd(x) ((pmd_t) { (x) } )
Index: pagelet_pgd.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-vax/mm/pagelet_pgd.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -r1.2 -r1.3
--- pagelet_pgd.h 31 Jul 2001 17:33:26 -0000 1.2
+++ pagelet_pgd.h 9 Apr 2002 12:33:20 -0000 1.3
@@ -45,9 +45,9 @@
* into the pgd entry)
* All the actual stuff is done by the pmd_xxx functions
*/
-extern inline int pgd_none(pgd_t pgd) { return !(pgd).pmd; }
-extern inline int pgd_bad(pgd_t pgd) { return !(pgd).br; }
-extern inline int pgd_present(pgd_t pgd) { return ((pgd).pmd != 0); }
+static inline int pgd_none(pgd_t pgd) { return !(pgd).pmd; }
+static inline int pgd_bad(pgd_t pgd) { return !(pgd).br; }
+static inline int pgd_present(pgd_t pgd) { return ((pgd).pmd != 0); }
extern void pgd_clear(pgd_t * pgdp);
Index: pagelet_pmd.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-vax/mm/pagelet_pmd.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -r1.3 -r1.4
--- pagelet_pmd.h 31 Jul 2001 17:33:26 -0000 1.3
+++ pagelet_pmd.h 9 Apr 2002 12:33:20 -0000 1.4
@@ -5,6 +5,7 @@
*
* Copyright atp Jan 2001.
* atp Jul 2001. Go to a fake 3 level.
+ * atp Feb 2002. Add in pmd_populate needed for 2.4.3 changes to mm.
*/
@@ -34,30 +35,33 @@
/*
* we dont want linux mucking about with our pmd pages. It will get it
* wrong. pmd_alloc and pmd_free do the business there.
+ *
+ * Changes for 2.4.3 and above. pmd_alloc is no more. we have pgd
+ * and pmd_populate now.
+ * -- Change to a pmd that is a two page block of memeory.
+ * -- remove special flag.
*/
#define set_pmd(pmdptr, pmdval)
-/* Fixme:, check the length as well as the base register. */
-extern inline int pmd_none(pmd_t pmd)
+static inline int pmd_none(pmd_t pmd)
{
- if (pmd_val(pmd) & 0x1) return 1;
return (pmd_val(pmd) == 0);
}
-extern inline int pmd_bad(pmd_t pmd) { return (pmd_val(pmd) == 0); }
-extern inline int pmd_present(pmd_t pmd) { return (pmd_val(pmd) != 0); }
+static inline int pmd_bad(pmd_t pmd) { return (pmd_val(pmd) == 0); }
+static inline int pmd_present(pmd_t pmd) { return (pmd_val(pmd) != 0); }
/* clear the pmd entry */
-extern inline void pmd_clear(pmd_t * pmdp) { pmd_val(*pmdp) = 0; }
+static inline void pmd_clear(pmd_t * pmdp) { pmd_val(*pmdp) = 0; }
/* Find an entry in the second-level page table.. */
#define pmd_index(address) ((address >> PMD_SHIFT) & (PTRS_PER_PMD-1))
-extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
+static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
{
+ /* locate the pmd entry according to address */
pmd_t *ptr;
ptr = (pmd_t *)pmd_val(*dir) + pmd_index(address);
- /* locate the pmd entry according to address */
// printk("pmd_offset: pgd %8p, pmd_val %8lx, address %8lx, index %8lx, offset %8p\n",dir,pmd_val(*dir),address,pmd_index(address),ptr);
return ptr;
}
Index: pagelet_pte.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-vax/mm/pagelet_pte.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -r1.7 -r1.8
--- pagelet_pte.h 31 Aug 2001 11:53:29 -0000 1.7
+++ pagelet_pte.h 9 Apr 2002 12:33:20 -0000 1.8
@@ -141,8 +141,6 @@
#define pte_page(x) (mem_map+(unsigned long)(((pte_val(x) & PAGE_PFN_MASK) \
>> (PAGE_SHIFT - PAGELET_SHIFT))))
-
-
/*
* This requires that pte_set is called after pte_modify
* -- There is (7/2/2001) one reference to this in mm/mprotect.c
Index: pgalloc.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-vax/mm/pgalloc.h,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -r1.13 -r1.14
--- pgalloc.h 2 Sep 2001 20:52:51 -0000 1.13
+++ pgalloc.h 9 Apr 2002 12:33:20 -0000 1.14
@@ -1,7 +1,7 @@
#ifndef __ASM_VAX_MM_PGALLOC_H
#define __ASM_VAX_MM_PGALLOC_H
-/* Copyright atp 1998-2001. pgalloc.h for VAX architecture. */
+/* Copyright atp 1998-2002. pgalloc.h for VAX architecture. */
/*
* Fixmes:
* 1) the pte_alloc/freeing stuff. Check Constraints here
@@ -20,6 +20,7 @@
* atp Jun 2001 remove fixed size processes, use 3 level page table and pte slots.
* atp Jun-Jul 2001 - complete rewrite.
* atp Aug 2001 - swapping and vmalloc need pmd_alloc_kernel
+ * atp Feb 2002 - Update to track mm changes in 2.4.x (x>2)
*
* each 'pgd' spans an address range of 0x40000000 bytes.
* each page of 'ptes' spans an address range of 0x80000 bytes
@@ -33,21 +34,24 @@
#ifndef CONFIG_SMP
extern struct pgtable_cache_struct {
- unsigned long *pgd_cache;
+ unsigned long *pgd_cache; /* These are special recyclable slots */
unsigned long pgd_slots_used;
unsigned long pgd_cache_sz;
- unsigned long *pte_cache;
+ unsigned long *pmd_cache; /* These are two page blocks */
+ unsigned long pmd_cache_sz;
+ unsigned long *pte_cache; /* These are one page blocks */
unsigned long pgtable_cache_sz;
} quicklists;
#else
#include <asm/smp.h>
-#define quicklists cpu_data[smp_processor_id()]
-
+//#define quicklists cpu_data[smp_processor_id()]
+#error SMP not supported
#endif
#define pgd_quicklist (quicklists.pgd_cache)
-#define pmd_quicklist ((unsigned long *)0)
+#define pmd_quicklist (quicklists.pmd_cache)
#define pte_quicklist (quicklists.pte_cache)
+#define pmd_cache_size (quicklists.pmd_cache_sz)
#define pgtable_cache_size (quicklists.pgtable_cache_sz)
#define pgd_cache_size (quicklists.pgd_cache_sz)
#define pgd_slots_used (quicklists.pgd_slots_used)
@@ -58,64 +62,72 @@
* if any.
*/
-extern pgd_t *pgd_alloc(void);
-extern pgd_t *get_pgd_fast(void);
-extern __inline__ void free_pgd_fast(pgd_t *pgd)
+static inline void free_pgd_fast(pgd_t *pgd)
{
*(unsigned long *)pgd = (unsigned long) pgd_quicklist;
pgd_quicklist = (unsigned long *) pgd;
pgd_cache_size++;
}
-extern __inline__ void free_pgd_slow(pgd_t *pgd)
+static inline void free_pgd_slow(pgd_t *pgd)
{
- /* we dont do this at present */
-}
+ /*
+ * atp Mar 2002.
+ * We never free pgd 'pages'. The cache structure maintains
+ * a free list of free pgd/memory map slots, in the user page
+ * tables. This is contiguous in S0 page space
+ * If we need a pgd, we pick a 'slot' which holds all the pmds
+ * and ptes in a contiguous block of system address space.
+ */
-extern pmd_t *get_pmd_slow(void);
+}
-/* Page Mid level directory handling routines. */
-static inline pmd_t *get_pmd_fast(void)
+/* renamed from get_pmd_slow to pmd_alloc_one, mar 2002 */
+/* FIXME: This can be statically inlined -> pgalloc.h */
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
+{
+ pmd_t *ret;
+ ret = (pmd_t *)__get_free_pages(GFP_KERNEL,1);
+ if (ret) {
+ clear_page(ret);
+ clear_page(ret + (PAGE_SIZE/sizeof(pmd_t)));
+ }
+ return ret;
+}
+
+/* Page Mid level directory handling routines.
+ * renamed from get_pmd_fast */
+static inline pmd_t *pmd_alloc_one_fast(struct mm_struct *mm, unsigned long address)
{
unsigned long *ret;
- if ((ret = (unsigned long *)pte_quicklist) != NULL) {
- pte_quicklist = (unsigned long *)(*ret);
+ if ((ret = (unsigned long *)pmd_quicklist) != NULL) {
+ pmd_quicklist = (unsigned long *)(*ret);
ret[0] = 0;
- pgtable_cache_size--;
+ pmd_cache_size--;
}
return (pmd_t *)ret;
}
static inline void free_pmd_fast(pmd_t *pmd)
{
- *(unsigned long *)pmd = (unsigned long) pte_quicklist;
- pte_quicklist = (unsigned long *) pmd;
- pgtable_cache_size++;
+ *(unsigned long *)pmd = (unsigned long) pmd_quicklist;
+ pmd_quicklist = (unsigned long *) pmd;
+ pmd_cache_size++;
}
static inline void free_pmd_slow(pmd_t *pmd)
{
- free_page((unsigned long)pmd);
+ /*
+ * a pmd is a *two* page block of memory, allocated with
+ * __get_free_pages(GFP_KERNEL, 1);
+ */
+ free_pages(((unsigned long)pmd),1);
}
-/* in arch/vax/mm/pgalloc.c */
-extern pmd_t *pmd_alloc(pgd_t *pgd, unsigned long address);
-extern void pmd_free(pmd_t *pmd);
-extern pmd_t *pmd_alloc_kernel(pgd_t *pgd, unsigned long address);
-extern void pmd_free_kernel(pmd_t *pmd);
-extern void pte_free(pte_t *pte);
-extern pte_t *get_pageaddr_from_pte(pte_t *ptep);
-extern void free_pte_slow(pte_t *pte);
-
-extern pte_t *get_pte_slow(void);
-extern pte_t *get_pte_kernel_slow(pmd_t *pmd, unsigned long offset);
-extern void remap_and_clear_pte_page(pmd_t *s0addr, pte_t *page);
-extern void remap_pte_invalidate(pmd_t *s0addr);
-extern void pte_free_kernel(pte_t *pte);
-
-extern __inline__ pte_t *get_pte_fast(void)
+/* renamed from get_pte_fast, mar 2002 */
+static inline pte_t *pte_alloc_one_fast(struct mm_struct *mm, unsigned long address)
{
unsigned long *ret;
@@ -127,24 +139,47 @@
return (pte_t *)ret;
}
-extern __inline__ void free_pte_fast(pte_t *pte)
+/* renamed from get_pte_slow mar 2002 */
+static inline pte_t *pte_alloc_one(struct mm_struct *mm, unsigned long address)
+{
+ unsigned long pte;
+
+ pte = (unsigned long) __get_free_page(GFP_KERNEL);
+ if (pte) {
+ return (pte_t *) pte;
+ }
+ return NULL;
+}
+
+static inline void free_pte_fast(pte_t *pte)
{
*(unsigned long *)pte = (unsigned long) pte_quicklist;
pte_quicklist = (unsigned long *) pte;
pgtable_cache_size++;
}
-extern __inline__ void page_clear(pte_t *pte) {memset(pte, 0, PAGE_SIZE);}
-#define pgd_free(pgd) free_pgd_fast(pgd)
+/* in arch/vax/mm/pgalloc.c */
+extern pgd_t *pgd_alloc(struct mm_struct *mm);
+extern pgd_t *get_pgd_fast(void);
+extern void pmd_free(pmd_t *pmd);
+extern void pte_free(pte_t *pte);
+extern pte_t *get_pageaddr_from_pte(pte_t *ptep);
+extern void free_pte_slow(pte_t *pte);
+extern void remap_and_clear_pte_page(pmd_t *s0addr, pte_t *page);
+extern void remap_pte_invalidate(pmd_t *s0addr);
+extern void pte_free_kernel(pte_t *pte);
+extern pte_t * vax_pte_alloc_one(pmd_t *pmd);
+extern void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pmd_t *pmd);
+extern void pmd_populate(struct mm_struct *mm, pmd_t * pmd, pte_t *pte);
+extern void pmd_populate_S0(pgd_t *pgd, pmd_t *pmd);
-/* atp jun 01, moved these to arch/vax/mm/pgalloc.c */
-/* Allocate a new page for a page table for the kernel */
-extern pte_t *pte_alloc_kernel(pmd_t *pmd, unsigned long address);
-extern pte_t *pte_alloc(pmd_t *pmd, unsigned long address);
-extern pte_t * pte_alloc_one(pmd_t *pmd);
+/* in arch/vax/mm/init.c */
extern int do_check_pgt_cache(int, int);
+
+#define pgd_free(pgd) free_pgd_fast(pgd)
+
/* tlb routines */
Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-vax/mm/pgtable.h,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -r1.15 -r1.16
--- pgtable.h 11 Sep 2001 19:29:35 -0000 1.15
+++ pgtable.h 9 Apr 2002 12:33:20 -0000 1.16
@@ -59,6 +59,14 @@
/* SPT_SIZE is the size in BYTES */
#define SPT_SIZE ((unsigned long)( (swapper_pg_dir[2]).lr ) << 2)
+/* Offsets for the system page table for the asm code in head.S
+ * if you alter pgd_t change these.
+ */
+/* swapper_pg_dir[2].br */
+#define ASM_SBR_OFFSET 40
+/* swapper_pg_dir[2].lr */
+#define ASM_SLR_OFFSET 44
+
/*
* Macros to get page table addresses + offsets.
*
Index: task.h
===================================================================
RCS file: /cvsroot/linux-vax/kernel-2.4/include/asm-vax/mm/task.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -r1.6 -r1.7
--- task.h 11 Sep 2001 19:29:35 -0000 1.6
+++ task.h 9 Apr 2002 12:33:21 -0000 1.7
@@ -4,6 +4,19 @@
/* atp July 2001. */
/* These are all used to size the relevant structures in the system
* page table, in paging_init (arch/vax/mm/init.c)
+ *
+ * reminder: The vax memory map is not sparse. Every hole in the address
+ * space uses page table entries, and wastes memory. In addition
+ * Because the page tables need to be contiguous, in S0 virtual
+ * memory, we have to allocate contiguous system page table entries,
+ * which, in turn have to be contiguous in physical ram. So we fix
+ * at boot the amount of Virtual Address space that each task has
+ * available, and the maximum number of tasks that can be run.
+ * Keep these values as small as you can, or you will waste lots
+ * of memory on useless pagetables. Documentation/vax/memory.txt.
+ *
+ * Mar 2002. Update to 2.4.3 memory management. Thought of a better way
+ * of workig back to the pgd. Removed PGD_SPECIAL botch.
*/
/* currently allocate 32mb of virtual memory */
@@ -13,8 +26,11 @@
* get wierd here */
/* TASK_WSMAX is the max virtual address space in P0 */
-/* TASK_WSMAX must not be larger than 768MB. In the unlikely event that
- * you really want to allocate that much to a process, change PGD_SPECIAL below */
+/* TASK_WSMAX must not be larger than 1Gb, it is the sum of the
+ * TXT section - which defines the largest program that can be run,
+ * and the MMAP section, which describes how much virtual address space
+ * that program has available to it
+ */
/* TASK_TXTMAX is the maximum program size */
#define TASK_TXTMAX (6*1024*1024)
@@ -25,9 +41,6 @@
#define TASK_MMAPMAX (58*1024*1024)
/* TASK_STKMAX is the max space for the stack in P1 */
-/* Like WSMAX above, the upper limit for this is set by PGD_SPECIAL below. If this
- * is above 256MB change PGD_SPECIAL
- */
#define TASK_STKMAX (4*1024*1024)
#define TASK_WSMAX (TASK_TXTMAX+TASK_MMAPMAX)
@@ -70,13 +83,6 @@
#define P0PMD_OFFSET (0)
#define P1PMD_OFFSET (PAGE_SIZE*2)
-/*
- * This is a special index into the pmd. This stores a back pointer to the
- * pgd in the pmd. The default value of 1536 allows 768 MB for WSMAX and 256
- * MB for stack. If you want to change that allocation, bear in mind that you
- * have to trade WSMAX for STKMAX. Unless I think of a cleverer way of doing this.
- */
-#define PGD_SPECIAL 1536
/*
* User space process size: 2GB (default).
* This is a bit bogus - a linux thing.
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:34
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/pmc
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-mips/pmc
Added Files:
ev64120.h ev64120int.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/*
* This is a direct copy of the ev96100.h file, with a global search and
* replace. The numbers are the same.
*
* The reason I'm duplicating this is so that the 64120/96100
* defines won't be confusing in the source code.
*/
#ifndef _ASM_PMC_CP7000_H
#define _ASM_PMC_CP7000_H
#include <asm/addrspace.h>
/*
* GT64120 config space base address
*/
#define GT64120_BASE (KSEG1ADDR(0x14000000))
#define MIPS_GT_BASE GT64120_BASE
/*
* PCI Bus allocation
*/
#define GT_PCI_MEM_BASE 0x12000000
#define GT_PCI_MEM_SIZE 0x02000000
#define GT_PCI_IO_BASE 0x10000000
#define GT_PCI_IO_SIZE 0x02000000
#define GT_ISA_IO_BASE PCI_IO_BASE
/*
* Duart I/O ports.
*/
#define EV64120_COM1_BASE_ADDR (0x1d000000 + 0x20)
#define EV64120_COM2_BASE_ADDR (0x1d000000 + 0x00)
/*
* EV64120 interrupt controller register base.
*/
#define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
/*
* EV64120 UART register base.
*/
#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
#define EV64120_BASE_BAUD ( 3686400 / 16 )
/*
* Because of an error/peculiarity in the Galileo chip, we need to swap the
* bytes when running bigendian.
*/
#define GT_WRITE(ofs, data) \
*(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data)
#define GT_READ(ofs, data) \
*data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs))
#endif /* _ASM_PMC_CP7000_H */
--- NEW FILE ---
#ifndef _ASM_PMC_CP7000INT_H
#define _ASM_PMC_CP7000INT_H
#define INT_CAUSE_MAIN 0
#define INT_CAUSE_HIGH 1
#define MAX_CAUSE_REGS 4
#define MAX_CAUSE_REG_WIDTH 32
void hook_irq_handler (int int_cause , int bit_num , void *isr_ptr);
int disable_galileo_irq (int int_cause , int bit_num);
int enable_galileo_irq (int int_cause , int bit_num);
extern struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
/*
* PCI interrupts will come in on either the INTA or INTD interrups lines,
* which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
* boards, they all either come in on IntD or they all come in on IntA, they
* aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
* "requested" interrupt numbers and go through the list whenever we get an
* IntA/D.
*
* All PCI interrupts have numbers >= 20 by arbitrary convention. Any
* interrupt < 8 is an interrupt that is maskable on MIPS.
*/
#define TIMER 4
#define INTA 2
#define INTD 5
#endif /* _ASM_PMC_CP7000INT_H */
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips64/mips-boards
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-mips64/mips-boards
Added Files:
atlas.h atlasint.h generic.h gt64120.h io.h malta.h maltaint.h
piix4.h prom.h saa9730_uart.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the Atlas board specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_ATLAS_H
#define _MIPS_ATLAS_H
#include <asm/addrspace.h>
/*
* Atlas RTC-device indirect register access.
*/
#define ATLAS_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
#define ATLAS_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
/*
* Atlas interrupt controller register base.
*/
#define ATLAS_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
/*
* Atlas UART register base.
*/
#define ATLAS_UART_REGS_BASE (0x1f000900)
#define ATLAS_BASE_BAUD ( 3686400 / 16 )
/*
* Atlas PSU standby register.
*/
#define ATLAS_PSUSTBY_REG (KSEG1ADDR(0x1f000600))
#define ATLAS_GOSTBY 0x4d
/*
* We make a universal assumption about the way the bootloader (YAMON)
* have located the Philips SAA9730 chip.
* This is not ideal, but is needed for setting up remote debugging as
* soon as possible.
*/
#define ATLAS_SAA9730_REG (KSEG1ADDR(0x08800000))
#endif /* !(_MIPS_ATLAS_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines for the Atlas interrupt controller.
*
*/
#ifndef _MIPS_ATLASINT_H
#define _MIPS_ATLASINT_H
/* Number of IRQ supported on hw interrupt 0. */
#define ATLASINT_UART 0
#define ATLASINT_END 32
/*
* Atlas registers are memory mapped on 64-bit aligned boundaries and
* only word access are allowed.
*/
struct atlas_ictrl_regs {
volatile unsigned long intraw;
long dummy1;
volatile unsigned long intseten;
long dummy2;
volatile unsigned long intrsten;
long dummy3;
volatile unsigned long intenable;
long dummy4;
volatile unsigned long intstatus;
long dummy5;
};
extern void atlasint_init(void);
#endif /* !(_MIPS_ATLASINT_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the MIPS boards specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_GENERIC_H
#define _MIPS_GENERIC_H
#include <asm/addrspace.h>
#include <asm/byteorder.h>
/*
* Display register base.
*/
#define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410))
#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418))
/*
* Yamon Prom print address.
*/
#define YAMON_PROM_PRINT_ADDR (KSEG1ADDR(0x1fc00504))
/*
* Reset register.
*/
#define SOFTRES_REG (KSEG1ADDR(0x1f000500))
#define GORESET 0x42
/*
* Galileo GT64120 system controller register base.
*/
#define MIPS_GT_BASE (KSEG1ADDR(0x1be00000))
/*
* Because of the way the internal register works on the Galileo chip,
* we need to swap the bytes when running bigendian.
*/
#define GT_WRITE(ofs, data) \
*(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data)
#define GT_READ(ofs, data) \
data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs))
#define GT_PCI_WRITE(ofs, data) \
*(volatile u32 *)(MIPS_GT_BASE+ofs) = data
#define GT_PCI_READ(ofs, data) \
data = *(volatile u32 *)(MIPS_GT_BASE+ofs)
#endif /* !(_MIPS_GENERIC_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Register definitions for Galileo 64120 system controller.
*
*/
#ifndef GT64120_H
#define GT64120_H
#define MSK(n) ((1 << (n)) - 1)
/************************************************************************
* Register offset addresses
************************************************************************/
#define GT_CPU_OFS 0x000
#define GT_CPU_OFS 0x000
#define GT_SCS10LD_OFS 0x008
#define GT_SCS10HD_OFS 0x010
#define GT_SCS32LD_OFS 0x018
#define GT_SCS32HD_OFS 0x020
#define GT_CS20LD_OFS 0x028
#define GT_CS20HD_OFS 0x030
#define GT_CS3BOOTLD_OFS 0x038
#define GT_CS3BOOTHD_OFS 0x040
#define GT_PCI0IOLD_OFS 0x048
#define GT_PCI0IOHD_OFS 0x050
#define GT_PCI0M0LD_OFS 0x058
#define GT_PCI0M0HD_OFS 0x060
#define GT_ISD_OFS 0x068
#define GT_PCI0M1LD_OFS 0x080
#define GT_PCI0M1HD_OFS 0x088
#define GT_PCI1IOLD_OFS 0x090
#define GT_PCI1IOHD_OFS 0x098
#define GT_PCI1M0LD_OFS 0x0a0
#define GT_PCI1M0HD_OFS 0x0a8
#define GT_PCI1M1LD_OFS 0x0b0
#define GT_PCI1M1HD_OFS 0x0b8
#define GT_SCS0LD_OFS 0x400
#define GT_SCS0HD_OFS 0x404
#define GT_SCS1LD_OFS 0x408
#define GT_SCS1HD_OFS 0x40c
#define GT_SCS2LD_OFS 0x410
#define GT_SCS2HD_OFS 0x414
#define GT_SCS3LD_OFS 0x418
#define GT_SCS3HD_OFS 0x41c
#define GT_CS0LD_OFS 0x420
#define GT_CS0HD_OFS 0x424
#define GT_CS1LD_OFS 0x428
#define GT_CS1HD_OFS 0x42c
#define GT_CS2LD_OFS 0x430
#define GT_CS2HD_OFS 0x434
#define GT_CS3LD_OFS 0x438
#define GT_CS3HD_OFS 0x43c
#define GT_BOOTLD_OFS 0x440
#define GT_BOOTHD_OFS 0x444
#define GT_SDRAM_B0_OFS 0x44c
#define GT_SDRAM_CFG_OFS 0x448
#define GT_SDRAM_B2_OFS 0x454
#define GT_SDRAM_OPMODE_OFS 0x474
#define GT_SDRAM_BM_OFS 0x478
#define GT_SDRAM_ADDRDECODE_OFS 0x47c
#define GT_PCI0_CMD_OFS 0xc00
#define GT_PCI0_TOR_OFS 0xc04
#define GT_PCI0_BS_SCS10_OFS 0xc08
#define GT_PCI0_BS_SCS32_OFS 0xc0c
#define GT_INTRCAUSE_OFS 0xc18
#define GT_PCI0_IACK_OFS 0xc34
#define GT_PCI0_BARE_OFS 0xc3c
#define GT_PCI0_CFGADDR_OFS 0xcf8
#define GT_PCI0_CFGDATA_OFS 0xcfc
/************************************************************************
* Register encodings
************************************************************************/
#define GT_CPU_ENDIAN_SHF 12
#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF)
#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK
#define GT_CPU_WR_SHF 16
#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF)
#define GT_CPU_WR_BIT GT_CPU_WR_MSK
#define GT_CPU_WR_DXDXDXDX 0
#define GT_CPU_WR_DDDD 1
#define GT_CFGADDR_CFGEN_SHF 31
#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF)
#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK
#define GT_CFGADDR_BUSNUM_SHF 16
#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
#define GT_CFGADDR_DEVNUM_SHF 11
#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
#define GT_CFGADDR_FUNCNUM_SHF 8
#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
#define GT_CFGADDR_REGNUM_SHF 2
#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF)
#define GT_SDRAM_BM_ORDER_SHF 2
#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK
#define GT_SDRAM_BM_ORDER_SUB 1
#define GT_SDRAM_BM_ORDER_LIN 0
#define GT_SDRAM_BM_RSVD_ALL1 0xFFB
#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0
#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
#define GT_SDRAM_ADDRDECODE_ADDR_0 0
#define GT_SDRAM_ADDRDECODE_ADDR_1 1
#define GT_SDRAM_ADDRDECODE_ADDR_2 2
#define GT_SDRAM_ADDRDECODE_ADDR_3 3
#define GT_SDRAM_ADDRDECODE_ADDR_4 4
#define GT_SDRAM_ADDRDECODE_ADDR_5 5
#define GT_SDRAM_ADDRDECODE_ADDR_6 6
#define GT_SDRAM_ADDRDECODE_ADDR_7 7
#define GT_SDRAM_B0_CASLAT_SHF 0
#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF)
#define GT_SDRAM_B0_CASLAT_2 1
#define GT_SDRAM_B0_CASLAT_3 2
#define GT_SDRAM_B0_FTDIS_SHF 2
#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK
#define GT_SDRAM_B0_SRASPRCHG_SHF 3
#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK
#define GT_SDRAM_B0_SRASPRCHG_2 0
#define GT_SDRAM_B0_SRASPRCHG_3 1
#define GT_SDRAM_B0_B0COMPAB_SHF 4
#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK
#define GT_SDRAM_B0_64BITINT_SHF 5
#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK
#define GT_SDRAM_B0_64BITINT_2 0
#define GT_SDRAM_B0_64BITINT_4 1
#define GT_SDRAM_B0_BW_SHF 6
#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF)
#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK
#define GT_SDRAM_B0_BW_32 0
#define GT_SDRAM_B0_BW_64 1
#define GT_SDRAM_B0_BLODD_SHF 7
#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK
#define GT_SDRAM_B0_PAR_SHF 8
#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF)
#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK
#define GT_SDRAM_B0_BYPASS_SHF 9
#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK
#define GT_SDRAM_B0_SRAS2SCAS_SHF 10
#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK
#define GT_SDRAM_B0_SRAS2SCAS_2 0
#define GT_SDRAM_B0_SRAS2SCAS_3 1
#define GT_SDRAM_B0_SIZE_SHF 11
#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK
#define GT_SDRAM_B0_SIZE_16M 0
#define GT_SDRAM_B0_SIZE_64M 1
#define GT_SDRAM_B0_EXTPAR_SHF 12
#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK
#define GT_SDRAM_B0_BLEN_SHF 13
#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK
#define GT_SDRAM_B0_BLEN_8 0
#define GT_SDRAM_B0_BLEN_4 1
#define GT_SDRAM_CFG_REFINT_SHF 0
#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14
#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK
#define GT_SDRAM_CFG_RMW_SHF 15
#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK
#define GT_SDRAM_CFG_NONSTAGREF_SHF 16
#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK
#define GT_SDRAM_CFG_DUPCNTL_SHF 19
#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK
#define GT_SDRAM_CFG_DUPBA_SHF 20
#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK
#define GT_SDRAM_CFG_DUPEOT0_SHF 21
#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK
#define GT_SDRAM_CFG_DUPEOT1_SHF 22
#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK
#define GT_SDRAM_OPMODE_OP_SHF 0
#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
#define GT_SDRAM_OPMODE_OP_NORMAL 0
#define GT_SDRAM_OPMODE_OP_NOP 1
#define GT_SDRAM_OPMODE_OP_PRCHG 2
#define GT_SDRAM_OPMODE_OP_MODE 3
#define GT_SDRAM_OPMODE_OP_CBR 4
#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
#define GT_PCI0_BARE_SWSCS32DIS_SHF 1
#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK
#define GT_PCI0_BARE_SWSCS10DIS_SHF 2
#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK
#define GT_PCI0_BARE_INTIODIS_SHF 3
#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK
#define GT_PCI0_BARE_INTMEMDIS_SHF 4
#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK
#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5
#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK
#define GT_PCI0_BARE_CS20DIS_SHF 6
#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK
#define GT_PCI0_BARE_SCS32DIS_SHF 7
#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK
#define GT_PCI0_BARE_SCS10DIS_SHF 8
#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK
#define GT_INTRCAUSE_MASABORT0_SHF 18
#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
#define GT_INTRCAUSE_TARABORT0_SHF 19
#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
#define GT_PCI0_CFGADDR_REGNUM_SHF 2
#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
#define GT_PCI0_CFGADDR_DEVNUM_SHF 11
#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
#define GT_PCI0_CFGADDR_BUSNUM_SHF 16
#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
#define GT_PCI0_CMD_MBYTESWAP_SHF 0
#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK
#define GT_PCI0_CMD_MWORDSWAP_SHF 10
#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK
#define GT_PCI0_CMD_SBYTESWAP_SHF 16
#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK
#define GT_PCI0_CMD_SWORDSWAP_SHF 11
#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK
/************************************************************************
* Misc
************************************************************************/
#define GT_DEF_BASE 0x14000000
#define GT_DEF_PCI0_MEM0_BASE 0x12000000
#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */
#define GT_LATTIM_MIN 6 /* Minimum lat */
#endif /* #ifndef GT64120_H */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the MIPS boards specific IO address-MAP.
*
*/
#ifndef _ASM_MIPS_BOARDS_IO_H
#define _ASM_MIPS_BOARDS_IO_H
#include <asm/addrspace.h>
#define IO_SPACE_BASE K1BASE
#define IO_SPACE_LIMIT 0xffffffff
#endif /* _ASM_MIPS_BOARDS_IO_H */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the Malta board specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_MALTA_H
#define _MIPS_MALTA_H
#include <asm/addrspace.h>
#include <asm/io.h>
/*
* Malta I/O ports base address.
*/
#define MALTA_PORT_BASE (KSEG1ADDR(0x18000000))
/*
* Malta RTC-device indirect register access.
*/
#define MALTA_RTC_ADR_REG 0x70
#define MALTA_RTC_DAT_REG 0x71
/*
* Malta SMSC FDC37M817 Super I/O Controller register.
*/
#define SMSC_CONFIG_REG 0x3f0
#define SMSC_DATA_REG 0x3f1
#define SMSC_CONFIG_DEVNUM 0x7
#define SMSC_CONFIG_ACTIVATE 0x30
#define SMSC_CONFIG_ENTER 0x55
#define SMSC_CONFIG_EXIT 0xaa
#define SMSC_CONFIG_DEVNUM_FLOPPY 0
#define SMSC_CONFIG_ACTIVATE_ENABLE 1
#define SMSC_WRITE(x,a) outb(x,a)
#endif /* !(_MIPS_MALTA_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines for the Malta interrupt controller.
*
*/
#ifndef _MIPS_MALTAINT_H
#define _MIPS_MALTAINT_H
/* Number of IRQ supported on hw interrupt 0. */
#define MALTAINT_END 16
extern void maltaint_init(void);
#endif /* !(_MIPS_MALTAINT_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Register definitions for Intel PIIX4 South Bridge Device.
*
*/
#ifndef PIIX4_H
#define PIIX4_H
/************************************************************************
* IO register offsets
************************************************************************/
#define PIIX4_ICTLR1_ICW1 0x20
#define PIIX4_ICTLR1_ICW2 0x21
#define PIIX4_ICTLR1_ICW3 0x21
#define PIIX4_ICTLR1_ICW4 0x21
#define PIIX4_ICTLR2_ICW1 0xa0
#define PIIX4_ICTLR2_ICW2 0xa1
#define PIIX4_ICTLR2_ICW3 0xa1
#define PIIX4_ICTLR2_ICW4 0xa1
#define PIIX4_ICTLR1_OCW1 0x21
#define PIIX4_ICTLR1_OCW2 0x20
#define PIIX4_ICTLR1_OCW3 0x20
#define PIIX4_ICTLR1_OCW4 0x20
#define PIIX4_ICTLR2_OCW1 0xa1
#define PIIX4_ICTLR2_OCW2 0xa0
#define PIIX4_ICTLR2_OCW3 0xa0
#define PIIX4_ICTLR2_OCW4 0xa0
/************************************************************************
* Register encodings.
************************************************************************/
#define PIIX4_OCW2_NSEOI (0x1 << 5)
#define PIIX4_OCW2_SEOI (0x3 << 5)
#define PIIX4_OCW2_RNSEOI (0x5 << 5)
#define PIIX4_OCW2_RAEOIS (0x4 << 5)
#define PIIX4_OCW2_RAEOIC (0x0 << 5)
#define PIIX4_OCW2_RSEOI (0x7 << 5)
#define PIIX4_OCW2_SP (0x6 << 5)
#define PIIX4_OCW2_NOP (0x2 << 5)
#define PIIX4_OCW2_SEL (0x0 << 3)
#define PIIX4_OCW2_ILS_0 0
#define PIIX4_OCW2_ILS_1 1
#define PIIX4_OCW2_ILS_2 2
#define PIIX4_OCW2_ILS_3 3
#define PIIX4_OCW2_ILS_4 4
#define PIIX4_OCW2_ILS_5 5
#define PIIX4_OCW2_ILS_6 6
#define PIIX4_OCW2_ILS_7 7
#define PIIX4_OCW2_ILS_8 0
#define PIIX4_OCW2_ILS_9 1
#define PIIX4_OCW2_ILS_10 2
#define PIIX4_OCW2_ILS_11 3
#define PIIX4_OCW2_ILS_12 4
#define PIIX4_OCW2_ILS_13 5
#define PIIX4_OCW2_ILS_14 6
#define PIIX4_OCW2_ILS_15 7
#define PIIX4_OCW3_SEL (0x1 << 3)
#define PIIX4_OCW3_IRR 0x2
#define PIIX4_OCW3_ISR 0x3
#endif /* !(PIIX4_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* MIPS boards bootprom interface for the Linux kernel.
*
*/
#ifndef _MIPS_PROM_H
#define _MIPS_PROM_H
extern char *prom_getcmdline(void);
extern char *prom_getenv(char *name);
extern void setup_prom_printf(int tty_no);
extern void prom_printf(char *fmt, ...);
extern void prom_init_cmdline(void);
extern void prom_meminit(void);
extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
extern void prom_free_prom_memory (void);
extern void mips_display_message(const char *str);
extern void mips_display_word(unsigned int num);
extern int get_ethernet_addr(char *ethernet_addr);
/* Memory descriptor management. */
#define PROM_MAX_PMEMBLOCKS 32
struct prom_pmemblock {
unsigned int base; /* Phys addr. */
unsigned int size; /* In bytes. */
unsigned int type; /* free or prom memory */
};
#endif /* !(_MIPS_PROM_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Register definitions for the UART part of the Philips SAA9730 chip.
*
*/
#ifndef SAA9730_UART_H
#define SAA9730_UART_H
/* The SAA9730 UART register map, as seen via the PCI bus */
#define SAA9730_UART_REGS_ADDR 0x21800
struct uart_saa9730_regmap {
volatile unsigned char Thr_Rbr;
volatile unsigned char Ier;
volatile unsigned char Iir_Fcr;
volatile unsigned char Lcr;
volatile unsigned char Mcr;
volatile unsigned char Lsr;
volatile unsigned char Msr;
volatile unsigned char Scr;
volatile unsigned char BaudDivLsb;
volatile unsigned char BaudDivMsb;
volatile unsigned char Junk0;
volatile unsigned char Junk1;
volatile unsigned int Config; /* 0x2180c */
volatile unsigned int TxStart; /* 0x21810 */
volatile unsigned int TxLength; /* 0x21814 */
volatile unsigned int TxCounter; /* 0x21818 */
volatile unsigned int RxStart; /* 0x2181c */
volatile unsigned int RxLength; /* 0x21820 */
volatile unsigned int RxCounter; /* 0x21824 */
};
typedef volatile struct uart_saa9730_regmap t_uart_saa9730_regmap;
/*
* Only a subset of the UART control bits are defined here,
* enough to make the serial debug port work.
*/
#define SAA9730_LCR_DATA8 0x03
#define SAA9730_MCR_DTR 0x01
#define SAA9730_MCR_RTS 0x02
#define SAA9730_LSR_DR 0x01
#define SAA9730_LSR_THRE 0x20
#endif /* !(SAA9730_UART_H) */
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:31
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips64/gcc In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-mips64/gcc Added Files: sgidefs.h Log Message: Synch to 2.4.15 commit 1 --- NEW FILE --- /* * include/sgidefs.h * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1996 by Ralf Baechle * * This file is here to satisfy GCC's expectations. */ #ifndef __SGIDEFS_H #define __SGIDEFS_H #include <asm/sgidefs.h> #endif /* __SGIDEFS_H */ |
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:31
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/it8172
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-mips/it8172
Added Files:
it8172.h it8172_cir.h it8172_dbg.h it8172_int.h it8172_lpc.h
it8172_pci.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/*
*
* BRIEF MODULE DESCRIPTION
* IT8172 system controller defines.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* pp...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __IT8172__H__
#define __IT8172__H__
#include <asm/addrspace.h>
#define IT8172_BASE 0x18000000
#define IT8172_PCI_IO_BASE 0x14000000
#define IT8172_PCI_MEM_BASE 0x10000000
// System registers offsets from IT8172_BASE
#define IT_CMFPCR 0x0
#define IT_DSRR 0x2
#define IT_PCDCR 0x4
#define IT_SPLLCR 0x6
#define IT_CIDR 0x10
#define IT_CRNR 0x12
#define IT_CPUTR 0x14
#define IT_CTCR 0x16
#define IT_SDPR 0xF0
// Power management register offset from IT8172_PCI_IO_BASE
// Power Management Device Standby Register
#define IT_PM_DSR 0x15800
#define IT_PM_DSR_TMR0SB 0x0001
#define IT_PM_DSR_TMR1SB 0x0002
#define IT_PM_DSR_CIR0SB 0x0004
#define IT_PM_DSR_CIR1SB 0x0008
#define IT_PM_DSR_SCR0SB 0x0010
#define IT_PM_DSR_SCR1SB 0x0020
#define IT_PM_DSR_PPSB 0x0040
#define IT_PM_DSR_I2CSB 0x0080
#define IT_PM_DSR_UARTSB 0x0100
#define IT_PM_DSR_IDESB 0x0200
#define IT_PM_DSR_ACSB 0x0400
#define IT_PM_DSR_M68KSB 0x0800
// Power Management PCI Device Software Reset Register
#define IT_PM_PCISR 0x15802
#define IT_PM_PCISR_IDESR 0x0001
#define IT_PM_PCISR_CDMASR 0x0002
#define IT_PM_PCISR_USBSR 0x0004
#define IT_PM_PCISR_DMASR 0x0008
#define IT_PM_PCISR_ACSR 0x0010
#define IT_PM_PCISR_MEMSR 0x0020
#define IT_PM_PCISR_68KSR 0x0040
// PCI Configuration address and data register offsets
// from IT8172_BASE
#define IT_CONFADDR 0x4000
#define IT_BUSNUM_SHF 16
#define IT_DEVNUM_SHF 11
#define IT_FUNCNUM_SHF 8
#define IT_REGNUM_SHF 2
#define IT_CONFDATA 0x4004
// PCI configuration header common register offsets
#define IT_VID 0x00
#define IT_DID 0x02
#define IT_PCICMD 0x04
#define IT_PCISTS 0x06
#define IT_RID 0x08
#define IT_CLASSC 0x09
#define IT_HEADT 0x0E
#define IT_SERIRQC 0x49
// PCI to Internal/LPC Bus Bridge configuration header register offset
#define IT_P2I_BCR 0x4C
#define IT_P2I_D0IOSC 0x50
#define IT_P2I_D1IOSC 0x54
#define IT_P2I_D2IOSC 0x58
#define IT_P2I_D3IOSC 0x5C
#define IT_P2I_D4IOSC 0x60
#define IT_P2I_D5IOSC 0x64
#define IT_P2I_D6IOSC 0x68
#define IT_P2I_D7IOSC 0x6C
#define IT_P2I_D8IOSC 0x70
#define IT_P2I_D9IOSC 0x74
#define IT_P2I_D10IOSC 0x78
#define IT_P2I_D11IOSC 0x7C
// Memory controller register offsets from IT8172_BASE
#define IT_MC_SDRMR 0x1000
#define IT_MC_SDRTR 0x1004
#define IT_MC_MCR 0x1008
#define IT_MC_SDTYPE 0x100C
#define IT_MC_WPBA 0x1010
#define IT_MC_WPTA 0x1014
#define IT_MC_HATR 0x1018
#define IT_MC_PCICR 0x101C
// Flash/ROM control register offsets from IT8172_BASE
#define IT_FC_BRCR 0x2000
#define IT_FC_FCR 0x2004
#define IT_FC_DCR 0x2008
// M68K interface bridge configuration header register offset
#define IT_M68K_MBCSR 0x54
#define IT_M68K_TMR 0x58
#define IT_M68K_BCR 0x5C
#define IT_M68K_BSR 0x5D
#define IT_M68K_DTR 0x5F
// Register offset from IT8172_PCI_IO_BASE
// These registers are accessible through 8172 PCI IO window.
// INTC
#define IT_INTC_BASE 0x10000
#define IT_INTC_LBDNIRR 0x10000
#define IT_INTC_LBDNIMR 0x10002
#define IT_INTC_LBDNITR 0x10004
#define IT_INTC_LBDNIAR 0x10006
#define IT_INTC_LPCNIRR 0x10010
#define IT_INTC_LPCNIMR 0x10012
#define IT_INTC_LPCNITR 0x10014
#define IT_INTC_LPCNIAR 0x10016
#define IT_INTC_PDNIRR 0x10020
#define IT_INTC_PDNIMR 0x10022
#define IT_INTC_PDNITR 0x10024
#define IT_INTC_PDNIAR 0x10026
#define IT_INTC_UMNIRR 0x10030
#define IT_INTC_UMNITR 0x10034
#define IT_INTC_UMNIAR 0x10036
#define IT_INTC_TYPER 0x107FE
// IT8172 PCI device number
#define IT_C2P_DEVICE 0
#define IT_AUDIO_DEVICE 1
#define IT_DMAC_DEVICE 1
#define IT_CDMAC_DEVICE 1
#define IT_USB_DEVICE 1
#define IT_P2I_DEVICE 1
#define IT_IDE_DEVICE 1
#define IT_M68K_DEVICE 1
// IT8172 PCI function number
#define IT_C2P_FUNCION 0
#define IT_AUDIO_FUNCTION 0
#define IT_DMAC_FUNCTION 1
#define IT_CDMAC_FUNCTION 2
#define IT_USB_FUNCTION 3
#define IT_P2I_FUNCTION 4
#define IT_IDE_FUNCTION 5
#define IT_M68K_FUNCTION 6
// IT8172 GPIO
#define IT_GPADR 0x13800
#define IT_GPBDR 0x13808
#define IT_GPCDR 0x13810
#define IT_GPACR 0x13802
#define IT_GPBCR 0x1380A
#define IT_GPCCR 0x13812
#define IT_GPAICR 0x13804
#define IT_GPBICR 0x1380C
#define IT_GPCICR 0x13814
#define IT_GPAISR 0x13806
#define IT_GPBISR 0x1380E
#define IT_GPCISR 0x13816
#define IT_GCR 0x13818
// IT8172 RTC
#define IT_RTC_BASE 0x14800
#define IT_RTC_RIR0 0x00
#define IT_RTC_RTR0 0x01
#define IT_RTC_RIR1 0x02
#define IT_RTC_RTR1 0x03
#define IT_RTC_RIR2 0x04
#define IT_RTC_RTR2 0x05
#define IT_RTC_RCTR 0x08
#define IT_RTC_RA 0x0A
#define IT_RTC_RB 0x0B
#define IT_RTC_RC 0x0C
#define IT_RTC_RD 0x0D
#define RTC_SEC_INDEX 0x00
#define RTC_MIN_INDEX 0x02
#define RTC_HOUR_INDEX 0x04
#define RTC_DAY_INDEX 0x06
#define RTC_DATE_INDEX 0x07
#define RTC_MONTH_INDEX 0x08
#define RTC_YEAR_INDEX 0x09
// IT8172 internal device registers
#define IT_TIMER_BASE 0x10800
#define IT_CIR0_BASE 0x11000
#define IT_UART_BASE 0x11800
#define IT_SCR0_BASE 0x12000
#define IT_SCR1_BASE 0x12800
#define IT_PP_BASE 0x13000
#define IT_I2C_BASE 0x14000
#define IT_CIR1_BASE 0x15000
// IT8172 Smart Card Reader offsets from IT_SCR*_BASE
#define IT_SCR_SFR 0x08
#define IT_SCR_SCDR 0x09
// IT8172 IT_SCR_SFR bit definition & mask
#define IT_SCR_SFR_GATE_UART 0x40
#define IT_SCR_SFR_GATE_UART_BIT 6
#define IT_SCR_SFR_GATE_UART_OFF 0
#define IT_SCR_SFR_GATE_UART_ON 1
#define IT_SCR_SFR_FET_CHARGE 0x30
#define IT_SCR_SFR_FET_CHARGE_BIT 4
#define IT_SCR_SFR_FET_CHARGE_3_3_US 3
#define IT_SCR_SFR_FET_CHARGE_13_US 2
#define IT_SCR_SFR_FET_CHARGE_53_US 1
#define IT_SCR_SFR_FET_CHARGE_213_US 0
#define IT_SCR_SFR_CARD_FREQ 0x0C
#define IT_SCR_SFR_CARD_FREQ_BIT 2
#define IT_SCR_SFR_CARD_FREQ_STOP 3
#define IT_SCR_SFR_CARD_FREQ_3_5_MHZ 0
#define IT_SCR_SFR_CARD_FREQ_7_1_MHZ 2
#define IT_SCR_SFR_CARD_FREQ_96_DIV_MHZ 1
#define IT_SCR_SFR_FET_ACTIVE 0x02
#define IT_SCR_SFR_FET_ACTIVE_BIT 1
#define IT_SCR_SFR_FET_ACTIVE_INVERT 0
#define IT_SCR_SFR_FET_ACTIVE_NONINVERT 1
#define IT_SCR_SFR_ENABLE 0x01
#define IT_SCR_SFR_ENABLE_BIT 0
#define IT_SCR_SFR_ENABLE_OFF 0
#define IT_SCR_SFR_ENABLE_ON 1
// IT8172 IT_SCR_SCDR bit definition & mask
#define IT_SCR_SCDR_RESET_MODE 0x80
#define IT_SCR_SCDR_RESET_MODE_BIT 7
#define IT_SCR_SCDR_RESET_MODE_ASYNC 0
#define IT_SCR_SCDR_RESET_MODE_SYNC 1
#define IT_SCR_SCDR_DIVISOR 0x7F
#define IT_SCR_SCDR_DIVISOR_BIT 0
#define IT_SCR_SCDR_DIVISOR_STOP_VAL_1 0x00
#define IT_SCR_SCDR_DIVISOR_STOP_VAL_2 0x01
#define IT_SCR_SCDR_DIVISOR_STOP_VAL_3 0x7F
// IT8172 DMA
#define IT_DMAC_BASE 0x16000
#define IT_DMAC_BCAR0 0x00
#define IT_DMAC_BCAR1 0x04
#define IT_DMAC_BCAR2 0x08
#define IT_DMAC_BCAR3 0x0C
#define IT_DMAC_BCCR0 0x02
#define IT_DMAC_BCCR1 0x06
#define IT_DMAC_BCCR2 0x0a
#define IT_DMAC_BCCR3 0x0e
#define IT_DMAC_CR 0x10
#define IT_DMAC_SR 0x12
#define IT_DMAC_ESR 0x13
#define IT_DMAC_RQR 0x14
#define IT_DMAC_MR 0x16
#define IT_DMAC_EMR 0x17
#define IT_DMAC_MKR 0x18
#define IT_DMAC_PAR0 0x20
#define IT_DMAC_PAR1 0x22
#define IT_DMAC_PAR2 0x24
#define IT_DMAC_PAR3 0x26
// IT8172 IDE
#define IT_IDE_BASE 0x17800
#define IT_IDE_STATUS 0x1F7
// IT8172 Audio Controller
#define IT_AC_BASE 0x17000
#define IT_AC_PCMOV 0x00
#define IT_AC_FMOV 0x02
#define IT_AC_I2SV 0x04
#define IT_AC_DRSS 0x06
#define IT_AC_PCC 0x08
#define IT_AC_PCDL 0x0A
#define IT_AC_PCB1STA 0x0C
#define IT_AC_PCB2STA 0x10
#define IT_AC_CAPCC 0x14
#define IT_AC_CAPCDL 0x16
#define IT_AC_CAPB1STA 0x18
#define IT_AC_CAPB2STA 0x1C
#define IT_AC_CODECC 0x22
#define IT_AC_I2SMC 0x24
#define IT_AC_VS 0x26
#define IT_AC_SRCS 0x28
#define IT_AC_CIRCP 0x2A
#define IT_AC_CIRDP 0x2C
#define IT_AC_TM 0x4A
#define IT_AC_PFDP 0x4C
#define IT_AC_GC 0x54
#define IT_AC_IMC 0x56
#define IT_AC_ISC 0x5B
#define IT_AC_OPL3SR 0x68
#define IT_AC_OPL3DWDR 0x69
#define IT_AC_OPL3AB1W 0x6A
#define IT_AC_OPL3DW 0x6B
#define IT_AC_BPDC 0x70
// IT8172 Timer
#define IT_TIMER_BASE 0x10800
#define TIMER_TCVR0 0x00
#define TIMER_TRVR0 0x02
#define TIMER_TCR0 0x04
#define TIMER_TIRR 0x06
#define TIMER_TCVR1 0x08
#define TIMER_TRVR1 0x0A
#define TIMER_TCR1 0x0C
#define TIMER_TIDR 0x0E
#define IT_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs)) = data
#define IT_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs))
#define IT_IO_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
#define IT_IO_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
#define IT_IO_WRITE16(ofs, data) *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
#define IT_IO_READ16(ofs, data) data = *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
#endif
--- NEW FILE ---
/*
*
* BRIEF MODULE DESCRIPTION
* IT8172 Consumer IR port defines.
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* pp...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#define NUM_CIR_PORTS 2
/* Master Control Register */
#define CIR_RESET 0x1
#define CIR_FIFO_CLEAR 0x2
#define CIR_SET_FIFO_TL(x) (((x)&0x3)<<2)
#define CIR_ILE 0x10
#define CIR_ILSEL 0x20
/* Interrupt Enable Register */
#define CIR_TLDLIE 0x1
#define CIR_RDAIE 0x2
#define CIR_RFOIE 0x4
#define CIR_IEC 0x80
/* Interrupt Identification Register */
#define CIR_TLDLI 0x1
#define CIR_RDAI 0x2
#define CIR_RFOI 0x4
#define CIR_NIP 0x80
/* Carrier Frequency Register */
#define CIR_SET_CF(x) ((x)&0x1f)
#define CFQ_38_480 0xB /* 38 KHz low, 480 KHz high */
#define CIR_HCFS 0x20
#define CIR_SET_HS(x) (((x)&0x1)<<5)
/* Receiver Control Register */
#define CIR_SET_RXDCR(x) ((x)&0x7)
#define CIR_RXACT 0x8
#define CIR_RXEND 0x10
#define CIR_RDWOS 0x20
#define CIR_SET_RDWOS(x) (((x)&0x1)<<5)
#define CIR_RXEN 0x80
/* Transmitter Control Register */
#define CIR_SET_TXMPW(x) ((x)&0x7)
#define CIR_SET_TXMPM(x) (((x)&0x3)<<3)
#define CIR_TXENDF 0x20
#define CIR_TXRLE 0x40
/* Receiver FIFO Status Register */
#define CIR_RXFBC_MASK 0x3f
#define CIR_RXFTO 0x80
/* Wakeup Code Length Register */
#define CIR_SET_WCL ((x)&0x3f)
#define CIR_WCL_MASK(x) ((x)&0x3f)
/* Wakeup Power Control/Status Register */
#define CIR_BTMON 0x2
#define CIR_CIRON 0x4
#define CIR_RCRST 0x10
#define CIR_WCRST 0x20
struct cir_port {
int port;
unsigned short baud_rate;
unsigned char fifo_tl;
unsigned char cfq;
unsigned char hcfs;
unsigned char rdwos;
unsigned char rxdcr;
};
struct it8172_cir_regs {
unsigned char dr; /* data */
char pad;
unsigned char mstcr; /* master control */
char pad1;
unsigned char ier; /* interrupt enable */
char pad2;
unsigned char iir; /* interrupt identification */
char pad3;
unsigned char cfr; /* carrier frequency */
char pad4;
unsigned char rcr; /* receiver control */
char pad5;
unsigned char tcr; /* transmitter control */
char pad6;
char pad7;
char pad8;
unsigned char bdlr; /* baud rate divisor low byte */
char pad9;
unsigned char bdhr; /* baud rate divisor high byte */
char pad10;
unsigned char tfsr; /* tx fifo byte count */
char pad11;
unsigned char rfsr; /* rx fifo status */
char pad12;
unsigned char wcl; /* wakeup code length */
char pad13;
unsigned char wcr; /* wakeup code read/write */
char pad14;
unsigned char wps; /* wakeup power control/status */
};
int cir_port_init(struct cir_port *cir);
extern void clear_fifo(struct cir_port *cir);
extern void enable_receiver(struct cir_port *cir);
extern void disable_receiver(struct cir_port *cir);
extern void enable_rx_demodulation(struct cir_port *cir);
extern void disable_rx_demodulation(struct cir_port *cir);
extern void set_rx_active(struct cir_port *cir);
extern void int_enable(struct cir_port *cir);
extern void rx_int_enable(struct cir_port *cir);
extern char get_int_status(struct cir_port *cir);
extern int cir_get_rx_count(struct cir_port *cir);
extern char cir_read_data(struct cir_port *cir);
--- NEW FILE ---
/*
*
* BRIEF MODULE DESCRIPTION
* Function prototypes for low level uart routines to
* directly access a 16550 uart.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* pp...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
extern void putch(const unsigned char c);
extern void puts(unsigned char *cp);
extern void fputs(unsigned char *cp);
extern void put64(uint64_t ul);
extern void put32(unsigned u);
--- NEW FILE ---
/*
*
* BRIEF MODULE DESCRIPTION
* ITE 8172 Interrupt Numbering
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* pp...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _MIPS_ITEINT_H
#define _MIPS_ITEINT_H
/*
* Here's the "strategy":
* We number the LPC serial irqs from 0 to 15,
* the local bus irqs from 16 to 31,
* the pci dev register interrupts from 32 to 47,
* and the non-maskable ints from 48 to 53.
*/
#define IT8172_LPC_IRQ_BASE 0 /* first LPC int number */
#define IT8172_SERIRQ_0 (IT8172_LPC_IRQ_BASE + 0)
#define IT8172_SERIRQ_1 (IT8172_LPC_IRQ_BASE + 1)
#define IT8172_SERIRQ_2 (IT8172_LPC_IRQ_BASE + 2)
#define IT8172_SERIRQ_3 (IT8172_LPC_IRQ_BASE + 3)
#define IT8172_SERIRQ_4 (IT8172_LPC_IRQ_BASE + 4)
#define IT8172_SERIRQ_5 (IT8172_LPC_IRQ_BASE + 5)
#define IT8172_SERIRQ_6 (IT8172_LPC_IRQ_BASE + 6)
#define IT8172_SERIRQ_7 (IT8172_LPC_IRQ_BASE + 7)
#define IT8172_SERIRQ_8 (IT8172_LPC_IRQ_BASE + 8)
#define IT8172_SERIRQ_9 (IT8172_LPC_IRQ_BASE + 9)
#define IT8172_SERIRQ_10 (IT8172_LPC_IRQ_BASE + 10)
#define IT8172_SERIRQ_11 (IT8172_LPC_IRQ_BASE + 11)
#define IT8172_SERIRQ_12 (IT8172_LPC_IRQ_BASE + 12)
#define IT8172_SERIRQ_13 (IT8172_LPC_IRQ_BASE + 13)
#define IT8172_SERIRQ_14 (IT8172_LPC_IRQ_BASE + 14)
#define IT8172_SERIRQ_15 (IT8172_LPC_IRQ_BASE + 15)
#define IT8172_LB_IRQ_BASE 16 /* first local bus int number */
#define IT8172_PPR_IRQ (IT8172_LB_IRQ_BASE + 0) /* parallel port */
#define IT8172_TIMER0_IRQ (IT8172_LB_IRQ_BASE + 1)
#define IT8172_TIMER1_IRQ (IT8172_LB_IRQ_BASE + 2)
#define IT8172_I2C_IRQ (IT8172_LB_IRQ_BASE + 3)
#define IT8172_GPIO_IRQ (IT8172_LB_IRQ_BASE + 4)
#define IT8172_CIR0_IRQ (IT8172_LB_IRQ_BASE + 5)
#define IT8172_CIR1_IRQ (IT8172_LB_IRQ_BASE + 6)
#define IT8172_UART_IRQ (IT8172_LB_IRQ_BASE + 7)
#define IT8172_SCR0_IRQ (IT8172_LB_IRQ_BASE + 8)
#define IT8172_SCR1_IRQ (IT8172_LB_IRQ_BASE + 9)
#define IT8172_RTC_IRQ (IT8172_LB_IRQ_BASE + 10)
#define IT8172_IOCHK_IRQ (IT8172_LB_IRQ_BASE + 11)
/* 12 - 15 reserved */
/*
* Note here that the pci dev registers includes bits for more than
* just the pci devices.
*/
#define IT8172_PCI_DEV_IRQ_BASE 32 /* first pci dev irq */
#define IT8172_AC97_IRQ (IT8172_PCI_DEV_IRQ_BASE + 0)
#define IT8172_MC68K_IRQ (IT8172_PCI_DEV_IRQ_BASE + 1)
#define IT8172_IDE_IRQ (IT8172_PCI_DEV_IRQ_BASE + 2)
#define IT8172_USB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 3)
#define IT8172_BRIDGE_MASTER_IRQ (IT8172_PCI_DEV_IRQ_BASE + 4)
#define IT8172_BRIDGE_TARGET_IRQ (IT8172_PCI_DEV_IRQ_BASE + 5)
#define IT8172_PCI_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 6)
#define IT8172_PCI_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 7)
#define IT8172_PCI_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 8)
#define IT8172_PCI_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 9)
#define IT8172_S_INTA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 10)
#define IT8172_S_INTB_IRQ (IT8172_PCI_DEV_IRQ_BASE + 11)
#define IT8172_S_INTC_IRQ (IT8172_PCI_DEV_IRQ_BASE + 12)
#define IT8172_S_INTD_IRQ (IT8172_PCI_DEV_IRQ_BASE + 13)
#define IT8172_CDMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 14)
#define IT8172_DMA_IRQ (IT8172_PCI_DEV_IRQ_BASE + 15)
#define IT8172_NMI_IRQ_BASE 48
#define IT8172_SER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 0)
#define IT8172_PCI_NMI_IRQ (IT8172_NMI_IRQ_BASE + 1)
#define IT8172_RTC_NMI_IRQ (IT8172_NMI_IRQ_BASE + 2)
#define IT8172_CPUIF_NMI_IRQ (IT8172_NMI_IRQ_BASE + 3)
#define IT8172_PMER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 4)
#define IT8172_POWER_NMI_IRQ (IT8172_NMI_IRQ_BASE + 5)
/* Finally, let's move over here the mips cpu timer interrupt.
* This is more or less strictly for statistics.
*/
#define MIPS_CPU_TIMER_IRQ (IT8172_NMI_IRQ_BASE + 6)
#define IT8172_INT_END MIPS_CPU_TIMER_IRQ
/*
* IT8172 Interrupt Controller Registers
*/
struct it8172_intc_regs {
volatile unsigned short lb_req; /* offset 0 */
volatile unsigned short lb_mask;
volatile unsigned short lb_trigger;
volatile unsigned short lb_level;
unsigned char pad0[8];
volatile unsigned short lpc_req; /* offset 0x10 */
volatile unsigned short lpc_mask;
volatile unsigned short lpc_trigger;
volatile unsigned short lpc_level;
unsigned char pad1[8];
volatile unsigned short pci_req; /* offset 0x20 */
volatile unsigned short pci_mask;
volatile unsigned short pci_trigger;
volatile unsigned short pci_level;
unsigned char pad2[8];
volatile unsigned short nmi_req; /* offset 0x30 */
volatile unsigned short nmi_mask;
volatile unsigned short nmi_trigger;
volatile unsigned short nmi_level;
unsigned char pad3[6];
volatile unsigned short nmi_redir; /* offset 0x3E */
unsigned char pad4[0xBE];
volatile unsigned short intstatus; /* offset 0xFE */
};
#endif /* _MIPS_ITEINT_H */
--- NEW FILE ---
/*
*
* BRIEF MODULE DESCRIPTION
* IT8172 system controller defines.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* pp...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
--- NEW FILE ---
/*
*
* BRIEF MODULE DESCRIPTION
* IT8172 system controller specific pci defines.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* pp...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _8172PCI_H_
#define _8172PCI_H_
// PCI configuration space Type0
#define PCI_IDREG 0x00
#define PCI_CMDSTSREG 0x04
#define PCI_CLASSREG 0x08
#define PCI_BHLCREG 0x0C
#define PCI_BASE1REG 0x10
#define PCI_BASE2REG 0x14
#define PCI_BASE3REG 0x18
#define PCI_BASE4REG 0x1C
#define PCI_BASE5REG 0x20
#define PCI_BASE6REG 0x24
#define PCI_ROMBASEREG 0x30
#define PCI_INTRREG 0x3C
// PCI configuration space Type1
#define PCI_BUSNOREG 0x18
#define IT_PCI_VENDORID(x) ((x) & 0xFFFF)
#define IT_PCI_DEVICEID(x) (((x)>>16) & 0xFFFF)
// Command register
#define PCI_CMD_IOEN 0x00000001
#define PCI_CMD_MEMEN 0x00000002
#define PCI_CMD_BUSMASTER 0x00000004
#define PCI_CMD_SPCYCLE 0x00000008
#define PCI_CMD_WRINV 0x00000010
#define PCI_CMD_VGASNOOP 0x00000020
#define PCI_CMD_PERR 0x00000040
#define PCI_CMD_WAITCTRL 0x00000080
#define PCI_CMD_SERR 0x00000100
#define PCI_CMD_FAST_BACKTOBACK 0x00000200
// Status register
#define PCI_STS_66MHZ 0x00200000
#define PCI_STS_SUPPORT_UDF 0x00400000
#define PCI_STS_FAST_BACKTOBACK 0x00800000
#define PCI_STS_DATA_PERR 0x01000000
#define PCI_STS_DEVSEL0 0x02000000
#define PCI_STS_DEVSEL1 0x04000000
#define PCI_STS_SIG_TGTABORT 0x08000000
#define PCI_STS_RCV_TGTABORT 0x10000000
#define PCI_STS_RCV_MSTABORT 0x20000000
#define PCI_STS_SYSERR 0x40000000
#define PCI_STS_DETCT_PERR 0x80000000
#define IT_PCI_CLASS(x) (((x)>>24) & 0xFF)
#define IT_PCI_SUBCLASS(x) (((x)>>16) & 0xFF)
#define IT_PCI_INTERFACE(x) (((x)>>8) & 0xFF)
#define IT_PCI_REVISION(x) ((x) & 0xFF)
// PCI class code
#define PCI_CLASS_BRIDGE 0x06
// bridge subclass
#define PCI_SUBCLASS_BRIDGE_HOST 0x00
#define PCI_SUBCLASS_BRIDGE_PCI 0x04
// BHLCREG
#define IT_PCI_BIST(x) (((x)>>24) & 0xFF)
#define IT_PCI_HEADERTYPE(x) (((x)>>16) & 0xFF)
#define IT_PCI_LATENCYTIMER(x) (((x)>>8) & 0xFF)
#define IT_PCI_CACHELINESIZE(x) ((x) & 0xFF)
#define PCI_MULTIFUNC 0x80
// INTRREG
#define IT_PCI_MAXLAT(x) (((x)>>24) & 0xFF)
#define IT_PCI_MINGNT(x) (((x)>>16) & 0xFF)
#define IT_PCI_INTRPIN(x) (((x)>>8) & 0xFF)
#define IT_PCI_INTRLINE(x) ((x) & 0xFF)
#define PCI_VENDOR_NEC 0x1033
#define PCI_VENDOR_DEC 0x1101
#endif // _8172PCI_H_
|
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:29
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/gt64120 In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-mips/gt64120 Added Files: gt64120.h Log Message: Synch to 2.4.15 commit 1 --- NEW FILE --- /* * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. * Carsten Langgaard, car...@mi... * * Copyright 2001 MontaVista Software Inc. * Author: Jun Sun, js...@mv... or js...@ju... * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. */ #ifndef _ASM_GT64120_GT64120_H #define _ASM_GT64120_GT64120_H #define MSK(n) ((1 << (n)) - 1) /* * Register offset addresses */ #define GT_CPU_OFS 0x000 /* * Interrupt Registers */ #define GT_SCS10LD_OFS 0x008 #define GT_SCS10HD_OFS 0x010 #define GT_SCS32LD_OFS 0x018 #define GT_SCS32HD_OFS 0x020 #define GT_CS20LD_OFS 0x028 #define GT_CS20HD_OFS 0x030 #define GT_CS3BOOTLD_OFS 0x038 #define GT_CS3BOOTHD_OFS 0x040 #define GT_PCI0IOLD_OFS 0x048 #define GT_PCI0IOHD_OFS 0x050 #define GT_PCI0M0LD_OFS 0x058 #define GT_PCI0M0HD_OFS 0x060 #define GT_ISD_OFS 0x068 #define GT_PCI0M1LD_OFS 0x080 #define GT_PCI0M1HD_OFS 0x088 #define GT_PCI1IOLD_OFS 0x090 #define GT_PCI1IOHD_OFS 0x098 #define GT_PCI1M0LD_OFS 0x0a0 #define GT_PCI1M0HD_OFS 0x0a8 #define GT_PCI1M1LD_OFS 0x0b0 #define GT_PCI1M1HD_OFS 0x0b8 /* * GT64120A only */ #define GT_PCI0IOREMAP_OFS 0x0f0 #define GT_PCI0M0REMAP_OFS 0x0f8 #define GT_PCI0M1REMAP_OFS 0x100 #define GT_PCI1IOREMAP_OFS 0x108 #define GT_PCI1M0REMAP_OFS 0x110 #define GT_PCI1M1REMAP_OFS 0x118 #define GT_SCS0LD_OFS 0x400 #define GT_SCS0HD_OFS 0x404 #define GT_SCS1LD_OFS 0x408 #define GT_SCS1HD_OFS 0x40c #define GT_SCS2LD_OFS 0x410 #define GT_SCS2HD_OFS 0x414 #define GT_SCS3LD_OFS 0x418 #define GT_SCS3HD_OFS 0x41c #define GT_CS0LD_OFS 0x420 #define GT_CS0HD_OFS 0x424 #define GT_CS1LD_OFS 0x428 #define GT_CS1HD_OFS 0x42c #define GT_CS2LD_OFS 0x430 #define GT_CS2HD_OFS 0x434 #define GT_CS3LD_OFS 0x438 #define GT_CS3HD_OFS 0x43c #define GT_BOOTLD_OFS 0x440 #define GT_BOOTHD_OFS 0x444 #define GT_SDRAM_B0_OFS 0x44c #define GT_SDRAM_CFG_OFS 0x448 #define GT_SDRAM_B2_OFS 0x454 #define GT_SDRAM_OPMODE_OFS 0x474 #define GT_SDRAM_BM_OFS 0x478 #define GT_SDRAM_ADDRDECODE_OFS 0x47c #define GT_PCI0_CMD_OFS 0xc00 /* GT64120A only */ #define GT_PCI0_TOR_OFS 0xc04 #define GT_PCI0_BS_SCS10_OFS 0xc08 #define GT_PCI0_BS_SCS32_OFS 0xc0c #define GT_INTRCAUSE_OFS 0xc18 #define GT_INTRMASK_OFS 0xc1c /* GT64120A only */ #define GT_PCI0_IACK_OFS 0xc34 #define GT_PCI0_BARE_OFS 0xc3c #define GT_HINTRCAUSE_OFS 0xc98 /* GT64120A only */ #define GT_HINTRMASK_OFS 0xc9c /* GT64120A only */ #define GT_PCI1_CFGADDR_OFS 0xcf0 /* GT64120A only */ #define GT_PCI1_CFGDATA_OFS 0xcf4 /* GT64120A only */ #define GT_PCI0_CFGADDR_OFS 0xcf8 #define GT_PCI0_CFGDATA_OFS 0xcfc /* * Timer/Counter. GT64120A only. */ #define GT_TC0_OFS 0x850 #define GT_TC1_OFS 0x854 #define GT_TC2_OFS 0x858 #define GT_TC3_OFS 0x85C #define GT_TC_CONTROL_OFS 0x864 /* * I2O Support Registers */ #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c /* * Register encodings */ #define GT_CPU_ENDIAN_SHF 12 #define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) #define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK #define GT_CPU_WR_SHF 16 #define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) #define GT_CPU_WR_BIT GT_CPU_WR_MSK #define GT_CPU_WR_DXDXDXDX 0 #define GT_CPU_WR_DDDD 1 #define GT_CFGADDR_CFGEN_SHF 31 #define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) #define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK #define GT_CFGADDR_BUSNUM_SHF 16 #define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) #define GT_CFGADDR_DEVNUM_SHF 11 #define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) #define GT_CFGADDR_FUNCNUM_SHF 8 #define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) #define GT_CFGADDR_REGNUM_SHF 2 #define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) #define GT_SDRAM_BM_ORDER_SHF 2 #define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) #define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK #define GT_SDRAM_BM_ORDER_SUB 1 #define GT_SDRAM_BM_ORDER_LIN 0 #define GT_SDRAM_BM_RSVD_ALL1 0xffb #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 #define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) #define GT_SDRAM_ADDRDECODE_ADDR_0 0 #define GT_SDRAM_ADDRDECODE_ADDR_1 1 #define GT_SDRAM_ADDRDECODE_ADDR_2 2 #define GT_SDRAM_ADDRDECODE_ADDR_3 3 #define GT_SDRAM_ADDRDECODE_ADDR_4 4 #define GT_SDRAM_ADDRDECODE_ADDR_5 5 #define GT_SDRAM_ADDRDECODE_ADDR_6 6 #define GT_SDRAM_ADDRDECODE_ADDR_7 7 #define GT_SDRAM_B0_CASLAT_SHF 0 #define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) #define GT_SDRAM_B0_CASLAT_2 1 #define GT_SDRAM_B0_CASLAT_3 2 #define GT_SDRAM_B0_FTDIS_SHF 2 #define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) #define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK #define GT_SDRAM_B0_SRASPRCHG_SHF 3 #define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) #define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK #define GT_SDRAM_B0_SRASPRCHG_2 0 #define GT_SDRAM_B0_SRASPRCHG_3 1 #define GT_SDRAM_B0_B0COMPAB_SHF 4 #define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) #define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK #define GT_SDRAM_B0_64BITINT_SHF 5 #define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) #define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK #define GT_SDRAM_B0_64BITINT_2 0 #define GT_SDRAM_B0_64BITINT_4 1 #define GT_SDRAM_B0_BW_SHF 6 #define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) #define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK #define GT_SDRAM_B0_BW_32 0 #define GT_SDRAM_B0_BW_64 1 #define GT_SDRAM_B0_BLODD_SHF 7 #define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) #define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK #define GT_SDRAM_B0_PAR_SHF 8 #define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) #define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK #define GT_SDRAM_B0_BYPASS_SHF 9 #define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) #define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK #define GT_SDRAM_B0_SRAS2SCAS_SHF 10 #define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) #define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK #define GT_SDRAM_B0_SRAS2SCAS_2 0 #define GT_SDRAM_B0_SRAS2SCAS_3 1 #define GT_SDRAM_B0_SIZE_SHF 11 #define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) #define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK #define GT_SDRAM_B0_SIZE_16M 0 #define GT_SDRAM_B0_SIZE_64M 1 #define GT_SDRAM_B0_EXTPAR_SHF 12 #define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) #define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK #define GT_SDRAM_B0_BLEN_SHF 13 #define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) #define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK #define GT_SDRAM_B0_BLEN_8 0 #define GT_SDRAM_B0_BLEN_4 1 #define GT_SDRAM_CFG_REFINT_SHF 0 #define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) #define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 #define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) #define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK #define GT_SDRAM_CFG_RMW_SHF 15 #define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) #define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK #define GT_SDRAM_CFG_NONSTAGREF_SHF 16 #define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) #define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK #define GT_SDRAM_CFG_DUPCNTL_SHF 19 #define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) #define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK #define GT_SDRAM_CFG_DUPBA_SHF 20 #define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) #define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK #define GT_SDRAM_CFG_DUPEOT0_SHF 21 #define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) #define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK #define GT_SDRAM_CFG_DUPEOT1_SHF 22 #define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) #define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK #define GT_SDRAM_OPMODE_OP_SHF 0 #define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) #define GT_SDRAM_OPMODE_OP_NORMAL 0 #define GT_SDRAM_OPMODE_OP_NOP 1 #define GT_SDRAM_OPMODE_OP_PRCHG 2 #define GT_SDRAM_OPMODE_OP_MODE 3 #define GT_SDRAM_OPMODE_OP_CBR 4 #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 #define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) #define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK #define GT_PCI0_BARE_SWSCS32DIS_SHF 1 #define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) #define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK #define GT_PCI0_BARE_SWSCS10DIS_SHF 2 #define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) #define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK #define GT_PCI0_BARE_INTIODIS_SHF 3 #define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) #define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK #define GT_PCI0_BARE_INTMEMDIS_SHF 4 #define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) #define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK #define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 #define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) #define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK #define GT_PCI0_BARE_CS20DIS_SHF 6 #define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) #define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK #define GT_PCI0_BARE_SCS32DIS_SHF 7 #define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) #define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK #define GT_PCI0_BARE_SCS10DIS_SHF 8 #define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) #define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK #define GT_INTRCAUSE_MASABORT0_SHF 18 #define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) #define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK #define GT_INTRCAUSE_TARABORT0_SHF 19 #define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK #define GT_PCI0_CFGADDR_REGNUM_SHF 2 #define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) #define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 #define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) #define GT_PCI0_CFGADDR_DEVNUM_SHF 11 #define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) #define GT_PCI0_CFGADDR_BUSNUM_SHF 16 #define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) #define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 #define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) #define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK #define GT_PCI0_CMD_MBYTESWAP_SHF 0 #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK #define GT_PCI0_CMD_MWORDSWAP_SHF 10 #define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) #define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK #define GT_PCI0_CMD_SBYTESWAP_SHF 16 #define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) #define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK #define GT_PCI0_CMD_SWORDSWAP_SHF 11 #define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) #define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK /* * Misc */ #define GT_DEF_BASE 0x14000000 #define GT_DEF_PCI0_IO_BASE 0x10000000 #define GT_DEF_PCI0_IO_SIZE 0x02000000 #define GT_DEF_PCI0_MEM0_BASE 0x12000000 #define GT_DEF_PCI0_MEM0_SIZE 0x02000000 #define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ #define GT_LATTIM_MIN 6 /* Minimum lat */ /*********************************************************************** * BOARD-DEPENDENT SECTIONS * *********************************************************************** */ /* * include asm/gt64120/<board>/gt64120_dep.h file */ #include <linux/config.h> #include <linux/init.h> #if defined(CONFIG_MOMENCO_OCELOT) #include <asm/gt64120/momenco_ocelot/gt64120_dep.h> #endif /* * The gt64120_dep.h file must define the following macros * * GT_READ(ofs, data_pointer) * GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit * * TIMER - gt64120 timer irq, temporary solution until * full gt64120 cascade interrupt support is in place */ /* * Board-dependent functions, which must be defined in * arch/mips/gt64120/<board>/pci.c file. * * This function is called by pcibios_fixup_bus(bus), which in turn is * invoked a bus is scanned. You typically fixes IRQ numbers in this routine. */ extern void __init gt64120_board_pcibios_fixup_bus(struct pci_bus *bus); #endif /* _ASM_GT64120_GT64120_H */ |
|
From: Andy P. <at...@us...> - 2002-04-09 12:33:29
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/gt64120/momenco_ocelot
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-mips/gt64120/momenco_ocelot
Added Files:
gt64120_dep.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/***********************************************************************
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
*
* include/asm-mips/gt64120/momenco-ocelot/gt64120-dep.h
* Board-dependent definitions for GT-64120 chip.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
***********************************************************************
*/
#ifndef _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H
#define _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H
#include <asm/addrspace.h> /* for KSEG1ADDR() */
#include <asm/byteorder.h> /* for cpu_to_le32() */
/*
* PCI address allocation
*/
#define GT_PCI_MEM_BASE (0x22000000)
#define GT_PCI_MEM_SIZE GT_DEF_PCI0_MEM0_SIZE
#define GT_PCI_IO_BASE (0x20000000)
#define GT_PCI_IO_SIZE GT_DEF_PCI0_IO_SIZE
extern unsigned long gt64120_base;
#define GT64120_BASE (gt64120_base)
/*
* Because of an error/peculiarity in the Galileo chip, we need to swap the
* bytes when running bigendian.
*/
#define GT_WRITE(ofs, data) \
*(volatile u32 *)(GT64120_BASE+ofs) = cpu_to_le32(data)
#define GT_READ(ofs, data) \
*data = le32_to_cpu(*(volatile u32 *)(GT64120_BASE+ofs))
/*
* gt timer irq
*/
#define TIMER 6
#endif /* _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H */
|
Update of /cvsroot/linux-vax/kernel-2.4/include/asm-mips/mips-boards
In directory usw-pr-cvs1:/tmp/cvs-serv9454/asm-mips/mips-boards
Added Files:
atlas.h atlasint.h generic.h malta.h maltaint.h piix4.h prom.h
saa9730_uart.h
Log Message:
Synch to 2.4.15 commit 1
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the Atlas board specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_ATLAS_H
#define _MIPS_ATLAS_H
#include <asm/addrspace.h>
/*
* Atlas RTC-device indirect register access.
*/
#define ATLAS_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
#define ATLAS_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
/*
* Atlas interrupt controller register base.
*/
#define ATLAS_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
/*
* Atlas UART register base.
*/
#define ATLAS_UART_REGS_BASE (0x1f000900)
#define ATLAS_BASE_BAUD ( 3686400 / 16 )
/*
* Atlas PSU standby register.
*/
#define ATLAS_PSUSTBY_REG (KSEG1ADDR(0x1f000600))
#define ATLAS_GOSTBY 0x4d
/*
* We make a universal assumption about the way the bootloader (YAMON)
* have located the Philips SAA9730 chip.
* This is not ideal, but is needed for setting up remote debugging as
* soon as possible.
*/
#define ATLAS_SAA9730_REG (KSEG1ADDR(0x08800000))
#endif /* !(_MIPS_ATLAS_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines for the Atlas interrupt controller.
*
*/
#ifndef _MIPS_ATLASINT_H
#define _MIPS_ATLASINT_H
/* Number of IRQ supported on hw interrupt 0. */
#define ATLASINT_UART 0
#define ATLASINT_END 32
/*
* Atlas registers are memory mapped on 64-bit aligned boundaries and
* only word access are allowed.
*/
struct atlas_ictrl_regs {
volatile unsigned long intraw;
long dummy1;
volatile unsigned long intseten;
long dummy2;
volatile unsigned long intrsten;
long dummy3;
volatile unsigned long intenable;
long dummy4;
volatile unsigned long intstatus;
long dummy5;
};
extern void atlasint_init(void);
#endif /* !(_MIPS_ATLASINT_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the MIPS boards specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_GENERIC_H
#define _MIPS_GENERIC_H
#include <asm/addrspace.h>
#include <asm/byteorder.h>
/*
* Display register base.
*/
#define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410))
#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418))
/*
* Yamon Prom print address.
*/
#define YAMON_PROM_PRINT_ADDR (KSEG1ADDR(0x1fc00504))
/*
* Reset register.
*/
#define SOFTRES_REG (KSEG1ADDR(0x1f000500))
#define GORESET 0x42
/*
* Galileo GT64120 system controller register base.
*/
#define MIPS_GT_BASE (KSEG1ADDR(0x1be00000))
/*
* Because of the way the internal register works on the Galileo chip,
* we need to swap the bytes when running bigendian.
*/
#define GT_WRITE(ofs, data) \
*(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data)
#define GT_READ(ofs, data) \
data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs))
#define GT_PCI_WRITE(ofs, data) \
*(volatile u32 *)(MIPS_GT_BASE+ofs) = data
#define GT_PCI_READ(ofs, data) \
data = *(volatile u32 *)(MIPS_GT_BASE+ofs)
#endif /* !(_MIPS_GENERIC_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the Malta board specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_MALTA_H
#define _MIPS_MALTA_H
#include <asm/addrspace.h>
#include <asm/io.h>
/*
* Malta I/O ports base address.
*/
#define MALTA_PORT_BASE (KSEG1ADDR(0x18000000))
/*
* Malta RTC-device indirect register access.
*/
#define MALTA_RTC_ADR_REG 0x70
#define MALTA_RTC_DAT_REG 0x71
/*
* Malta SMSC FDC37M817 Super I/O Controller register.
*/
#define SMSC_CONFIG_REG 0x3f0
#define SMSC_DATA_REG 0x3f1
#define SMSC_CONFIG_DEVNUM 0x7
#define SMSC_CONFIG_ACTIVATE 0x30
#define SMSC_CONFIG_ENTER 0x55
#define SMSC_CONFIG_EXIT 0xaa
#define SMSC_CONFIG_DEVNUM_FLOPPY 0
#define SMSC_CONFIG_ACTIVATE_ENABLE 1
#define SMSC_WRITE(x,a) outb(x,a)
#endif /* !(_MIPS_MALTA_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines for the Malta interrupt controller.
*
*/
#ifndef _MIPS_MALTAINT_H
#define _MIPS_MALTAINT_H
/* Number of IRQ supported on hw interrupt 0. */
#define MALTAINT_END 16
extern void maltaint_init(void);
#endif /* !(_MIPS_MALTAINT_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Register definitions for Intel PIIX4 South Bridge Device.
*
*/
#ifndef PIIX4_H
#define PIIX4_H
/************************************************************************
* IO register offsets
************************************************************************/
#define PIIX4_ICTLR1_ICW1 0x20
#define PIIX4_ICTLR1_ICW2 0x21
#define PIIX4_ICTLR1_ICW3 0x21
#define PIIX4_ICTLR1_ICW4 0x21
#define PIIX4_ICTLR2_ICW1 0xa0
#define PIIX4_ICTLR2_ICW2 0xa1
#define PIIX4_ICTLR2_ICW3 0xa1
#define PIIX4_ICTLR2_ICW4 0xa1
#define PIIX4_ICTLR1_OCW1 0x21
#define PIIX4_ICTLR1_OCW2 0x20
#define PIIX4_ICTLR1_OCW3 0x20
#define PIIX4_ICTLR1_OCW4 0x20
#define PIIX4_ICTLR2_OCW1 0xa1
#define PIIX4_ICTLR2_OCW2 0xa0
#define PIIX4_ICTLR2_OCW3 0xa0
#define PIIX4_ICTLR2_OCW4 0xa0
/************************************************************************
* Register encodings.
************************************************************************/
#define PIIX4_OCW2_NSEOI (0x1 << 5)
#define PIIX4_OCW2_SEOI (0x3 << 5)
#define PIIX4_OCW2_RNSEOI (0x5 << 5)
#define PIIX4_OCW2_RAEOIS (0x4 << 5)
#define PIIX4_OCW2_RAEOIC (0x0 << 5)
#define PIIX4_OCW2_RSEOI (0x7 << 5)
#define PIIX4_OCW2_SP (0x6 << 5)
#define PIIX4_OCW2_NOP (0x2 << 5)
#define PIIX4_OCW2_SEL (0x0 << 3)
#define PIIX4_OCW2_ILS_0 0
#define PIIX4_OCW2_ILS_1 1
#define PIIX4_OCW2_ILS_2 2
#define PIIX4_OCW2_ILS_3 3
#define PIIX4_OCW2_ILS_4 4
#define PIIX4_OCW2_ILS_5 5
#define PIIX4_OCW2_ILS_6 6
#define PIIX4_OCW2_ILS_7 7
#define PIIX4_OCW2_ILS_8 0
#define PIIX4_OCW2_ILS_9 1
#define PIIX4_OCW2_ILS_10 2
#define PIIX4_OCW2_ILS_11 3
#define PIIX4_OCW2_ILS_12 4
#define PIIX4_OCW2_ILS_13 5
#define PIIX4_OCW2_ILS_14 6
#define PIIX4_OCW2_ILS_15 7
#define PIIX4_OCW3_SEL (0x1 << 3)
#define PIIX4_OCW3_IRR 0x2
#define PIIX4_OCW3_ISR 0x3
#endif /* !(PIIX4_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* MIPS boards bootprom interface for the Linux kernel.
*
*/
#ifndef _MIPS_PROM_H
#define _MIPS_PROM_H
extern char *prom_getcmdline(void);
extern char *prom_getenv(char *name);
extern void setup_prom_printf(int tty_no);
extern void prom_printf(char *fmt, ...);
extern void prom_init_cmdline(void);
extern void prom_meminit(void);
extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
extern void prom_free_prom_memory (void);
extern void mips_display_message(const char *str);
extern void mips_display_word(unsigned int num);
extern int get_ethernet_addr(char *ethernet_addr);
/* Memory descriptor management. */
#define PROM_MAX_PMEMBLOCKS 32
struct prom_pmemblock {
unsigned long base; /* Within KSEG0. */
unsigned int size; /* In bytes. */
unsigned int type; /* free or prom memory */
};
#endif /* !(_MIPS_PROM_H) */
--- NEW FILE ---
/*
* Carsten Langgaard, car...@mi...
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Register definitions for the UART part of the Philips SAA9730 chip.
*
*/
#ifndef SAA9730_UART_H
#define SAA9730_UART_H
/* The SAA9730 UART register map, as seen via the PCI bus */
#define SAA9730_UART_REGS_ADDR 0x21800
struct uart_saa9730_regmap {
volatile unsigned char Thr_Rbr;
volatile unsigned char Ier;
volatile unsigned char Iir_Fcr;
volatile unsigned char Lcr;
volatile unsigned char Mcr;
volatile unsigned char Lsr;
volatile unsigned char Msr;
volatile unsigned char Scr;
volatile unsigned char BaudDivLsb;
volatile unsigned char BaudDivMsb;
volatile unsigned char Junk0;
volatile unsigned char Junk1;
volatile unsigned int Config; /* 0x2180c */
volatile unsigned int TxStart; /* 0x21810 */
volatile unsigned int TxLength; /* 0x21814 */
volatile unsigned int TxCounter; /* 0x21818 */
volatile unsigned int RxStart; /* 0x2181c */
volatile unsigned int RxLength; /* 0x21820 */
volatile unsigned int RxCounter; /* 0x21824 */
};
typedef volatile struct uart_saa9730_regmap t_uart_saa9730_regmap;
/*
* Only a subset of the UART control bits are defined here,
* enough to make the serial debug port work.
*/
#define SAA9730_LCR_DATA8 0x03
#define SAA9730_MCR_DTR 0x01
#define SAA9730_MCR_RTS 0x02
#define SAA9730_LSR_DR 0x01
#define SAA9730_LSR_THRE 0x20
#endif /* !(SAA9730_UART_H) */
|
