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From: James S. <jsi...@us...> - 2002-05-30 20:42:44
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv29100/arch/mips/mm
Modified Files:
c-mips32.c
Log Message:
Updated Mips 64 to OSS tree.
Index: c-mips32.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-mips32.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- c-mips32.c 28 Jan 2002 23:15:25 -0000 1.4
+++ c-mips32.c 30 May 2002 20:42:08 -0000 1.5
@@ -17,6 +17,7 @@
*
* MIPS32 CPU variant specific MMU/Cache routines.
*/
+#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
@@ -158,10 +159,6 @@
}
}
-
-
-
-
static void mips32_flush_cache_page_sc(struct vm_area_struct *vma,
unsigned long page)
{
@@ -413,6 +410,13 @@
protected_flush_icache_line(addr & ~(ic_lsize - 1));
}
+static void mips32_flush_icache_all(void)
+{
+ if (mips_cpu.cputype == CPU_20KC) {
+ blast_icache();
+ }
+}
+
/* Detect and size the various caches. */
static void __init probe_icache(unsigned long config)
{
@@ -665,6 +669,7 @@
_flush_cache_sigtramp = mips32_flush_cache_sigtramp;
_flush_icache_range = mips32_flush_icache_range; /* Ouch */
+ _flush_icache_all = mips32_flush_icache_all;
__flush_cache_all();
}
|
|
From: James S. <jsi...@us...> - 2002-05-30 20:42:44
|
Update of /cvsroot/linux-mips/linux/arch/mips64
In directory usw-pr-cvs1:/tmp/cvs-serv29100/arch/mips64
Modified Files:
config.in defconfig
Log Message:
Updated Mips 64 to OSS tree.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/config.in,v
retrieving revision 1.16
retrieving revision 1.17
diff -u -d -r1.16 -r1.17
--- config.in 21 Apr 2002 20:01:14 -0000 1.16
+++ config.in 30 May 2002 20:42:08 -0000 1.17
@@ -5,7 +5,7 @@
define_bool CONFIG_MIPS y
define_bool CONFIG_MIPS64 y
-mainmenu_name "Linux Kernel Configuration"
+mainmenu_name "Linux/MIPS64 Kernel Configuration"
mainmenu_option next_comment
comment 'Code maturity level options'
@@ -13,16 +13,31 @@
endmenu
mainmenu_option next_comment
-comment 'Machine selection'
-if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
- bool 'Support for MIPS Atlas board' CONFIG_MIPS_ATLAS
- bool 'Support for MIPS Malta board' CONFIG_MIPS_MALTA
+comment 'Loadable module support'
+bool 'Enable loadable module support' CONFIG_MODULES
+if [ "$CONFIG_MODULES" = "y" ]; then
+ bool ' Set version information on all module symbols' CONFIG_MODVERSIONS
+ bool ' Kernel module loader' CONFIG_KMOD
fi
-bool ' Support for SGI-IP27 (Origin200/2000)' CONFIG_SGI_IP27
-if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
- bool ' Support for SGI-IP22 (Indy/Indigo2)' CONFIG_SGI_IP22
- bool ' Support for SGI-IP32 (O2)' CONFIG_SGI_IP32
+endmenu
+
+mainmenu_option next_comment
+comment 'Machine selection'
+dep_bool 'Support for MIPS Atlas board (EXPERIMENTAL)' CONFIG_MIPS_ATLAS $CONFIG_EXPERIMENTAL
+dep_bool 'Support for MIPS Malta board (EXPERIMENTAL)' CONFIG_MIPS_MALTA $CONFIG_EXPERIMENTAL
+bool 'Support for SGI-IP27 (Origin200/2000)' CONFIG_SGI_IP27
+if [ "$CONFIG_SGI_IP27" = "y" ]; then
+ bool ' IP27 N-Mode' CONFIG_SGI_SN0_N_MODE
+ bool ' Discontiguous Memory Support' CONFIG_DISCONTIGMEM
+ bool ' NUMA support' CONFIG_NUMA
+ bool ' Mapped kernel support' CONFIG_MAPPED_KERNEL
+ bool ' Kernel text replication support' CONFIG_REPLICATE_KTEXT
+ bool ' Exception handler replication support' CONFIG_REPLICATE_EXHANDLERS
+ bool ' Multi-Processing support' CONFIG_SMP
+ #bool ' IP27 XXL' CONFIG_SGI_SN0_XXL
fi
+dep_bool 'Support for SGI-IP22 (Indy/Indigo2) (EXPERIMENTAL)' CONFIG_SGI_IP22 $CONFIG_EXPERIMENTAL
+dep_bool 'Support for SGI-IP32 (O2) (EXPERIMENTAL)' CONFIG_SGI_IP32 $CONFIG_EXPERIMENTAL
bool 'Support for SiByte SB1250 SOC' CONFIG_SIBYTE_SB1250
if [ "$CONFIG_SIBYTE_SB1250" = "y" ]; then
bool ' Support for SB1250 onchip PCI controller' CONFIG_PCI
@@ -33,28 +48,16 @@
if [ "$CONFIG_SIBYTE_SWARM" = "y" ]; then
bool ' Running under simulation' CONFIG_SIMULATION
bool ' Configure for L3proc Demo' CONFIG_L3DEMO
- int ' Maximum memory chunks' CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS 16
- bool ' Multi-Processing support' CONFIG_SMP
+ int ' Maximum memory chunks' CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS 16
+ bool ' Multi-Processing support' CONFIG_SMP
fi
fi
-if [ "$CONFIG_SGI_IP27" = "y" ]; then
- bool ' IP27 N-Mode' CONFIG_SGI_SN0_N_MODE
- bool ' Discontiguous Memory Support' CONFIG_DISCONTIGMEM
- bool ' NUMA support' CONFIG_NUMA
- bool ' Mapped kernel support' CONFIG_MAPPED_KERNEL
- bool ' Kernel text replication support' CONFIG_REPLICATE_KTEXT
- bool ' Exception handler replication support' CONFIG_REPLICATE_EXHANDLERS
- bool ' Multi-Processing support' CONFIG_SMP
- #bool ' IP27 XXL' CONFIG_SGI_SN0_XXL
-fi
-endmenu
-
define_bool CONFIG_RWSEM_GENERIC_SPINLOCK y
define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
#
-# Select some configuration options automatically based on user selections
+# Select some configuration options automatically based on user selections.
#
if [ "$CONFIG_MIPS_ATLAS" = "y" ]; then
@@ -64,7 +67,6 @@
define_bool CONFIG_PCI y
define_bool CONFIG_SWAP_IO_SPACE y
fi
-
if [ "$CONFIG_MIPS_MALTA" = "y" ]; then
define_bool CONFIG_BOOT_ELF32 y
define_bool CONFIG_I8259 y
@@ -73,7 +75,6 @@
define_bool CONFIG_PCI y
define_bool CONFIG_SWAP_IO_SPACE y
fi
-
if [ "$CONFIG_SGI_IP22" = "y" ]; then
define_bool CONFIG_ARC32 y
define_bool CONFIG_ARC_CONSOLE y
@@ -86,7 +87,6 @@
define_bool CONFIG_SGI y
define_int CONFIG_L1_CACHE_SHIFT 5
fi
-
if [ "$CONFIG_SGI_IP27" = "y" ]; then
define_bool CONFIG_BOOT_ELF64 y
define_bool CONFIG_ARC64 y
@@ -95,7 +95,6 @@
define_bool CONFIG_QL_ISP_A64 y
define_int CONFIG_L1_CACHE_SHIFT 7
fi
-
if [ "$CONFIG_SGI_IP32" = "y" ]; then
define_bool CONFIG_BOOT_ELF32 y
define_bool CONFIG_ARC32 y
@@ -107,7 +106,6 @@
define_bool CONFIG_ARC_MEMORY y
define_int CONFIG_L1_CACHE_SHIFT 5
fi
-
if [ "$CONFIG_SIBYTE_SWARM" = "y" ]; then
define_bool CONFIG_BOOT_ELF32 y
define_bool CONFIG_SWAP_IO_SPACE y
@@ -115,32 +113,19 @@
define_bool CONFIG_SIBYTE_SB1250 y
define_int CONFIG_L1_CACHE_SHIFT 5
fi
-
-if [ "$CONFIG_ISA" != "y" ]; then
- define_bool CONFIG_ISA n
- define_bool CONFIG_EISA n
-else
- define_bool CONFIG_EISA y
-fi
-
-if [ "$CONFIG_PCI" != "y" ]; then
- define_bool CONFIG_PCI n
-fi
-
-define_bool CONFIG_MCA n
-define_bool CONFIG_SBUS n
+endmenu
mainmenu_option next_comment
comment 'CPU selection'
-choice 'CPU type' \
- "R4300 CONFIG_CPU_R4300 \
- R4x00 CONFIG_CPU_R4X00 \
- R5000 CONFIG_CPU_R5000 \
- R52x0 CONFIG_CPU_NEVADA \
- R8000 CONFIG_CPU_R8000 \
- R10000 CONFIG_CPU_R10000 \
- SB1 CONFIG_CPU_SB1" R4x00
+choice 'CPU type' \
+ "R4300 CONFIG_CPU_R4300 \
+ R4x00 CONFIG_CPU_R4X00 \
+ R5000 CONFIG_CPU_R5000 \
+ R52x0 CONFIG_CPU_NEVADA \
+ R8000 CONFIG_CPU_R8000 \
+ R10000 CONFIG_CPU_R10000 \
+ SB1 CONFIG_CPU_SB1" R4x00
endmenu
if [ "$CONFIG_CPU_SB1" = "y" ]; then
@@ -160,10 +145,28 @@
fi
bool 'Generate little endian code' CONFIG_CPU_LITTLE_ENDIAN
+if [ "$CONFIG_ARC32" = "y" ]; then
+ bool 'ARC console support' CONFIG_ARC_CONSOLE
+fi
+
bool 'Networking support' CONFIG_NET
+if [ "$CONFIG_PCI" != "y" ]; then
+ define_bool CONFIG_PCI n
+fi
+
source drivers/pci/Config.in
+if [ "$CONFIG_ISA" != "y" ]; then
+ define_bool CONFIG_ISA n
+ define_bool CONFIG_EISA n
+else
+ define_bool CONFIG_EISA y
+fi
+
+define_bool CONFIG_MCA n
+define_bool CONFIG_SBUS n
+
bool 'Support for hot-pluggable devices' CONFIG_HOTPLUG
if [ "$CONFIG_HOTPLUG" = "y" ] ; then
@@ -177,36 +180,20 @@
bool 'System V IPC' CONFIG_SYSVIPC
bool 'BSD Process Accounting' CONFIG_BSD_PROCESS_ACCT
bool 'Sysctl support' CONFIG_SYSCTL
-
-if [ "$CONFIG_ARC32" = "y" ]; then
- bool 'ARC console support' CONFIG_ARC_CONSOLE
-fi
-
+define_bool CONFIG_KCORE_ELF y
+define_bool CONFIG_KCORE_AOUT n
tristate 'Kernel support for 64-bit ELF binaries' CONFIG_BINFMT_ELF
bool 'Kernel support for Linux/MIPS 32-bit binary compatibility' CONFIG_MIPS32_COMPAT
-if [ "$CONFIG_MIPS32_COMPAT" = "y" ]; then
- define_bool CONFIG_BINFMT_ELF32 y
-fi
+define_bool CONFIG_BINFMT_ELF32 $CONFIG_MIPS32_COMPAT
tristate 'Kernel support for MISC binaries' CONFIG_BINFMT_MISC
-
-endmenu
-
-mainmenu_option next_comment
-comment 'Loadable module support'
-bool 'Enable loadable module support' CONFIG_MODULES
-if [ "$CONFIG_MODULES" = "y" ]; then
- bool 'Set version information on all symbols for modules' CONFIG_MODVERSIONS
- bool 'Kernel module loader' CONFIG_KMOD
-fi
-
-source drivers/pci/Config.in
-
endmenu
source drivers/mtd/Config.in
source drivers/parport/Config.in
+source drivers/pnp/Config.in
+
source drivers/block/Config.in
source drivers/md/Config.in
@@ -217,18 +204,21 @@
source drivers/telephony/Config.in
-mainmenu_option next_comment
-comment 'ATA/IDE/MFM/RLL support'
+if [ "$CONFIG_ISA" = "y" -o "$CONFIG_PCI" = "y" ]; then
-tristate 'ATA/IDE/MFM/RLL support' CONFIG_IDE
+ mainmenu_option next_comment
+ comment 'ATA/IDE/MFM/RLL support'
-if [ "$CONFIG_IDE" != "n" ]; then
- source drivers/ide/Config.in
-else
- define_bool CONFIG_BLK_DEV_IDE_MODES n
- define_bool CONFIG_BLK_DEV_HD n
+ tristate 'ATA/IDE/MFM/RLL support' CONFIG_IDE
+
+ if [ "$CONFIG_IDE" != "n" ]; then
+ source drivers/ide/Config.in
+ else
+ define_bool CONFIG_BLK_DEV_IDE_MODES n
+ define_bool CONFIG_BLK_DEV_HD n
+ fi
+ endmenu
fi
-endmenu
mainmenu_option next_comment
comment 'SCSI support'
@@ -240,7 +230,9 @@
fi
endmenu
-#source drivers/message/i2o/Config.in
+if [ "$CONFIG_PCI" = "y" ]; then
+ source drivers/message/i2o/Config.in
+fi
if [ "$CONFIG_NET" = "y" ]; then
mainmenu_option next_comment
@@ -260,25 +252,27 @@
source net/irda/Config.in
-mainmenu_option next_comment
-comment 'ISDN subsystem'
-
if [ "$CONFIG_NET" != "n" ]; then
+ mainmenu_option next_comment
+ comment 'ISDN subsystem'
+
tristate 'ISDN support' CONFIG_ISDN
if [ "$CONFIG_ISDN" != "n" ]; then
source drivers/isdn/Config.in
fi
+ endmenu
fi
-endmenu
-mainmenu_option next_comment
-comment 'Old CD-ROM drivers (not SCSI, not IDE)'
+if [ "$CONFIG_ISA" = "y" ]; then
+ mainmenu_option next_comment
+ comment 'Old CD-ROM drivers (not SCSI, not IDE)'
-bool 'Support non-SCSI/IDE/ATAPI CDROM drives' CONFIG_CD_NO_IDESCSI
-if [ "$CONFIG_CD_NO_IDESCSI" != "n" ]; then
- source drivers/cdrom/Config.in
+ bool 'Support non-SCSI/IDE/ATAPI CDROM drives' CONFIG_CD_NO_IDESCSI
+ if [ "$CONFIG_CD_NO_IDESCSI" != "n" ]; then
+ source drivers/cdrom/Config.in
+ fi
+ endmenu
fi
-endmenu
source drivers/char/Config.in
@@ -301,10 +295,6 @@
fi
fi
endmenu
-fi
-
-if [ "$CONFIG_PROC_FS" = "y" ]; then
- define_bool CONFIG_KCORE_ELF y
fi
mainmenu_option next_comment
Index: defconfig
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/defconfig,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- defconfig 26 Feb 2002 19:03:28 -0000 1.15
+++ defconfig 30 May 2002 20:42:08 -0000 1.16
@@ -10,10 +10,16 @@
# CONFIG_EXPERIMENTAL is not set
#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
# Machine selection
#
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MALTA is not set
CONFIG_SGI_IP27=y
-# CONFIG_SIBYTE_SB1250 is not set
# CONFIG_SGI_SN0_N_MODE is not set
CONFIG_DISCONTIGMEM=y
CONFIG_NUMA=y
@@ -21,6 +27,9 @@
# CONFIG_REPLICATE_KTEXT is not set
# CONFIG_REPLICATE_EXHANDLERS is not set
CONFIG_SMP=y
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_SB1250 is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
CONFIG_BOOT_ELF64=y
@@ -29,10 +38,6 @@
CONFIG_PCI=y
CONFIG_QL_ISP_A64=y
CONFIG_L1_CACHE_SHIFT=7
-# CONFIG_ISA is not set
-# CONFIG_EISA is not set
-# CONFIG_MCA is not set
-# CONFIG_SBUS is not set
#
# CPU selection
@@ -54,24 +59,24 @@
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_NET=y
CONFIG_PCI_NAMES=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
# CONFIG_HOTPLUG is not set
# CONFIG_PCMCIA is not set
# CONFIG_HOTPLUG_PCI is not set
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
+CONFIG_KCORE_ELF=y
+# CONFIG_KCORE_AOUT is not set
CONFIG_BINFMT_ELF=y
CONFIG_MIPS32_COMPAT=y
CONFIG_BINFMT_ELF32=y
# CONFIG_BINFMT_MISC is not set
#
-# Loadable module support
-#
-# CONFIG_MODULES is not set
-CONFIG_PCI_NAMES=y
-
-#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
@@ -82,6 +87,12 @@
# CONFIG_PARPORT is not set
#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
@@ -227,6 +238,16 @@
# CONFIG_SCSI_U14_34F is not set
#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
# Network device support
#
CONFIG_NETDEVICES=y
@@ -306,11 +327,6 @@
# CONFIG_ISDN is not set
#
-# Old CD-ROM drivers (not SCSI, not IDE)
-#
-# CONFIG_CD_NO_IDESCSI is not set
-
-#
# Character devices
#
# CONFIG_VT is not set
@@ -465,7 +481,6 @@
# CONFIG_SUN_PARTITION is not set
# CONFIG_SMB_NLS is not set
# CONFIG_NLS is not set
-CONFIG_KCORE_ELF=y
#
# Sound
|
|
From: James S. <jsi...@us...> - 2002-05-30 20:42:44
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv29100/arch/mips/configs Modified Files: defconfig-sb1250-swarm Log Message: Updated Mips 64 to OSS tree. Index: defconfig-sb1250-swarm =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-sb1250-swarm,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- defconfig-sb1250-swarm 28 May 2002 20:25:35 -0000 1.8 +++ defconfig-sb1250-swarm 30 May 2002 20:42:08 -0000 1.9 @@ -10,19 +10,38 @@ CONFIG_EXPERIMENTAL=y # +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +CONFIG_KMOD=y + +# # Machine selection # # CONFIG_ACER_PICA_61 is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1500 is not set # CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set # CONFIG_MIPS_COBALT is not set # CONFIG_DECSTATION is not set -# CONFIG_DDB5074 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set # CONFIG_MIPS_MALTA is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_OLIVETTI_M700 is not set # CONFIG_NINO is not set +# CONFIG_SGI_IP22 is not set CONFIG_SIBYTE_SB1250=y # CONFIG_PCI is not set # CONFIG_SIBYTE_SB1250_PROF is not set @@ -33,38 +52,16 @@ # CONFIG_L3DEMO is not set CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS=16 CONFIG_SMP=y -# CONFIG_MIPS_MAGNUM_4000 is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_DDB5476 is not set -# CONFIG_DDB5477 is not set -# CONFIG_NEC_OSPREY is not set -# CONFIG_OLIVETTI_M700 is not set -# CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1500 is not set # CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_HP_LASERJET is not set # CONFIG_HIGHMEM is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set CONFIG_NEW_IRQ=y CONFIG_NEW_TIME_C=y CONFIG_DUMMY_KEYB=y CONFIG_SWAP_IO_SPACE=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y +# CONFIG_MIPS_AU1000 is not set # # CPU selection @@ -98,20 +95,27 @@ # General setup # # CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_KCORE_ELF=y -CONFIG_ELF_KERNEL=y # CONFIG_BINFMT_IRIX is not set # CONFIG_FORWARD_KEYBOARD is not set -# CONFIG_BINFMT_AOUT is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set CONFIG_NET=y +# CONFIG_PCI is not set +# CONFIG_ISA is not set +# CONFIG_EISA is not set +# CONFIG_TC is not set +# CONFIG_MCA is not set +# CONFIG_SBUS is not set # CONFIG_HOTPLUG is not set # CONFIG_PCMCIA is not set # CONFIG_HOTPLUG_PCI is not set CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_SYSCTL is not set +CONFIG_KCORE_ELF=y +# CONFIG_KCORE_AOUT is not set +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_PM is not set # # Memory Technology Devices (MTD) @@ -124,6 +128,12 @@ # CONFIG_PARPORT is not set # +# Plug and Play configuration +# +# CONFIG_PNP is not set +# CONFIG_ISAPNP is not set + +# # Block devices # # CONFIG_BLK_DEV_FD is not set @@ -200,67 +210,11 @@ # CONFIG_PHONE_IXJ_PCMCIA is not set # -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set -# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set -# CONFIG_BLK_DEV_IDEDISK_IBM is not set -# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set -# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set -# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set -# CONFIG_BLK_DEV_IDEDISK_WD is not set -# CONFIG_BLK_DEV_COMMERIAL is not set -# CONFIG_BLK_DEV_TIVO is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -CONFIG_BLK_DEV_IDE_SWARM=y -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_DMA_NONPCI is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# # SCSI support # # CONFIG_SCSI is not set # -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_LAN is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# # Network device support # CONFIG_NETDEVICES=y @@ -340,11 +294,6 @@ # ISDN subsystem # # CONFIG_ISDN is not set - -# -# Old CD-ROM drivers (not SCSI, not IDE) -# -# CONFIG_CD_NO_IDESCSI is not set # # Character devices |
|
From: James S. <jsi...@us...> - 2002-05-30 20:42:43
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv29100/arch/mips
Modified Files:
config.in
Log Message:
Updated Mips 64 to OSS tree.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.100
retrieving revision 1.101
diff -u -d -r1.100 -r1.101
--- config.in 29 May 2002 00:23:16 -0000 1.100
+++ config.in 30 May 2002 20:42:08 -0000 1.101
@@ -5,7 +5,7 @@
define_bool CONFIG_MIPS y
define_bool CONFIG_MIPS32 y
-mainmenu_name "Linux Kernel Configuration"
+mainmenu_name "Linux/MIPS Kernel Configuration"
mainmenu_option next_comment
comment 'Code maturity level options'
@@ -13,138 +13,209 @@
endmenu
[...1042 lines suppressed...]
-if [ "$CONFIG_DECSTATION" != "y" ]; then
- mainmenu_option next_comment
- comment 'Sound'
+mainmenu_option next_comment
+comment 'Sound'
- tristate 'Sound card support' CONFIG_SOUND
- if [ "$CONFIG_SOUND" != "n" ]; then
- source drivers/sound/Config.in
- fi
- endmenu
+tristate 'Sound card support' CONFIG_SOUND
+if [ "$CONFIG_SOUND" != "n" ]; then
+ source drivers/sound/Config.in
fi
+endmenu
if [ "$CONFIG_SGI_IP22" = "y" ]; then
source drivers/sgi/Config.in
|
|
From: James S. <jsi...@us...> - 2002-05-30 20:42:43
|
Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm
In directory usw-pr-cvs1:/tmp/cvs-serv29100/arch/mips/sibyte/swarm
Modified Files:
cfe_api.c cfe_api.h setup.c smp.c
Log Message:
Updated Mips 64 to OSS tree.
Index: cfe_api.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/cfe_api.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- cfe_api.c 19 Feb 2002 17:32:53 -0000 1.3
+++ cfe_api.c 30 May 2002 20:42:08 -0000 1.4
@@ -55,11 +55,10 @@
return 0;
}
+int cfe_iocb_dispatch(cfe_xiocb_t *xiocb);
int cfe_iocb_dispatch(cfe_xiocb_t *xiocb)
{
- if (!cfe_dispfunc)
- return -1;
-
+ if (!cfe_dispfunc) return -1;
return (*cfe_dispfunc)(cfe_handle,xiocb);
}
@@ -344,7 +343,7 @@
int cfe_start_cpu(int cpu, void (*fn)(void), long sp, long gp, long a1)
{
cfe_xiocb_t xiocb;
-
+
xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
xiocb.xiocb_status = 0;
xiocb.xiocb_handle = 0;
@@ -356,13 +355,30 @@
xiocb.plist.xiocb_cpuctl.sp_val = sp;
xiocb.plist.xiocb_cpuctl.a1_val = a1;
xiocb.plist.xiocb_cpuctl.start_addr = (long)fn;
-
+
cfe_iocb_dispatch(&xiocb);
-
+
return xiocb.xiocb_status;
}
+int cfe_stop_cpu(int cpu)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t);
+ xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
+ xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_STOP;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+
void cfe_open_console()
{
cfe_console_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
@@ -374,7 +390,6 @@
int res;
if (cfe_console_handle != -1) {
- cfe_write(cfe_console_handle, str, strlen(str));
do {
res = cfe_writeblk(cfe_console_handle, 0, str, len);
if (res < 0)
@@ -384,3 +399,4 @@
} while (len);
}
}
+
Index: cfe_api.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/cfe_api.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- cfe_api.h 28 Jan 2002 20:31:57 -0000 1.2
+++ cfe_api.h 30 May 2002 20:42:08 -0000 1.3
@@ -54,6 +54,7 @@
int cfe_flushcache(int flg);
int cfe_getstdhandle(int flg);
int cfe_start_cpu(int cpu, void (*fn)(void), long sp, long gp, long a1);
+int cfe_stop_cpu(int cpu);
void cfe_open_console(void);
void cfe_console_print(char *);
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/setup.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- setup.c 21 Apr 2002 20:01:13 -0000 1.11
+++ setup.c 30 May 2002 20:42:08 -0000 1.12
@@ -19,7 +19,7 @@
/*
* Setup code for the SWARM board
*/
-
+#include <linux/config.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/smp.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- smp.c 26 Feb 2002 17:34:15 -0000 1.7
+++ smp.c 30 May 2002 20:42:08 -0000 1.8
@@ -15,8 +15,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
-
-#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
@@ -38,13 +36,14 @@
int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp)
{
int retval;
-
- if ((retval = cfe_start_cpu(1, &smp_bootstrap, sp, gp, 0)) != 0) {
- printk("cfe_start_cpu returned %i\n" , retval);
- panic("secondary bootstrap failed");
+
+ retval = cfe_start_cpu(cpu, &smp_bootstrap, sp, gp, 0);
+ if (retval != 0) {
+ printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
+ return 0;
+ } else {
+ return 1;
}
-
- return 1;
}
@@ -66,23 +65,35 @@
*/
int prom_setup_smp(void)
{
- /* Nothing to do here */
- return 2;
+ int i;
+ int num_cpus = 1;
+
+ /* Use CFE to find out how many CPUs are available */
+ for (i=1; i<NR_CPUS; i++) {
+ if (cfe_stop_cpu(i) == 0) {
+ num_cpus++;
+ }
+ }
+ printk("Detected %i available CPU(s)\n", num_cpus);
+ return num_cpus;
}
void prom_smp_finish(void)
{
+ extern void sb1250_smp_finish(void);
sb1250_smp_finish();
}
/*
* XXX This is really halfway portable code and halfway system specific code.
+ * XXX Seems like some of this is CPU-specific, too - rather than board/system.
*/
extern atomic_t cpus_booted;
void __init smp_boot_cpus(void)
{
int i;
+ int cur_cpu = 0;
smp_num_cpus = prom_setup_smp();
init_new_context(current, &init_mm);
@@ -92,10 +103,18 @@
CPUMASK_CLRALL(cpu_online_map);
CPUMASK_SETB(cpu_online_map, 0);
atomic_set(&cpus_booted, 1); /* Master CPU is already booted... */
+ __cpu_number_map[0] = 0;
+ __cpu_logical_map[0] = 0;
init_idle();
- for (i = 1; i < smp_num_cpus; i++) {
+
+ /*
+ * This loop attempts to compensate for "holes" in the CPU
+ * numbering. It's overkill, but general.
+ */
+ for (i = 1; i < smp_num_cpus; ) {
struct task_struct *p;
struct pt_regs regs;
+ int retval;
printk("Starting CPU %d... ", i);
/* Spawn a new process normally. Grab a pointer to
@@ -115,9 +134,20 @@
del_from_runqueue(p);
unhash_process(p);
- prom_boot_secondary(i,
- (unsigned long)p + KERNEL_STACK_SIZE - 32,
- (unsigned long)p);
+ do {
+ /* Iterate until we find a CPU that comes up */
+ cur_cpu++;
+ retval = prom_boot_secondary(cur_cpu,
+ (unsigned long)p + KERNEL_STACK_SIZE - 32,
+ (unsigned long)p);
+ __cpu_number_map[i] = i;
+ __cpu_logical_map[i] = i;
+ } while (!retval && (cur_cpu < NR_CPUS));
+ if (retval) {
+ i++;
+ } else {
+ panic("CPU discovery disaster");
+ }
#if 0
/* This is copied from the ip-27 code in the mips64 tree */
|
|
From: James S. <jsi...@us...> - 2002-05-30 20:42:19
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64/mips-boards In directory usw-pr-cvs1:/tmp/cvs-serv29100/include/asm-mips64/mips-boards Added Files: bonito64.h generic.h malta.h msc01_pci.h Log Message: Updated Mips 64 to OSS tree. --- NEW FILE: bonito64.h --- /* * bonito.h * * Carsten Langgaard, car...@mi... * Copyright (C) 2001 MIPS Technologies, Inc. All rights reserved. * * ######################################################################## * * This file is the original bonito.h from Algorithmics with minor changes * to fit into linux. */ /* * Bonito Register Map * Copyright (c) 1999 Algorithmics Ltd * * Algorithmics gives permission for anyone to use and modify this file * without any obligation or license condition except that you retain * this copyright message in any source redistribution in whole or part. * * Updated copies of this and other files can be found at * ftp://ftp.algor.co.uk/pub/bonito/ * * Users of the Bonito controller are warmly recommended to contribute * any useful changes back to Algorithmics (mail to bo...@al...). */ /* Revision 1.48 autogenerated on 08/17/99 15:20:01 */ /* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */ #ifndef _ASM_MIPS_BOARDS_BONITO64_H #define _ASM_MIPS_BOARDS_BONITO64_H #ifdef __ASSEMBLER__ /* offsets from base register */ #define BONITO(x) (x) #else /* !__ASSEMBLER */ /* offsets from base pointer, this construct allows optimisation */ /* static char * const _bonito = PA_TO_KVA1(BONITO_BASE); */ #define BONITO(x) *(volatile u32 *)(_bonito + (x)) #endif /* __ASSEMBLER__ */ #define BONITO_BOOT_BASE 0x1fc00000 #define BONITO_BOOT_SIZE 0x00100000 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) #define BONITO_FLASH_BASE 0x1c000000 #define BONITO_FLASH_SIZE 0x03000000 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) #define BONITO_SOCKET_BASE 0x1f800000 #define BONITO_SOCKET_SIZE 0x00400000 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) #define BONITO_REG_BASE 0x1fe00000 #define BONITO_REG_SIZE 0x00040000 #define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) #define BONITO_DEV_BASE 0x1ff00000 #define BONITO_DEV_SIZE 0x00100000 #define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) #define BONITO_PCILO_BASE 0x10000000 #define BONITO_PCILO_SIZE 0x0c000000 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) #define BONITO_PCILO0_BASE 0x10000000 #define BONITO_PCILO1_BASE 0x14000000 #define BONITO_PCILO2_BASE 0x18000000 #define BONITO_PCIHI_BASE 0x20000000 #define BONITO_PCIHI_SIZE 0x20000000 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) #define BONITO_PCIIO_BASE 0x1fd00000 #define BONITO_PCIIO_SIZE 0x00100000 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) #define BONITO_PCICFG_BASE 0x1fe80000 #define BONITO_PCICFG_SIZE 0x00080000 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) /* Bonito Register Bases */ #define BONITO_PCICONFIGBASE 0x00 #define BONITO_REGBASE 0x100 /* PCI Configuration Registers */ #define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x)) #define BONITO_PCIDID BONITO_PCI_REG(0x00) #define BONITO_PCICMD BONITO_PCI_REG(0x04) #define BONITO_PCICLASS BONITO_PCI_REG(0x08) #define BONITO_PCILTIMER BONITO_PCI_REG(0x0c) #define BONITO_PCIBASE0 BONITO_PCI_REG(0x10) #define BONITO_PCIBASE1 BONITO_PCI_REG(0x14) #define BONITO_PCIBASE2 BONITO_PCI_REG(0x18) #define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30) #define BONITO_PCIINT BONITO_PCI_REG(0x3c) #define BONITO_PCICMD_PERR_CLR 0x80000000 #define BONITO_PCICMD_SERR_CLR 0x40000000 #define BONITO_PCICMD_MABORT_CLR 0x20000000 #define BONITO_PCICMD_MTABORT_CLR 0x10000000 #define BONITO_PCICMD_TABORT_CLR 0x08000000 #define BONITO_PCICMD_MPERR_CLR 0x01000000 #define BONITO_PCICMD_PERRRESPEN 0x00000040 #define BONITO_PCICMD_ASTEPEN 0x00000080 #define BONITO_PCICMD_SERREN 0x00000100 #define BONITO_PCILTIMER_BUSLATENCY 0x0000ff00 #define BONITO_PCILTIMER_BUSLATENCY_SHIFT 8 /* 1. Bonito h/w Configuration */ /* Power on register */ #define BONITO_BONPONCFG BONITO(BONITO_REGBASE + 0x00) #define BONITO_BONPONCFG_SYSCONTROLLERRD 0x00040000 #define BONITO_BONPONCFG_ROMCS1SAMP 0x00020000 #define BONITO_BONPONCFG_ROMCS0SAMP 0x00010000 #define BONITO_BONPONCFG_CPUBIGEND 0x00004000 /* Added by RPF 11-9-00 */ #define BONITO_BONPONCFG_BURSTORDER 0x00001000 /* --- */ #define BONITO_BONPONCFG_CPUPARITY 0x00002000 #define BONITO_BONPONCFG_CPUTYPE 0x00000007 #define BONITO_BONPONCFG_CPUTYPE_SHIFT 0 #define BONITO_BONPONCFG_PCIRESET_OUT 0x00000008 #define BONITO_BONPONCFG_IS_ARBITER 0x00000010 #define BONITO_BONPONCFG_ROMBOOT 0x000000c0 #define BONITO_BONPONCFG_ROMBOOT_SHIFT 6 #define BONITO_BONPONCFG_ROMBOOT_FLASH (0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT) #define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT) #define BONITO_BONPONCFG_ROMBOOT_SDRAM (0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT) #define BONITO_BONPONCFG_ROMBOOT_CPURESET (0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT) #define BONITO_BONPONCFG_ROMCS0WIDTH 0x00000100 #define BONITO_BONPONCFG_ROMCS1WIDTH 0x00000200 #define BONITO_BONPONCFG_ROMCS0FAST 0x00000400 #define BONITO_BONPONCFG_ROMCS1FAST 0x00000800 #define BONITO_BONPONCFG_CONFIG_DIS 0x00000020 /* Other Bonito configuration */ #define BONITO_BONGENCFG_OFFSET 0x4 #define BONITO_BONGENCFG BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET) #define BONITO_BONGENCFG_DEBUGMODE 0x00000001 #define BONITO_BONGENCFG_SNOOPEN 0x00000002 #define BONITO_BONGENCFG_CPUSELFRESET 0x00000004 #define BONITO_BONGENCFG_FORCE_IRQA 0x00000008 #define BONITO_BONGENCFG_IRQA_ISOUT 0x00000010 #define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020 #define BONITO_BONGENCFG_BYTESWAP 0x00000040 #define BONITO_BONGENCFG_UNCACHED 0x00000080 #define BONITO_BONGENCFG_PREFETCHEN 0x00000100 #define BONITO_BONGENCFG_WBEHINDEN 0x00000200 #define BONITO_BONGENCFG_CACHEALG 0x00000c00 #define BONITO_BONGENCFG_CACHEALG_SHIFT 10 #define BONITO_BONGENCFG_PCIQUEUE 0x00001000 #define BONITO_BONGENCFG_CACHESTOP 0x00002000 #define BONITO_BONGENCFG_MSTRBYTESWAP 0x00004000 #define BONITO_BONGENCFG_BUSERREN 0x00008000 #define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000 #define BONITO_BONGENCFG_SHORTCOPYTIMEOUT 0x00020000 /* 2. IO & IDE configuration */ #define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08) /* 3. IO & IDE configuration */ #define BONITO_SDCFG BONITO(BONITO_REGBASE + 0x0c) /* 4. PCI address map control */ #define BONITO_PCIMAP BONITO(BONITO_REGBASE + 0x10) #define BONITO_PCIMEMBASECFG BONITO(BONITO_REGBASE + 0x14) #define BONITO_PCIMAP_CFG BONITO(BONITO_REGBASE + 0x18) /* 5. ICU & GPIO regs */ /* GPIO Regs - r/w */ #define BONITO_GPIODATA_OFFSET 0x1c #define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET) #define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20) /* ICU Configuration Regs - r/w */ #define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24) #define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28) #define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c) /* ICU Enable Regs - IntEn & IntISR are r/o. */ #define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30) #define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34) #define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38) #define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c) /* PCI mail boxes */ #define BONITO_PCIMAIL0_OFFSET 0x40 #define BONITO_PCIMAIL1_OFFSET 0x44 #define BONITO_PCIMAIL2_OFFSET 0x48 #define BONITO_PCIMAIL3_OFFSET 0x4c #define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40) #define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44) #define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48) #define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c) /* 6. PCI cache */ #define BONITO_PCICACHECTRL BONITO(BONITO_REGBASE + 0x50) #define BONITO_PCICACHETAG BONITO(BONITO_REGBASE + 0x54) #define BONITO_PCIBADADDR BONITO(BONITO_REGBASE + 0x58) #define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c) /* #define BONITO_PCIRDPOST BONITO(BONITO_REGBASE + 0x60) #define BONITO_PCIDATA BONITO(BONITO_REGBASE + 0x64) */ /* 7. IDE DMA & Copier */ #define BONITO_CONFIGBASE 0x000 #define BONITO_BONITOBASE 0x100 #define BONITO_LDMABASE 0x200 #define BONITO_COPBASE 0x300 #define BONITO_REG_BLOCKMASK 0x300 #define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0) #define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0) #define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4) #define BONITO_LDMAGO BONITO(BONITO_LDMABASE + 0x8) #define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc) #define BONITO_COPCTRL BONITO(BONITO_COPBASE + 0x0) #define BONITO_COPSTAT BONITO(BONITO_COPBASE + 0x0) #define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4) #define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8) #define BONITO_COPGO BONITO(BONITO_COPBASE + 0xc) /* ###### Bit Definitions for individual Registers #### */ /* Gen DMA. */ #define BONITO_IDECOPDADDR_DMA_DADDR 0x0ffffffc #define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT 2 #define BONITO_IDECOPPADDR_DMA_PADDR 0xfffffffc #define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT 2 #define BONITO_IDECOPGO_DMA_SIZE 0x0000fffe #define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0 #define BONITO_IDECOPGO_DMA_WRITE 0x00010000 #define BONITO_IDECOPGO_DMAWCOUNT 0x000f0000 #define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16 #define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000 #define BONITO_IDECOPCTRL_DMA_RSTBIT 0x40000000 /* DRAM - sdCfg */ #define BONITO_SDCFG_AROWBITS 0x00000003 #define BONITO_SDCFG_AROWBITS_SHIFT 0 #define BONITO_SDCFG_ACOLBITS 0x0000000c #define BONITO_SDCFG_ACOLBITS_SHIFT 2 #define BONITO_SDCFG_ABANKBIT 0x00000010 #define BONITO_SDCFG_ASIDES 0x00000020 #define BONITO_SDCFG_AABSENT 0x00000040 #define BONITO_SDCFG_AWIDTH64 0x00000080 #define BONITO_SDCFG_BROWBITS 0x00000300 #define BONITO_SDCFG_BROWBITS_SHIFT 8 #define BONITO_SDCFG_BCOLBITS 0x00000c00 #define BONITO_SDCFG_BCOLBITS_SHIFT 10 #define BONITO_SDCFG_BBANKBIT 0x00001000 #define BONITO_SDCFG_BSIDES 0x00002000 #define BONITO_SDCFG_BABSENT 0x00004000 #define BONITO_SDCFG_BWIDTH64 0x00008000 #define BONITO_SDCFG_EXTRDDATA 0x00010000 #define BONITO_SDCFG_EXTRASCAS 0x00020000 #define BONITO_SDCFG_EXTPRECH 0x00040000 #define BONITO_SDCFG_EXTRASWIDTH 0x00180000 #define BONITO_SDCFG_EXTRASWIDTH_SHIFT 19 /* Changed by RPF 11-9-00 */ #define BONITO_SDCFG_DRAMMODESET 0x00200000 /* --- */ #define BONITO_SDCFG_DRAMEXTREGS 0x00400000 #define BONITO_SDCFG_DRAMPARITY 0x00800000 /* Added by RPF 11-9-00 */ #define BONITO_SDCFG_DRAMBURSTLEN 0x03000000 #define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24 #define BONITO_SDCFG_DRAMMODESET_DONE 0x80000000 /* --- */ /* PCI Cache - pciCacheCtrl */ #define BONITO_PCICACHECTRL_CACHECMD 0x00000007 #define BONITO_PCICACHECTRL_CACHECMD_SHIFT 0 #define BONITO_PCICACHECTRL_CACHECMDLINE 0x00000018 #define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT 3 #define BONITO_PCICACHECTRL_CMDEXEC 0x00000020 #define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001 #define BONITO_IODEVCFG_SPEEDBIT_CS0 0x00000002 #define BONITO_IODEVCFG_MOREABITS_CS0 0x00000004 #define BONITO_IODEVCFG_BUFFBIT_CS1 0x00000008 #define BONITO_IODEVCFG_SPEEDBIT_CS1 0x00000010 #define BONITO_IODEVCFG_MOREABITS_CS1 0x00000020 #define BONITO_IODEVCFG_BUFFBIT_CS2 0x00000040 #define BONITO_IODEVCFG_SPEEDBIT_CS2 0x00000080 #define BONITO_IODEVCFG_MOREABITS_CS2 0x00000100 #define BONITO_IODEVCFG_BUFFBIT_CS3 0x00000200 #define BONITO_IODEVCFG_SPEEDBIT_CS3 0x00000400 #define BONITO_IODEVCFG_MOREABITS_CS3 0x00000800 #define BONITO_IODEVCFG_BUFFBIT_IDE 0x00001000 #define BONITO_IODEVCFG_SPEEDBIT_IDE 0x00002000 #define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000 #define BONITO_IODEVCFG_MODEBIT_IDE 0x00008000 #define BONITO_IODEVCFG_DMAON_IDE 0x001f0000 #define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16 #define BONITO_IODEVCFG_DMAOFF_IDE 0x01e00000 #define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT 21 #define BONITO_IODEVCFG_EPROMSPLIT 0x02000000 /* Added by RPF 11-9-00 */ #define BONITO_IODEVCFG_CPUCLOCKPERIOD 0xfc000000 #define BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT 26 /* --- */ /* gpio */ #define BONITO_GPIO_GPIOW 0x000003ff #define BONITO_GPIO_GPIOW_SHIFT 0 #define BONITO_GPIO_GPIOR 0x01ff0000 #define BONITO_GPIO_GPIOR_SHIFT 16 #define BONITO_GPIO_GPINR 0xfe000000 #define BONITO_GPIO_GPINR_SHIFT 25 #define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N))) #define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N))) #define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N))) /* ICU */ #define BONITO_ICU_MBOXES 0x0000000f #define BONITO_ICU_MBOXES_SHIFT 0 #define BONITO_ICU_DMARDY 0x00000010 #define BONITO_ICU_DMAEMPTY 0x00000020 #define BONITO_ICU_COPYRDY 0x00000040 #define BONITO_ICU_COPYEMPTY 0x00000080 #define BONITO_ICU_COPYERR 0x00000100 #define BONITO_ICU_PCIIRQ 0x00000200 #define BONITO_ICU_MASTERERR 0x00000400 #define BONITO_ICU_SYSTEMERR 0x00000800 #define BONITO_ICU_DRAMPERR 0x00001000 #define BONITO_ICU_RETRYERR 0x00002000 #define BONITO_ICU_GPIOS 0x01ff0000 #define BONITO_ICU_GPIOS_SHIFT 16 #define BONITO_ICU_GPINS 0x7e000000 #define BONITO_ICU_GPINS_SHIFT 25 #define BONITO_ICU_MBOX(N) (1<<(BONITO_ICU_MBOXES_SHIFT+(N))) #define BONITO_ICU_GPIO(N) (1<<(BONITO_ICU_GPIOS_SHIFT+(N))) #define BONITO_ICU_GPIN(N) (1<<(BONITO_ICU_GPINS_SHIFT+(N))) /* pcimap */ #define BONITO_PCIMAP_PCIMAP_LO0 0x0000003f #define BONITO_PCIMAP_PCIMAP_LO0_SHIFT 0 #define BONITO_PCIMAP_PCIMAP_LO1 0x00000fc0 #define BONITO_PCIMAP_PCIMAP_LO1_SHIFT 6 #define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000 #define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12 #define BONITO_PCIMAP_PCIMAP_2 0x00040000 #define BONITO_PCIMAP_WIN(WIN,ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) #define BONITO_PCIMAP_WINSIZE (1<<26) #define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) #define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26) /* pcimembaseCfg */ #define BONITO_PCIMEMBASECFG_MASK 0xf0000000 #define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f #define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0 #define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0 #define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT 5 #define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED 0x00000400 #define BONITO_PCIMEMBASECFG_MEMBASE0_IO 0x00000800 #define BONITO_PCIMEMBASECFG_MEMBASE1_MASK 0x0001f000 #define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT 12 #define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS 0x003e0000 #define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT 17 #define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED 0x00400000 #define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000 #define BONITO_PCIMEMBASECFG_ASHIFT 23 #define BONITO_PCIMEMBASECFG_AMASK 0x007fffff #define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) #define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) #define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) #define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) #define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) #define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) #define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \ (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \ (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \ ) /* PCICmd */ #define BONITO_PCICMD_MEMEN 0x00000002 #define BONITO_PCICMD_MSTREN 0x00000004 #endif /* _ASM_MIPS_BOARDS_BONITO64_H */ --- NEW FILE: msc01_pci.h --- /* * mcs01_pci.h * * Carsten Langgaard, car...@mi... * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. * * ######################################################################## * * PCI Register definitions for the MIPS System Controller. */ #ifndef MSC01_PCI_H #define MSC01_PCI_H /***************************************************************************** * Register offset addresses ****************************************************************************/ #define MSC01_PCI_ID_OFS 0x0000 #define MSC01_PCI_SC2PMBASL_OFS 0x0208 #define MSC01_PCI_SC2PMMSKL_OFS 0x0218 #define MSC01_PCI_SC2PMMAPL_OFS 0x0228 #define MSC01_PCI_SC2PIOBASL_OFS 0x0248 #define MSC01_PCI_SC2PIOMSKL_OFS 0x0258 #define MSC01_PCI_SC2PIOMAPL_OFS 0x0268 #define MSC01_PCI_P2SCMSKL_OFS 0x0308 #define MSC01_PCI_P2SCMAPL_OFS 0x0318 #define MSC01_PCI_INTCFG_OFS 0x0600 #define MSC01_PCI_INTSTAT_OFS 0x0608 #define MSC01_PCI_CFGADDR_OFS 0x0610 #define MSC01_PCI_CFGDATA_OFS 0x0618 #define MSC01_PCI_IACK_OFS 0x0620 #define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */ #define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */ #define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */ #define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */ #define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */ #define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */ #define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */ #define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */ #define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */ #define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */ #define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */ #define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */ #define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */ #define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */ #define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */ #define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */ #define MSC01_PCI_BAR0_OFS 0x2220 #define MSC01_PCI_CFG_OFS 0x2380 #define MSC01_PCI_SWAP_OFS 0x2388 /***************************************************************************** * Register encodings ****************************************************************************/ #define MSC01_PCI_ID_ID_SHF 16 #define MSC01_PCI_ID_ID_MSK 0x00ff0000 #define MSC01_PCI_ID_ID_HOSTBRIDGE 82 #define MSC01_PCI_ID_MAR_SHF 8 #define MSC01_PCI_ID_MAR_MSK 0x0000ff00 #define MSC01_PCI_ID_MIR_SHF 0 #define MSC01_PCI_ID_MIR_MSK 0x000000ff #define MSC01_PCI_SC2PMBASL_BAS_SHF 24 #define MSC01_PCI_SC2PMBASL_BAS_MSK 0xff000000 #define MSC01_PCI_SC2PMMSKL_MSK_SHF 24 #define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000 #define MSC01_PCI_SC2PMMAPL_MAP_SHF 24 #define MSC01_PCI_SC2PMMAPL_MAP_MSK 0xff000000 #define MSC01_PCI_SC2PIOBASL_BAS_SHF 24 #define MSC01_PCI_SC2PIOBASL_BAS_MSK 0xff000000 #define MSC01_PCI_SC2PIOMSKL_MSK_SHF 24 #define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000 #define MSC01_PCI_SC2PIOMAPL_MAP_SHF 24 #define MSC01_PCI_SC2PIOMAPL_MAP_MSK 0xff000000 #define MSC01_PCI_P2SCMSKL_MSK_SHF 24 #define MSC01_PCI_P2SCMSKL_MSK_MSK 0xff000000 #define MSC01_PCI_P2SCMAPL_MAP_SHF 24 #define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000 #define MSC01_PCI_INTCFG_RST_SHF 10 #define MSC01_PCI_INTCFG_RST_MSK 0x00000400 #define MSC01_PCI_INTCFG_RST_BIT 0x00000400 #define MSC01_PCI_INTCFG_MWE_SHF 9 #define MSC01_PCI_INTCFG_MWE_MSK 0x00000200 #define MSC01_PCI_INTCFG_MWE_BIT 0x00000200 #define MSC01_PCI_INTCFG_DTO_SHF 8 #define MSC01_PCI_INTCFG_DTO_MSK 0x00000100 #define MSC01_PCI_INTCFG_DTO_BIT 0x00000100 #define MSC01_PCI_INTCFG_MA_SHF 7 #define MSC01_PCI_INTCFG_MA_MSK 0x00000080 #define MSC01_PCI_INTCFG_MA_BIT 0x00000080 #define MSC01_PCI_INTCFG_TA_SHF 6 #define MSC01_PCI_INTCFG_TA_MSK 0x00000040 #define MSC01_PCI_INTCFG_TA_BIT 0x00000040 #define MSC01_PCI_INTCFG_RTY_SHF 5 #define MSC01_PCI_INTCFG_RTY_MSK 0x00000020 #define MSC01_PCI_INTCFG_RTY_BIT 0x00000020 #define MSC01_PCI_INTCFG_MWP_SHF 4 #define MSC01_PCI_INTCFG_MWP_MSK 0x00000010 #define MSC01_PCI_INTCFG_MWP_BIT 0x00000010 #define MSC01_PCI_INTCFG_MRP_SHF 3 #define MSC01_PCI_INTCFG_MRP_MSK 0x00000008 #define MSC01_PCI_INTCFG_MRP_BIT 0x00000008 #define MSC01_PCI_INTCFG_SWP_SHF 2 #define MSC01_PCI_INTCFG_SWP_MSK 0x00000004 #define MSC01_PCI_INTCFG_SWP_BIT 0x00000004 #define MSC01_PCI_INTCFG_SRP_SHF 1 #define MSC01_PCI_INTCFG_SRP_MSK 0x00000002 #define MSC01_PCI_INTCFG_SRP_BIT 0x00000002 #define MSC01_PCI_INTCFG_SE_SHF 0 #define MSC01_PCI_INTCFG_SE_MSK 0x00000001 #define MSC01_PCI_INTCFG_SE_BIT 0x00000001 #define MSC01_PCI_INTSTAT_RST_SHF 10 #define MSC01_PCI_INTSTAT_RST_MSK 0x00000400 #define MSC01_PCI_INTSTAT_RST_BIT 0x00000400 #define MSC01_PCI_INTSTAT_MWE_SHF 9 #define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200 #define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200 #define MSC01_PCI_INTSTAT_DTO_SHF 8 #define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100 #define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100 #define MSC01_PCI_INTSTAT_MA_SHF 7 #define MSC01_PCI_INTSTAT_MA_MSK 0x00000080 #define MSC01_PCI_INTSTAT_MA_BIT 0x00000080 #define MSC01_PCI_INTSTAT_TA_SHF 6 #define MSC01_PCI_INTSTAT_TA_MSK 0x00000040 #define MSC01_PCI_INTSTAT_TA_BIT 0x00000040 #define MSC01_PCI_INTSTAT_RTY_SHF 5 #define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020 #define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020 #define MSC01_PCI_INTSTAT_MWP_SHF 4 #define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010 #define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010 #define MSC01_PCI_INTSTAT_MRP_SHF 3 #define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008 #define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008 #define MSC01_PCI_INTSTAT_SWP_SHF 2 #define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004 #define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004 #define MSC01_PCI_INTSTAT_SRP_SHF 1 #define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002 #define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002 #define MSC01_PCI_INTSTAT_SE_SHF 0 #define MSC01_PCI_INTSTAT_SE_MSK 0x00000001 #define MSC01_PCI_INTSTAT_SE_BIT 0x00000001 #define MSC01_PCI_CFGADDR_BNUM_SHF 16 #define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000 #define MSC01_PCI_CFGADDR_DNUM_SHF 11 #define MSC01_PCI_CFGADDR_DNUM_MSK 0x0000f800 #define MSC01_PCI_CFGADDR_FNUM_SHF 8 #define MSC01_PCI_CFGADDR_FNUM_MSK 0x00000700 #define MSC01_PCI_CFGADDR_RNUM_SHF 2 #define MSC01_PCI_CFGADDR_RNUM_MSK 0x000000fc #define MSC01_PCI_CFGDATA_DATA_SHF 0 #define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff /* The defines below are ONLY valid for a MEM bar! */ #define MSC01_PCI_BAR0_SIZE_SHF 4 #define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0 #define MSC01_PCI_BAR0_P_SHF 3 #define MSC01_PCI_BAR0_P_MSK 0x00000008 #define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK #define MSC01_PCI_BAR0_D_SHF 1 #define MSC01_PCI_BAR0_D_MSK 0x00000006 #define MSC01_PCI_BAR0_T_SHF 0 #define MSC01_PCI_BAR0_T_MSK 0x00000001 #define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK #define MSC01_PCI_CFG_RA_SHF 17 #define MSC01_PCI_CFG_RA_MSK 0x00020000 #define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK #define MSC01_PCI_CFG_G_SHF 16 #define MSC01_PCI_CFG_G_MSK 0x00010000 #define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK #define MSC01_PCI_CFG_EN_SHF 15 #define MSC01_PCI_CFG_EN_MSK 0x00008000 #define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK #define MSC01_PCI_CFG_MAXRTRY_SHF 0 #define MSC01_PCI_CFG_MAXRTRY_MSK 0x000000ff #define MSC01_PCI_SWAP_IO_SHF 18 #define MSC01_PCI_SWAP_IO_MSK 0x000c0000 #define MSC01_PCI_SWAP_MEM_SHF 16 #define MSC01_PCI_SWAP_MEM_MSK 0x00030000 #define MSC01_PCI_SWAP_BAR0_SHF 0 #define MSC01_PCI_SWAP_BAR0_MSK 0x00000003 #define MSC01_PCI_SWAP_NOSWAP 0 #define MSC01_PCI_SWAP_BYTESWAP 1 /***************************************************************************** * Registers absolute addresses ****************************************************************************/ #define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS) #define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS) #define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS) #define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS) #define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS) #define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS) #define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS) #define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS) #define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS) #define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS) #define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS) #define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS) #define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS) #define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS) #define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS) #define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS) #define MSC01_PCI_HEAD2 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS) #define MSC01_PCI_HEAD3 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS) #define MSC01_PCI_HEAD4 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS) #define MSC01_PCI_HEAD5 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS) #define MSC01_PCI_HEAD6 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS) #define MSC01_PCI_HEAD7 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS) #define MSC01_PCI_HEAD8 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS) #define MSC01_PCI_HEAD9 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS) #define MSC01_PCI_HEAD10 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS) #define MSC01_PCI_HEAD11 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) #define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) #define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) #define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) #define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) #define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS) #define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS) #define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS) #endif /***************************************************************************** * End of msc01_pci.h *****************************************************************************/ |
|
From: James S. <jsi...@us...> - 2002-05-30 20:42:18
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv29100/include/asm-mips64
Modified Files:
asm.h bootinfo.h branch.h cache.h cpu.h fpu_emulator.h
mipsregs.h mmu_context.h processor.h serial.h spinlock.h
Added Files:
elf.h irq_cpu.h
Log Message:
Updated Mips 64 to OSS tree.
--- NEW FILE: irq_cpu.h ---
/*
* include/asm-mips/irq_cpu.h
*
* MIPS CPU interrupt definitions.
*
* Copyright (C) 2002 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MIPS64_IRQ_CPU_H
#define __ASM_MIPS64_IRQ_CPU_H
extern void mips_cpu_irq_init(int irq_base);
#endif /* __ASM_MIPS64_IRQ_CPU_H */
Index: asm.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/asm.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- asm.h 21 Apr 2002 20:06:20 -0000 1.9
+++ asm.h 30 May 2002 20:42:15 -0000 1.10
@@ -174,12 +174,12 @@
9:
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
- (_MIPS_ISA == _MIPS_ISA_MIPS64)
+ (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
#define MOVN(rd,rs,rt) \
movn rd,rs,rt
#define MOVZ(rd,rs,rt) \
movz rd,rs,rt
-#endif /* MIPS IV, MIPS V or MIPS64 */
+#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
/*
* Stack alignment
Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/bootinfo.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- bootinfo.h 19 Feb 2002 17:17:53 -0000 1.10
+++ bootinfo.h 30 May 2002 20:42:15 -0000 1.11
@@ -156,6 +156,7 @@
* Valid machtype for group Alchemy
*/
#define MACH_PB1000 0 /* Au1000-based eval board */
+#define MACH_PB1500 1 /* Au1500-based eval board */
/*
* Valid machtype for group NEC_VR41XX
Index: branch.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/branch.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- branch.h 31 Oct 2001 18:26:52 -0000 1.1
+++ branch.h 30 May 2002 20:42:15 -0000 1.2
@@ -3,10 +3,11 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Branch and jump emulation.
- *
- * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
+ * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
*/
+#ifndef _ASM_BRANCH_H
+#define _ASM_BRANCH_H
+
#include <asm/ptrace.h>
static inline int delay_slot(struct pt_regs *regs)
@@ -14,6 +15,14 @@
return regs->cp0_cause & CAUSEF_BD;
}
+static inline unsigned long exception_epc(struct pt_regs *regs)
+{
+ if (!delay_slot(regs))
+ return regs->cp0_epc;
+
+ return regs->cp0_epc + 4;
+}
+
extern int __compute_return_epc(struct pt_regs *regs);
static inline int compute_return_epc(struct pt_regs *regs)
@@ -25,3 +34,5 @@
return __compute_return_epc(regs);
}
+
+#endif /* _ASM_BRANCH_H */
Index: cache.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/cache.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- cache.h 21 Nov 2001 22:10:59 -0000 1.3
+++ cache.h 30 May 2002 20:42:15 -0000 1.4
@@ -9,6 +9,8 @@
#ifndef _ASM_CACHE_H
#define _ASM_CACHE_H
+#include <linux/config.h>
+
#ifndef _LANGUAGE_ASSEMBLY
/*
* Descriptor for a cache
Index: cpu.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/cpu.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- cpu.h 4 Jan 2002 18:04:53 -0000 1.7
+++ cpu.h 30 May 2002 20:42:15 -0000 1.8
@@ -62,6 +62,7 @@
#define PRID_IMP_R5500 0x5500
#define PRID_IMP_4KC 0x8000
#define PRID_IMP_5KC 0x8100
+#define PRID_IMP_20KC 0x8200
#define PRID_IMP_4KEC 0x8400
#define PRID_IMP_4KSC 0x8600
@@ -126,7 +127,7 @@
CPU_R5000A, CPU_R4640, CPU_NEVADA, CPU_RM7000, CPU_R5432, CPU_4KC,
CPU_5KC, CPU_R4310, CPU_SB1, CPU_TX3912, CPU_TX3922, CPU_TX3927,
CPU_AU1000, CPU_4KEC, CPU_4KSC, CPU_VR41XX, CPU_R5500, CPU_TX49XX,
- CPU_TX39XX, CPU_LAST
+ CPU_TX39XX, CPU_AU1500, CPU_20KC, CPU_LAST
};
#endif
@@ -159,5 +160,6 @@
#define MIPS_CPU_CACHE_CDEX 0x00000800 /* Create_Dirty_Exclusive CACHE op */
#define MIPS_CPU_MCHECK 0x00001000 /* Machine check exception */
#define MIPS_CPU_EJTAG 0x00002000 /* EJTAG exception */
+#define MIPS_CPU_FPUEX 0x00004000 /* FPU exception */
#endif /* _ASM_CPU_H */
Index: fpu_emulator.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/fpu_emulator.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- fpu_emulator.h 18 Mar 2002 22:25:08 -0000 1.1
+++ fpu_emulator.h 30 May 2002 20:42:15 -0000 1.2
@@ -1,15 +1,4 @@
/*
- * Definitiona for the Algorithmics FPU Emulator port into MIPS Linux
- */
-/**************************************************************************
- *
- * include/asm-mips/fpu_emulator.h
- *
- * Kevin D. Kissell, ke...@mi... and Carsten Langgaard, car...@mi...
- * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
- *
- * ########################################################################
- *
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
@@ -23,13 +12,16 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
- *************************************************************************/
-/*
* Further private data for which no space exists in mips_fpu_soft_struct.
* This should be subsumed into the mips_fpu_soft_struct structure as
* defined in processor.h as soon as the absurd wired absolute assembler
* offsets become dynamic at compile time.
+ *
+ * Kevin D. Kissell, ke...@mi... and Carsten Langgaard, car...@mi...
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*/
+#ifndef _ASM_FPU_EMULATOR_H
+#define _ASM_FPU_EMULATOR_H
struct mips_fpu_emulator_private {
unsigned int eir;
@@ -42,3 +34,5 @@
unsigned int errors;
} stats;
};
+
+#endif /* _ASM_FPU_EMULATOR_H */
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mipsregs.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- mipsregs.h 26 Feb 2002 17:08:29 -0000 1.11
+++ mipsregs.h 30 May 2002 20:42:15 -0000 1.12
@@ -52,12 +52,15 @@
#define CP0_XCONTEXT $20
#define CP0_FRAMEMASK $21
#define CP0_DIAGNOSTIC $22
+#define CP0_DEBUG $23
+#define CP0_DEPC $24
#define CP0_PERFORMANCE $25
#define CP0_ECC $26
#define CP0_CACHEERR $27
#define CP0_TAGLO $28
#define CP0_TAGHI $29
#define CP0_ERROREPC $30
+#define CP0_DESAVE $31
/*
* R4640/R4650 cp0 register names. These registers are listed
Index: mmu_context.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mmu_context.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- mmu_context.h 28 Jan 2002 20:32:05 -0000 1.4
+++ mmu_context.h 30 May 2002 20:42:15 -0000 1.5
@@ -27,7 +27,7 @@
#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
pgd_current[smp_processor_id()] = (unsigned long)(pgd)
#define TLBMISS_HANDLER_SETUP() \
- set_context((unsigned long) smp_processor_id() << (23 + 3)); \
+ set_context(((long)(&pgd_current[smp_processor_id()])) << 23); \
TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
extern unsigned long pgd_current[];
Index: processor.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/processor.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- processor.h 26 Feb 2002 17:34:15 -0000 1.9
+++ processor.h 30 May 2002 20:42:15 -0000 1.10
@@ -15,35 +15,19 @@
/*
* Return current * instruction pointer ("program counter").
- *
- * Two implementations. The ``la'' version results in shorter code for
- * the kernel which we assume to reside in the 32-bit compat address space.
- * The ``jal'' version is for use by modules which live in outer space.
- * This is just a single instruction unlike the long dla macro expansion.
*/
-#ifdef MODULE
-#define current_text_addr() \
-({ \
- void *_a; \
- \
- __asm__ ("jal\t1f, %0\n\t" \
- "1:" \
- : "=r" (_a)); \
- \
- _a; \
-})
-#else
#define current_text_addr() \
({ \
void *_a; \
\
- __asm__ ("dla\t%0, 1f\n\t" \
- "1:" \
- : "=r" (_a)); \
+ __asm__ ("bal\t1f\t\t\t# current_text_addr\n" \
+ "1:\tmove\t%0, $31" \
+ : "=r" (_a) \
+ : \
+ : "$31"); \
\
_a; \
})
-#endif
#if !defined (_LANGUAGE_ASSEMBLY)
#include <asm/cachectl.h>
Index: serial.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/serial.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- serial.h 17 Dec 2001 18:35:15 -0000 1.1
+++ serial.h 30 May 2002 20:42:15 -0000 1.2
@@ -9,6 +9,8 @@
#ifndef _ASM_SERIAL_H
#define _ASM_SERIAL_H
+#include <linux/config.h>
+
/*
* This assumes you have a 1.8432 MHz clock for your UART.
*
Index: spinlock.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/spinlock.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- spinlock.h 14 Feb 2002 20:38:59 -0000 1.4
+++ spinlock.h 30 May 2002 20:42:15 -0000 1.5
@@ -22,7 +22,7 @@
#define spin_lock_init(x) do { (x)->lock = 0; } while(0)
#define spin_is_locked(x) ((x)->lock != 0)
-#define spin_unlock_wait(x) do { barrier(); } while ((x)->lock);
+#define spin_unlock_wait(x) do { barrier(); } while ((x)->lock)
/*
* Simple spin lock operations. There are two variants, one clears IRQ's
|
|
From: James S. <jsi...@us...> - 2002-05-30 20:42:18
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64/ip32 In directory usw-pr-cvs1:/tmp/cvs-serv29100/include/asm-mips64/ip32 Modified Files: machine.h Log Message: Updated Mips 64 to OSS tree. Index: machine.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/ip32/machine.h,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- machine.h 4 Sep 2001 22:41:02 -0000 1.1 +++ machine.h 30 May 2002 20:42:15 -0000 1.2 @@ -9,9 +9,13 @@ */ #ifndef _ASM_IP32_MACHINE_H #define _ASM_IP32_MACHINE_H + +#include <linux/config.h> + #ifdef CONFIG_SGI_IP32 #define SGI_MACH_O2 0x3201 #endif /* CONFIG_SGI_IP32 */ + #endif /* _ASM_SGI_MACHINE_H */ |
|
From: James S. <jsi...@us...> - 2002-05-30 20:42:18
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32 In directory usw-pr-cvs1:/tmp/cvs-serv29100/arch/mips64/sgi-ip32 Modified Files: ip32-pci.c ip32-setup.c ip32-timer.c Log Message: Updated Mips 64 to OSS tree. Index: ip32-pci.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-pci.c,v retrieving revision 1.5 retrieving revision 1.6 diff -u -d -r1.5 -r1.6 --- ip32-pci.c 2 Dec 2001 19:05:31 -0000 1.5 +++ ip32-pci.c 30 May 2002 20:42:15 -0000 1.6 @@ -5,7 +5,6 @@ * * Copyright (C) 2000, 2001 Keith M Wesolowski */ -#include <linux/config.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/pci.h> Index: ip32-setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-setup.c,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- ip32-setup.c 26 Feb 2002 17:34:15 -0000 1.7 +++ ip32-setup.c 30 May 2002 20:42:15 -0000 1.8 @@ -7,6 +7,7 @@ * * Copyright (C) 2000 Harald Koerfgen */ +#include <linux/config.h> #include <linux/sched.h> #include <linux/interrupt.h> #include <linux/mc146818rtc.h> Index: ip32-timer.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-timer.c,v retrieving revision 1.4 retrieving revision 1.5 diff -u -d -r1.4 -r1.5 --- ip32-timer.c 2 Jan 2002 19:12:18 -0000 1.4 +++ ip32-timer.c 30 May 2002 20:42:15 -0000 1.5 @@ -9,7 +9,6 @@ */ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/config.h> #include <linux/errno.h> #include <linux/sched.h> #include <linux/param.h> |
|
From: James S. <jsi...@us...> - 2002-05-30 20:42:17
|
Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv29100/arch/mips64/mm
Modified Files:
c-sb1.c fault.c r4xx0.c tlb-sb1.c tlbex-r4k.S
Log Message:
Updated Mips 64 to OSS tree.
Index: c-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/c-sb1.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- c-sb1.c 24 Apr 2002 17:30:19 -0000 1.6
+++ c-sb1.c 30 May 2002 20:42:11 -0000 1.7
@@ -17,7 +17,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
-
+#include <linux/config.h>
#include <linux/init.h>
#include <asm/mmu_context.h>
#include <asm/bootinfo.h>
@@ -203,7 +203,7 @@
".set pop \n"
:
: "r" (start & ~(icache_line_size - 1)),
- "r" ((end - 1) & ~(dcache_line_size - 1)),
+ "r" ((end - 1) & ~(icache_line_size - 1)),
"r" (icache_line_size),
"i" (Index_Invalidate_I));
}
Index: fault.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/fault.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- fault.c 26 Feb 2002 17:34:15 -0000 1.11
+++ fault.c 30 May 2002 20:42:14 -0000 1.12
@@ -21,6 +21,7 @@
#include <linux/smp_lock.h>
#include <linux/version.h>
+#include <asm/branch.h>
#include <asm/hardirq.h>
#include <asm/pgalloc.h>
#include <asm/mmu_context.h>
@@ -208,7 +209,7 @@
no_context:
/* Are we prepared to handle this kernel fault? */
- fixup = search_exception_table(regs->cp0_epc);
+ fixup = search_exception_table(exception_epc(regs));
if (fixup) {
long new_epc;
Index: r4xx0.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/r4xx0.c,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- r4xx0.c 28 May 2002 20:25:37 -0000 1.15
+++ r4xx0.c 30 May 2002 20:42:14 -0000 1.16
@@ -9,6 +9,7 @@
* Copyright (C) 1997, 1998, 1999, 2000, 2001 Ralf Baechle (ra...@gn...)
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/
+#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
Index: tlb-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/tlb-sb1.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- tlb-sb1.c 19 Feb 2002 17:29:13 -0000 1.2
+++ tlb-sb1.c 30 May 2002 20:42:15 -0000 1.3
@@ -17,6 +17,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
+#include <linux/config.h>
#include <asm/mmu_context.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
@@ -67,7 +68,7 @@
"--------------------------------------------------------------------\n");
dump_cur_tlb_regs();
printk(" %08X\n", read_32bit_cp0_register(CP0_INDEX));
- printk("\n\nFull TLB Dump:"
+ printk("\n\nFull TLB Dump:\n"
"Idx EntryHi EntryLo0 EntryLo1 PageMask\n"
"--------------------------------------------------------------\n");
for (entry = 0; entry < mips_cpu.tlbsize; entry++) {
Index: tlbex-r4k.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/tlbex-r4k.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- tlbex-r4k.S 26 Feb 2002 17:35:25 -0000 1.1
+++ tlbex-r4k.S 30 May 2002 20:42:15 -0000 1.2
@@ -26,17 +26,16 @@
.macro LOAD_PTE2, ptr, tmp
#ifdef CONFIG_SMP
- dmfc0 \tmp, CP0_CONTEXT
- dla \ptr, pgd_current
- dsrl \tmp, 23
- daddu \ptr, \tmp
+ dmfc0 \ptr, CP0_CONTEXT
+ dmfc0 \tmp, CP0_BADVADDR
+ dsra \ptr, 23 # get pgd_current[cpu]
#else
+ dmfc0 \tmp, CP0_BADVADDR
dla \ptr, pgd_current
#endif
- dmfc0 \tmp, CP0_BADVADDR
- ld \ptr, (\ptr)
bltz \tmp, kaddr
- dsrl \tmp, (PGDIR_SHIFT-3) # get pgd offset in bytes
+ ld \ptr, (\ptr)
+ dsrl \tmp, (PGDIR_SHIFT-3) # get pgd offset in bytes
andi \tmp, ((PTRS_PER_PGD - 1)<<3)
daddu \ptr, \tmp # add in pgd offset
dmfc0 \tmp, CP0_BADVADDR
|
|
From: Steve L. <slo...@us...> - 2002-05-29 21:13:55
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv24821
Modified Files:
i8259.c
Log Message:
typo: 'struct pt_regs' arg to i8259_do_irq() must be pointer (missing '*').
Index: i8259.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/i8259.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- i8259.c 2 Jan 2002 20:42:11 -0000 1.9
+++ i8259.c 29 May 2002 21:13:53 -0000 1.10
@@ -262,7 +262,7 @@
spin_unlock_irqrestore(&i8259A_lock, flags);
}
-asmlinkage void i8259_do_irq(int irq, struct pt_regs regs)
+asmlinkage void i8259_do_irq(int irq, struct pt_regs *regs)
{
panic("i8259_do_irq: I want to be implemented");
}
|
|
From: Paul M. <le...@us...> - 2002-05-29 18:20:04
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv29039/arch/mips/kernel Modified Files: setup.c Log Message: Build fixes. Index: setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v retrieving revision 1.63 retrieving revision 1.64 diff -u -d -r1.63 -r1.64 --- setup.c 28 May 2002 20:57:27 -0000 1.63 +++ setup.c 29 May 2002 18:19:58 -0000 1.64 @@ -603,8 +603,8 @@ mips_cpu.isa_level = MIPS_CPU_ISA_M64; mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB | MIPS_CPU_FPU | - MIPS_CPU_FPUEX | MIPS_CPU_COUNTER | - MIPS_CPU_DIVEC | MIPS_CPU_MCHECK; + MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | + MIPS_CPU_MCHECK; mips_cpu.scache.ways = 8; break; } |
|
From: Paul M. <le...@us...> - 2002-05-29 18:20:03
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv29039/include/asm-mips Modified Files: mipsregs.h cpu.h Log Message: Build fixes. Index: mipsregs.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mipsregs.h,v retrieving revision 1.20 retrieving revision 1.21 diff -u -d -r1.20 -r1.21 --- mipsregs.h 9 May 2002 17:22:36 -0000 1.20 +++ mipsregs.h 29 May 2002 18:19:58 -0000 1.21 @@ -52,12 +52,15 @@ #define CP0_XCONTEXT $20 #define CP0_FRAMEMASK $21 #define CP0_DIAGNOSTIC $22 +#define CP0_DEBUG $23 +#define CP0_DEPC $24 #define CP0_PERFORMANCE $25 #define CP0_ECC $26 #define CP0_CACHEERR $27 #define CP0_TAGLO $28 #define CP0_TAGHI $29 #define CP0_ERROREPC $30 +#define CP0_DESAVE $31 #ifdef CONFIG_CPU_LX45XXX #define CP0_CCTL $20 /* Lexra Cache Control Register */ Index: cpu.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cpu.h,v retrieving revision 1.26 retrieving revision 1.27 diff -u -d -r1.26 -r1.27 --- cpu.h 16 May 2002 18:40:07 -0000 1.26 +++ cpu.h 29 May 2002 18:19:58 -0000 1.27 @@ -56,13 +56,12 @@ #define PRID_IMP_R4640 0x2200 #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ #define PRID_IMP_R5000 0x2300 -#define PRID_IMP_TX49 0x2d00 -#define PRID_IMP_R5900 0x2e00 -#define PRID_IMP_TX49 0x2d00 #define PRID_IMP_SONIC 0x2400 #define PRID_IMP_MAGIC 0x2500 #define PRID_IMP_RM7000 0x2700 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ +#define PRID_IMP_TX49 0x2d00 +#define PRID_IMP_R5900 0x2e00 #define PRID_IMP_R5432 0x5400 #define PRID_IMP_R5500 0x5500 #define PRID_IMP_4KC 0x8000 @@ -106,6 +105,7 @@ #define PRID_REV_TX3922 0x0030 #define PRID_REV_TX3927 0x0040 #define PRID_REV_TX3927B 0x0041 +#define PRID_REV_TX4927 0x0022 /* * FPU implementation/revision register (CP1 control register 0). @@ -180,6 +180,6 @@ #define MIPS_CPU_CACHE_CDEX 0x00000800 /* Create_Dirty_Exclusive CACHE op */ #define MIPS_CPU_MCHECK 0x00001000 /* Machine check exception */ #define MIPS_CPU_EJTAG 0x00002000 /* EJTAG exception */ -#define MIPS_CPU_FPUEX 0x00004000 /* FPU exception */ +#define MIPS_CPU_NOFPUEX 0x00004000 /* no FPU exception */ #endif /* _ASM_CPU_H */ |
|
From: Steve L. <slo...@us...> - 2002-05-29 00:23:19
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv21710/include/asm-mips
Modified Files:
au1000.h au1000_dma.h
Added Files:
au1000_usbdev.h
Log Message:
Updates to Au1x00 USB slave support. Split into device layer and two
function-layer drivers, a TTY driver and a raw bidirectional block
driver. Only one IN/OUT block endpoint pair is working correctly
now, so both function-layer drivers have only one bidirectional port.
--- NEW FILE: au1000_usbdev.h ---
/*
* BRIEF MODULE DESCRIPTION
* Au1000 USB Device-Side Driver
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* st...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#define USBDEV_REV 0x0110 // BCD
#define USBDEV_EP0_MAX_PACKET_SIZE 64
typedef enum {
ATTACHED = 0,
POWERED,
DEFAULT,
ADDRESS,
CONFIGURED
} usbdev_state_t;
typedef enum {
CB_NEW_STATE = 0,
CB_PKT_COMPLETE
} usbdev_cb_type_t;
typedef struct usbdev_pkt {
int ep_addr; // ep addr this packet routed to
int size; // size of payload in bytes
unsigned status; // packet status
struct usbdev_pkt* next; // function layer can't touch this
u8 payload[0]; // the payload
} usbdev_pkt_t;
#define PKT_STATUS_ACK (1<<0)
#define PKT_STATUS_NAK (1<<1)
#define PKT_STATUS_SU (1<<2)
extern int usbdev_init(struct usb_device_descriptor* dev_desc,
struct usb_config_descriptor* config_desc,
struct usb_interface_descriptor* if_desc,
struct usb_endpoint_descriptor* ep_desc,
struct usb_string_descriptor* str_desc[],
void (*cb)(usbdev_cb_type_t, unsigned long, void *),
void* cb_data);
extern void usbdev_exit(void);
extern int usbdev_alloc_packet (int ep_addr, int data_size,
usbdev_pkt_t** pkt);
extern int usbdev_send_packet (int ep_addr, usbdev_pkt_t* pkt);
extern int usbdev_receive_packet(int ep_addr, usbdev_pkt_t** pkt);
extern int usbdev_get_byte_count(int ep_addr);
Index: au1000.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/au1000.h,v
retrieving revision 1.19
retrieving revision 1.20
diff -u -d -r1.19 -r1.20
--- au1000.h 1 May 2002 18:00:31 -0000 1.19
+++ au1000.h 29 May 2002 00:23:17 -0000 1.20
@@ -56,24 +56,6 @@
mdelay(ms);
}
-void static inline outb_sync(u8 val, int reg)
-{
- *(volatile u8 *)(reg) = val;
- au_sync();
-}
-
-void static inline outw_sync(u16 val, int reg)
-{
- *(volatile u16 *)(reg) = val;
- au_sync();
-}
-
-void static inline outl_sync(u32 val, int reg)
-{
- *(volatile u32 *)(reg) = val;
- au_sync();
-}
-
void static inline au_writeb(u8 val, int reg)
{
*(volatile u8 *)(reg) = val;
Index: au1000_dma.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/au1000_dma.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- au1000_dma.h 1 May 2002 18:00:31 -0000 1.9
+++ au1000_dma.h 29 May 2002 00:23:17 -0000 1.10
@@ -45,6 +45,7 @@
/* DMA Channel Register Offsets */
#define DMA_MODE_SET 0x00000000
+#define DMA_MODE_READ DMA_MODE_SET
#define DMA_MODE_CLEAR 0x00000004
/* DMA Mode register bits follow */
#define DMA_DAH_MASK (0x0f << 20)
@@ -102,15 +103,21 @@
struct dma_chan {
int dev_id; // this channel is allocated if >=0, free otherwise
unsigned int io;
- int irq;
const char *dev_str;
+ int irq;
+ void *irq_dev;
unsigned int fifo_addr;
unsigned int mode;
};
/* These are in arch/mips/au1000/common/dma.c */
extern struct dma_chan au1000_dma_table[];
-extern int request_au1000_dma(int dev_id, const char *dev_str);
+extern int request_au1000_dma(int dev_id,
+ const char *dev_str,
+ void (*irqhandler)(int, void *,
+ struct pt_regs *),
+ unsigned long irqflags,
+ void *irq_dev_id);
extern void free_au1000_dma(unsigned int dmanr);
extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
int length, int *eof, void *data);
@@ -146,61 +153,92 @@
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- outl_sync(DMA_BE0, chan->io + DMA_MODE_SET);
+ au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
}
static __inline__ void enable_dma_buffer1(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- outl_sync(DMA_BE1, chan->io + DMA_MODE_SET);
+ au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
}
static __inline__ void enable_dma_buffers(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- outl_sync(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
+ au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
}
-/* enable/disable a specific DMA channel */
-static __inline__ void enable_dma(unsigned int dmanr)
+static __inline__ void start_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- // set device FIFO address
- outl_sync(virt_to_phys((void *) chan->fifo_addr),
- chan->io + DMA_PERIPHERAL_ADDR);
-
- outl_sync(chan->mode | (chan->dev_id << DMA_DID_BIT) | DMA_IE | DMA_GO,
- chan->io + DMA_MODE_SET);
+ au_writel(DMA_GO, chan->io + DMA_MODE_SET);
}
#define DMA_HALT_POLL 0x5000
-static __inline__ void disable_dma(unsigned int dmanr)
+static __inline__ void halt_dma(unsigned int dmanr)
{
- int i;
struct dma_chan *chan = get_dma_chan(dmanr);
+ int i;
if (!chan)
return;
- outl_sync(DMA_D1 | DMA_D0 | DMA_GO, chan->io + DMA_MODE_CLEAR);
-
+ au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
// poll the halt bit
for (i = 0; i < DMA_HALT_POLL; i++)
- if (au_readl(chan->io + DMA_MODE_SET) & DMA_HALT)
+ if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
break;
- if (i == DMA_HALT_POLL) {
- printk(KERN_INFO "disable_dma: HALT poll expired!\n");
- } else {
- // now we can disable the buffers
- outl_sync(~DMA_GO, chan->io + DMA_MODE_CLEAR);
- }
+ if (i == DMA_HALT_POLL)
+ printk(KERN_INFO "halt_dma: HALT poll expired!\n");
+}
+
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+ struct dma_chan *chan = get_dma_chan(dmanr);
+ if (!chan)
+ return;
+
+ halt_dma(dmanr);
+
+ // now we can disable the buffers
+ au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
+}
+
+static __inline__ int dma_halted(unsigned int dmanr)
+{
+ struct dma_chan *chan = get_dma_chan(dmanr);
+ if (!chan)
+ return 1;
+ return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
}
+/* initialize a DMA channel */
+static __inline__ void init_dma(unsigned int dmanr)
+{
+ struct dma_chan *chan = get_dma_chan(dmanr);
+ u32 mode;
+ if (!chan)
+ return;
+
+ disable_dma(dmanr);
+
+ // set device FIFO address
+ au_writel(virt_to_phys((void *) chan->fifo_addr),
+ chan->io + DMA_PERIPHERAL_ADDR);
+
+ mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
+ if (chan->irq)
+ mode |= DMA_IE;
+
+ au_writel(~mode, chan->io + DMA_MODE_CLEAR);
+ au_writel(mode, chan->io + DMA_MODE_SET);
+}
/*
* set mode for a specific DMA channel
@@ -233,7 +271,7 @@
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return -1;
- return (au_readl(chan->io + DMA_MODE_SET) & DMA_AB) ? 1 : 0;
+ return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
}
@@ -252,7 +290,7 @@
if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
return;
- outl_sync(virt_to_phys((void *) a),
+ au_writel(virt_to_phys((void *) a),
chan->io + DMA_PERIPHERAL_ADDR);
}
@@ -264,14 +302,14 @@
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- outl_sync(DMA_D0, chan->io + DMA_MODE_CLEAR);
+ au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
}
static __inline__ void clear_dma_done1(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- outl_sync(DMA_D1, chan->io + DMA_MODE_CLEAR);
+ au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
}
/*
@@ -289,7 +327,7 @@
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- outl_sync(a, chan->io + DMA_BUFFER0_START);
+ au_writel(a, chan->io + DMA_BUFFER0_START);
}
/*
@@ -300,7 +338,7 @@
struct dma_chan *chan = get_dma_chan(dmanr);
if (!chan)
return;
- outl_sync(a, chan->io + DMA_BUFFER1_START);
+ au_writel(a, chan->io + DMA_BUFFER1_START);
}
@@ -314,7 +352,7 @@
if (!chan)
return;
count &= DMA_COUNT_MASK;
- outl_sync(count, chan->io + DMA_BUFFER0_COUNT);
+ au_writel(count, chan->io + DMA_BUFFER0_COUNT);
}
/*
@@ -327,7 +365,7 @@
if (!chan)
return;
count &= DMA_COUNT_MASK;
- outl_sync(count, chan->io + DMA_BUFFER1_COUNT);
+ au_writel(count, chan->io + DMA_BUFFER1_COUNT);
}
/*
@@ -340,8 +378,8 @@
if (!chan)
return;
count &= DMA_COUNT_MASK;
- outl_sync(count, chan->io + DMA_BUFFER0_COUNT);
- outl_sync(count, chan->io + DMA_BUFFER1_COUNT);
+ au_writel(count, chan->io + DMA_BUFFER0_COUNT);
+ au_writel(count, chan->io + DMA_BUFFER1_COUNT);
}
/*
@@ -354,7 +392,7 @@
if (!chan)
return 0;
- return au_readl(chan->io + DMA_MODE_SET) & (DMA_D0 | DMA_D1);
+ return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
}
@@ -380,8 +418,8 @@
if (!chan)
return 0;
- curBufCntReg = (au_readl(chan->io + DMA_MODE_SET) & DMA_AB) ?
- DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
+ curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
+ DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
|
|
From: Steve L. <slo...@us...> - 2002-05-29 00:23:19
|
Update of /cvsroot/linux-mips/linux/drivers/sound
In directory usw-pr-cvs1:/tmp/cvs-serv21710/drivers/sound
Modified Files:
au1000.c
Log Message:
Updates to Au1x00 USB slave support. Split into device layer and two
function-layer drivers, a TTY driver and a raw bidirectional block
driver. Only one IN/OUT block endpoint pair is working correctly
now, so both function-layer drivers have only one bidirectional port.
Index: au1000.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/sound/au1000.c,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- au1000.c 2 May 2002 18:49:19 -0000 1.12
+++ au1000.c 29 May 2002 00:23:16 -0000 1.13
@@ -130,7 +130,6 @@
struct dmabuf {
unsigned int dmanr; // DMA Channel number
- int irq; // DMA Channel Done IRQ number
unsigned sample_rate; // Hz
unsigned src_factor; // SRC interp/decimation (no vra)
unsigned sample_size; // 8 or 16
@@ -443,7 +442,7 @@
spin_lock_irqsave(&s->lock, flags);
- disable_dma(db->dmanr);
+ halt_dma(db->dmanr);
db->stopped = 1;
@@ -460,7 +459,7 @@
spin_lock_irqsave(&s->lock, flags);
- disable_dma(db->dmanr);
+ halt_dma(db->dmanr);
db->stopped = 1;
@@ -522,17 +521,19 @@
set_xmit_slots(db->num_channels);
- set_dma_count(db->dmanr, db->dma_fragsize>>1);
if (get_dma_active_buffer(db->dmanr) == 0) {
+ clear_dma_done0(db->dmanr); // clear DMA done bit
set_dma_addr0(db->dmanr, buf1);
set_dma_addr1(db->dmanr, buf2);
} else {
+ clear_dma_done1(db->dmanr); // clear DMA done bit
set_dma_addr1(db->dmanr, buf1);
set_dma_addr0(db->dmanr, buf2);
}
+ set_dma_count(db->dmanr, db->dma_fragsize>>1);
enable_dma_buffers(db->dmanr);
-
- enable_dma(db->dmanr);
+
+ start_dma(db->dmanr);
#ifdef AU1000_VERBOSE_DEBUG
dump_au1000_dma_channel(db->dmanr);
@@ -564,17 +565,19 @@
set_recv_slots(db->num_channels);
- set_dma_count(db->dmanr, db->dma_fragsize>>1);
if (get_dma_active_buffer(db->dmanr) == 0) {
+ clear_dma_done0(db->dmanr); // clear DMA done bit
set_dma_addr0(db->dmanr, buf1);
set_dma_addr1(db->dmanr, buf2);
} else {
+ clear_dma_done1(db->dmanr); // clear DMA done bit
set_dma_addr1(db->dmanr, buf1);
set_dma_addr0(db->dmanr, buf2);
}
+ set_dma_count(db->dmanr, db->dma_fragsize>>1);
enable_dma_buffers(db->dmanr);
- enable_dma(db->dmanr);
+ start_dma(db->dmanr);
#ifdef AU1000_VERBOSE_DEBUG
dump_au1000_dma_channel(db->dmanr);
@@ -2026,18 +2029,24 @@
}
// Allocate the DMA Channels
if ((s->dma_dac.dmanr = request_au1000_dma(DMA_ID_AC97C_TX,
- "audio DAC")) < 0) {
+ "audio DAC",
+ dac_dma_interrupt,
+ SA_INTERRUPT, s)) < 0) {
err("Can't get DAC DMA");
goto err_dma1;
}
if ((s->dma_adc.dmanr = request_au1000_dma(DMA_ID_AC97C_RX,
- "audio ADC")) < 0) {
+ "audio ADC",
+ adc_dma_interrupt,
+ SA_INTERRUPT, s)) < 0) {
err("Can't get ADC DMA");
goto err_dma2;
}
- s->dma_dac.irq = get_dma_done_irq(s->dma_dac.dmanr);
- s->dma_adc.irq = get_dma_done_irq(s->dma_adc.dmanr);
+ info("DAC: DMA%d/IRQ%d, ADC: DMA%d/IRQ%d",
+ s->dma_dac.dmanr, get_dma_done_irq(s->dma_dac.dmanr),
+ s->dma_adc.dmanr, get_dma_done_irq(s->dma_adc.dmanr));
+
#ifdef USE_COHERENT_DMA
// enable DMA coherency in read/write DMA channels
set_dma_mode(s->dma_dac.dmanr,
@@ -2052,21 +2061,6 @@
get_dma_mode(s->dma_adc.dmanr) | DMA_NC);
#endif
- if (request_irq(s->dma_dac.irq, dac_dma_interrupt,
- SA_INTERRUPT, "audio DAC", s)) {
- err("Can't get DAC irq #%d", s->dma_dac.irq);
- goto err_irq1;
- }
- if (request_irq(s->dma_adc.irq, adc_dma_interrupt,
- SA_INTERRUPT, "audio ADC", s)) {
- err("Can't get ADC irq #%d", s->dma_adc.irq);
- goto err_irq2;
- }
-
- info("DAC: DMA%d/IRQ%d, ADC: DMA%d/IRQ%d",
- s->dma_dac.dmanr, s->dma_dac.irq,
- s->dma_adc.dmanr, s->dma_adc.irq);
-
/* register devices */
if ((s->dev_audio = register_sound_dsp(&au1000_audio_fops, -1)) < 0)
@@ -2164,10 +2158,6 @@
err_dma2:
free_au1000_dma(s->dma_dac.dmanr);
err_dma1:
- free_irq(s->dma_adc.irq, s);
- err_irq2:
- free_irq(s->dma_dac.irq, s);
- err_irq1:
release_region(virt_to_phys((void *) AC97C_CONFIG), 0x14);
return -1;
}
@@ -2183,8 +2173,6 @@
remove_proc_entry(AU1000_MODULE_NAME, NULL);
#endif /* AU1000_DEBUG */
synchronize_irq();
- free_irq(s->dma_adc.irq, s);
- free_irq(s->dma_dac.irq, s);
free_au1000_dma(s->dma_adc.dmanr);
free_au1000_dma(s->dma_dac.dmanr);
release_region(virt_to_phys((void *) AC97C_CONFIG), 0x14);
|
|
From: Steve L. <slo...@us...> - 2002-05-29 00:23:19
|
Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv21710/drivers/char
Modified Files:
Config.in Makefile
Added Files:
au1000_usbraw.c au1000_usbtty.c
Log Message:
Updates to Au1x00 USB slave support. Split into device layer and two
function-layer drivers, a TTY driver and a raw bidirectional block
driver. Only one IN/OUT block endpoint pair is working correctly
now, so both function-layer drivers have only one bidirectional port.
--- NEW FILE: au1000_usbraw.c ---
/*
* BRIEF MODULE DESCRIPTION
* Au1x00 USB Device-Side Raw Block Driver (function layer)
*
* Copyright 2001-2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* st...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/signal.h>
#include <linux/errno.h>
#include <linux/poll.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/fcntl.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/smp_lock.h>
#undef DEBUG
#include <linux/usb.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/irq.h>
#include <asm/au1000.h>
#include <asm/au1000_usbdev.h>
#define USBRAW_MAJOR 190 // FIXME: need a legal major
#define USBRAW_NAME "usbraw"
#define MAX_NUM_PORTS 2
#define IN_MAX_PACKET_SIZE 64
#define OUT_MAX_PACKET_SIZE 64
// FIXME: when Au1x00 endpoints 3 and 5 are fixed, make NUM_PORTS=2
#define NUM_PORTS 1
#define NUM_EP 2*NUM_PORTS
#define CONFIG_DESC_LEN \
USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + NUM_EP*USB_DT_ENDPOINT_SIZE
/* must be power of two */
#define READ_BUF_SIZE (1<<12)
struct usb_raw_port {
unsigned char number;
spinlock_t port_lock;
struct usb_endpoint_descriptor* out_desc;
struct usb_endpoint_descriptor* in_desc;
int out_ep_addr; /* endpoint address of OUT endpoint */
int in_ep_addr; /* endpoint address of IN endpoint */
__u8 read_buf[READ_BUF_SIZE]; // FIXME: allocate with get_free_pages
int read_nextin, read_nextout;
int read_count;
wait_queue_head_t wait;
struct fasync_struct *fasync; // asynch notification
int active; /* someone has this device open */
int open_count; /* number of times this port has been opened */
};
static struct usb_serial {
struct usb_device_descriptor* dev_desc;
struct usb_config_descriptor* config_desc;
struct usb_interface_descriptor* if_desc;
struct usb_string_descriptor * str_desc[6];
void* str_desc_buf;
usbdev_state_t dev_state;
struct usb_raw_port port[NUM_PORTS];
} usbraw;
static struct usb_device_descriptor dev_desc = {
bLength:USB_DT_DEVICE_SIZE,
bDescriptorType:USB_DT_DEVICE,
bcdUSB:USBDEV_REV, //usb rev
bDeviceClass:USB_CLASS_PER_INTERFACE, //class (none)
bDeviceSubClass:0x00, //subclass (none)
bDeviceProtocol:0x00, //protocol (none)
bMaxPacketSize0:USBDEV_EP0_MAX_PACKET_SIZE, //max packet size for ep0
idVendor:0x6d04, //vendor id
idProduct:0x0bc0, //product id
bcdDevice:0x0001, //BCD rev 0.1
iManufacturer:0x01, //manufactuer string index
iProduct:0x02, //product string index
iSerialNumber:0x03, //serial# string index
bNumConfigurations:0x01 //num configurations
};
static struct usb_endpoint_descriptor ep_desc[] = {
{
// Bulk IN for Port 0
bLength:USB_DT_ENDPOINT_SIZE,
bDescriptorType:USB_DT_ENDPOINT,
bEndpointAddress:USB_DIR_IN,
bmAttributes:USB_ENDPOINT_XFER_BULK,
wMaxPacketSize:IN_MAX_PACKET_SIZE,
bInterval:0x00 // ignored for bulk
},
{
// Bulk OUT for Port 0
bLength:USB_DT_ENDPOINT_SIZE,
bDescriptorType:USB_DT_ENDPOINT,
bEndpointAddress:USB_DIR_OUT,
bmAttributes:USB_ENDPOINT_XFER_BULK,
wMaxPacketSize:OUT_MAX_PACKET_SIZE,
bInterval:0x00 // ignored for bulk
},
{
// Bulk IN for Port 1
bLength:USB_DT_ENDPOINT_SIZE,
bDescriptorType:USB_DT_ENDPOINT,
bEndpointAddress:USB_DIR_IN,
bmAttributes:USB_ENDPOINT_XFER_BULK,
wMaxPacketSize:IN_MAX_PACKET_SIZE,
bInterval:0x00 // ignored for bulk
},
{
// Bulk OUT for Port 1
bLength:USB_DT_ENDPOINT_SIZE,
bDescriptorType:USB_DT_ENDPOINT,
bEndpointAddress:USB_DIR_OUT,
bmAttributes:USB_ENDPOINT_XFER_BULK,
wMaxPacketSize:OUT_MAX_PACKET_SIZE,
bInterval:0x00 // ignored for bulk
}
};
static struct usb_interface_descriptor if_desc = {
bLength:USB_DT_INTERFACE_SIZE,
bDescriptorType:USB_DT_INTERFACE,
bInterfaceNumber:0x00,
bAlternateSetting:0x00,
bNumEndpoints:NUM_EP,
bInterfaceClass:0xff,
bInterfaceSubClass:0xab,
bInterfaceProtocol:0x00,
iInterface:0x05
};
static struct usb_config_descriptor config_desc = {
bLength:USB_DT_CONFIG_SIZE,
bDescriptorType:USB_DT_CONFIG,
wTotalLength:CONFIG_DESC_LEN,
bNumInterfaces:0x01,
bConfigurationValue:0x01,
iConfiguration:0x04, // configuration string
bmAttributes:0xc0, // self-powered
MaxPower:20 // 40 mA
};
// String[0] is a list of Language IDs supported by this device
static struct usb_string_descriptor string_desc0 = {
bLength:4,
bDescriptorType:USB_DT_STRING,
wData:{0x0409} // English, US
};
// These strings will be converted to Unicode in string_desc[]
static char *strings[5] = {
"Alchemy Semiconductor", // iManufacturer
"USB Raw Block Device", // iProduct
"0.1", // iSerialNumber
"USB Raw Config", // iConfiguration
"USB Raw Interface" // iInterface
};
static void
receive_callback(struct usb_raw_port *port)
{
int i, pkt_size;
usbdev_pkt_t* pkt;
if ((pkt_size = usbdev_receive_packet(port->out_ep_addr,
&pkt)) <= 0) {
dbg(__FUNCTION__ ": usbdev_receive_packet returns %d",
pkt_size);
return;
}
dbg(__FUNCTION__ ": ep%d, size=%d", port->out_ep_addr, pkt_size);
spin_lock(&port->port_lock);
for (i=0; i < pkt_size; i++) {
port->read_buf[port->read_nextin++] = pkt->payload[i];
port->read_nextin &= (READ_BUF_SIZE - 1);
if (++port->read_count == READ_BUF_SIZE)
break;
}
spin_unlock(&port->port_lock);
/* free the packet */
kfree(pkt);
// async notify
if (port->fasync)
kill_fasync(&port->fasync, SIGIO, POLL_IN);
// wake up any read call
if (waitqueue_active(&port->wait))
wake_up_interruptible(&port->wait);
}
static void
transmit_callback(struct usb_raw_port *port, usbdev_pkt_t* pkt)
{
dbg(__FUNCTION__ ": ep%d", port->in_ep_addr);
/* just free the returned packet */
kfree(pkt);
}
static void
usbraw_callback(usbdev_cb_type_t cb_type, unsigned long arg, void* data)
{
usbdev_pkt_t* pkt;
int i;
switch (cb_type) {
case CB_NEW_STATE:
usbraw.dev_state = (usbdev_state_t)arg;
break;
case CB_PKT_COMPLETE:
pkt = (usbdev_pkt_t*)arg;
for (i=0; i<NUM_PORTS; i++) {
struct usb_raw_port *port = &usbraw.port[i];
if (pkt->ep_addr == port->in_ep_addr) {
transmit_callback(port, pkt);
break;
} else if (pkt->ep_addr == port->out_ep_addr) {
receive_callback(port);
break;
}
}
break;
}
}
/*****************************************************************************
* Here begins the driver interface functions
*****************************************************************************/
static unsigned int usbraw_poll(struct file * filp, poll_table * wait)
{
struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
unsigned long flags;
int count;
poll_wait(filp, &port->wait, wait);
spin_lock_irqsave(&port->port_lock, flags);
count = port->read_count;
spin_unlock_irqrestore(&port->port_lock, flags);
if (count > 0) {
dbg(__FUNCTION__ ": count=%d", count);
return POLLIN | POLLRDNORM;
}
return 0;
}
static int usbraw_fasync(int fd, struct file *filp, int mode)
{
struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
return fasync_helper(fd, filp, mode, &port->fasync);
}
static int usbraw_open(struct inode * inode, struct file *filp)
{
int portNumber;
struct usb_raw_port *port;
unsigned long flags;
/*
* the device-layer must be in the configured state before the
* function layer can operate.
*/
if (usbraw.dev_state != CONFIGURED)
return -ENODEV;
MOD_INC_USE_COUNT;
/* set up our port structure making the tty driver remember
our port object, and us it */
portNumber = MINOR(inode->i_rdev);
port = &usbraw.port[portNumber];
filp->private_data = port;
dbg(__FUNCTION__ ": port %d", port->number);
spin_lock_irqsave(&port->port_lock, flags);
++port->open_count;
if (!port->active) {
port->active = 1;
}
/* flush read buffer */
port->read_nextin = port->read_nextout = port->read_count = 0;
spin_unlock_irqrestore(&port->port_lock, flags);
return 0;
}
static int usbraw_release(struct inode * inode, struct file * filp)
{
struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
unsigned long flags;
dbg(__FUNCTION__ ": port %d", port->number);
if (!port->active) {
err(__FUNCTION__ ": port not opened");
return -ENODEV;
}
usbraw_fasync(-1, filp, 0);
spin_lock_irqsave(&port->port_lock, flags);
--port->open_count;
if (port->open_count <= 0) {
port->active = 0;
port->open_count = 0;
}
spin_unlock_irqrestore(&port->port_lock, flags);
MOD_DEC_USE_COUNT;
return 0;
}
static ssize_t usbraw_read(struct file * filp, char * buf,
size_t count, loff_t * l)
{
struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
unsigned long flags;
int i, cnt;
/*
* the device-layer must be in the configured state before the
* function layer can operate.
*/
if (usbraw.dev_state != CONFIGURED)
return -ENODEV;
do {
spin_lock_irqsave(&port->port_lock, flags);
cnt = port->read_count;
spin_unlock_irqrestore(&port->port_lock, flags);
if (cnt == 0) {
if (filp->f_flags & O_NONBLOCK)
return -EAGAIN;
interruptible_sleep_on(&port->wait);
if (signal_pending(current))
return -ERESTARTSYS;
}
} while (cnt == 0);
count = (count > cnt) ? cnt : count;
for (i=0; i<count; i++) {
put_user(port->read_buf[port->read_nextout++], &buf[i]);
port->read_nextout &= (READ_BUF_SIZE - 1);
spin_lock_irqsave(&port->port_lock, flags);
port->read_count--;
spin_unlock_irqrestore(&port->port_lock, flags);
if (port->read_count == 0)
break;
}
return i+1;
}
static ssize_t usbraw_write(struct file * filp, const char * buf,
size_t count, loff_t *ppos)
{
struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
usbdev_pkt_t* pkt;
int ret, max_pkt_sz;
/*
* the device-layer must be in the configured state before the
* function layer can operate.
*/
if (usbraw.dev_state != CONFIGURED)
return -ENODEV;
if (!port->active) {
err(__FUNCTION__ ": port not opened");
return -EINVAL;
}
if (count == 0) {
dbg(__FUNCTION__ ": write request of 0 bytes");
return (0);
}
max_pkt_sz = port->in_desc->wMaxPacketSize;
count = (count > max_pkt_sz) ? max_pkt_sz : count;
if ((ret = usbdev_alloc_packet(port->in_ep_addr, count, &pkt)) < 0)
return ret;
copy_from_user(pkt->payload, buf, count);
return usbdev_send_packet(port->in_ep_addr, pkt);
}
static int usbraw_ioctl(struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg)
{
struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
if (!port->active) {
err(__FUNCTION__ ": port not open");
return -ENODEV;
}
// FIXME: need any IOCTLs?
return -ENOIOCTLCMD;
}
static struct file_operations usbraw_fops = {
owner: THIS_MODULE,
write: usbraw_write,
read: usbraw_read,
poll: usbraw_poll,
ioctl: usbraw_ioctl,
fasync: usbraw_fasync,
open: usbraw_open,
release: usbraw_release,
};
void usbfn_raw_exit(void)
{
/* kill the device layer */
usbdev_exit();
unregister_chrdev(USBRAW_MAJOR, USBRAW_NAME);
if (usbraw.str_desc_buf)
kfree(usbraw.str_desc_buf);
}
int usbfn_raw_init(void)
{
int ret = 0, i, str_desc_len;
/* register our character device */
if ((ret = register_chrdev(USBRAW_MAJOR, USBRAW_NAME,
&usbraw_fops)) < 0) {
err("can't get major number");
return ret;
}
info("registered");
/*
* initialize pointers to descriptors
*/
usbraw.dev_desc = &dev_desc;
usbraw.config_desc = &config_desc;
usbraw.if_desc = &if_desc;
/*
* initialize the string descriptors
*/
/* alloc buffer big enough for all string descriptors */
str_desc_len = string_desc0.bLength;
for (i = 0; i < 5; i++)
str_desc_len += 2 + 2 * strlen(strings[i]);
usbraw.str_desc_buf = (void *) kmalloc(str_desc_len, GFP_KERNEL);
if (!usbraw.str_desc_buf) {
err(__FUNCTION__ ": failed to alloc string descriptors");
ret = -ENOMEM;
goto out;
}
usbraw.str_desc[0] =
(struct usb_string_descriptor *)usbraw.str_desc_buf;
memcpy(usbraw.str_desc[0], &string_desc0, string_desc0.bLength);
usbraw.str_desc[1] = (struct usb_string_descriptor *)
(usbraw.str_desc_buf + string_desc0.bLength);
for (i = 1; i < 6; i++) {
struct usb_string_descriptor *desc = usbraw.str_desc[i];
char *str = strings[i - 1];
int j, str_len = strlen(str);
desc->bLength = 2 + 2 * str_len;
desc->bDescriptorType = USB_DT_STRING;
for (j = 0; j < str_len; j++) {
desc->wData[j] = (u16) str[j];
}
if (i < 5)
usbraw.str_desc[i + 1] =
(struct usb_string_descriptor *)
((u8 *) desc + desc->bLength);
}
/*
* start the device layer. The device layer assigns us
* our endpoint addresses
*/
if ((ret = usbdev_init(&dev_desc, &config_desc, &if_desc, ep_desc,
usbraw.str_desc, usbraw_callback, NULL))) {
err(__FUNCTION__ ": device-layer init failed");
goto out;
}
/* initialize the devfs nodes for this device and let the user
know what ports we are bound to */
for (i = 0; i < NUM_PORTS; ++i) {
struct usb_raw_port *port = &usbraw.port[i];
port->number = i;
port->in_desc = &ep_desc[NUM_PORTS*i];
port->out_desc = &ep_desc[NUM_PORTS*i + 1];
port->in_ep_addr = port->in_desc->bEndpointAddress & 0x0f;
port->out_ep_addr = port->out_desc->bEndpointAddress & 0x0f;
init_waitqueue_head(&port->wait);
spin_lock_init(&port->port_lock);
}
out:
if (ret)
usbfn_raw_exit();
return ret;
}
/* Module information */
MODULE_AUTHOR("Steve Longerbeam, st...@mv..., www.mvista.com");
MODULE_DESCRIPTION("Au1x00 USB Device-Side Raw Block Driver");
MODULE_LICENSE("GPL");
module_init(usbfn_raw_init);
module_exit(usbfn_raw_exit);
--- NEW FILE: au1000_usbtty.c ---
/*
* BRIEF MODULE DESCRIPTION
* Au1x00 USB Device-Side Serial TTY Driver (function layer)
*
* Copyright 2001-2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* st...@mv... or so...@mv...
*
* Derived from drivers/usb/serial/usbserial.c:
*
* Copyright (C) 1999 - 2001 Greg Kroah-Hartman (gr...@kr...)
* Copyright (c) 2000 Peter Berger (pb...@br...)
* Copyright (c) 2000 Al Borchers (bor...@st...)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/signal.h>
#include <linux/errno.h>
#include <linux/poll.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/fcntl.h>
#include <linux/tty.h>
#include <linux/tty_driver.h>
#include <linux/tty_flip.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/smp_lock.h>
#undef DEBUG
#include <linux/usb.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/irq.h>
#include <asm/au1000.h>
#include <asm/au1000_usbdev.h>
/* local function prototypes */
static int serial_open(struct tty_struct *tty, struct file *filp);
static void serial_close(struct tty_struct *tty, struct file *filp);
static int serial_write(struct tty_struct *tty, int from_user,
const unsigned char *buf, int count);
static int serial_write_room(struct tty_struct *tty);
static int serial_chars_in_buffer(struct tty_struct *tty);
static void serial_throttle(struct tty_struct *tty);
static void serial_unthrottle(struct tty_struct *tty);
static int serial_ioctl(struct tty_struct *tty, struct file *file,
unsigned int cmd, unsigned long arg);
static void serial_set_termios (struct tty_struct *tty, struct termios * old);
#define SERIAL_TTY_MAJOR 189 // FIXME: need a legal major
#define MAX_NUM_PORTS 2
#define IN_MAX_PACKET_SIZE 32
#define OUT_MAX_PACKET_SIZE 32
// FIXME: when Au1x00 endpoints 3 and 5 are fixed, make NUM_PORTS=2
#define NUM_PORTS 2
#define NUM_EP 2*NUM_PORTS
#define CONFIG_DESC_LEN \
USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + NUM_EP*USB_DT_ENDPOINT_SIZE
struct usb_serial_port {
struct tty_struct *tty; /* the coresponding tty for this port */
unsigned char number;
spinlock_t port_lock;
struct usb_endpoint_descriptor* out_desc;
struct usb_endpoint_descriptor* in_desc;
int out_ep_addr; /* endpoint address of OUT endpoint */
int in_ep_addr; /* endpoint address of IN endpoint */
/* task queue for line discipline waking up on send packet complete */
struct tq_struct send_complete_tq;
/* task queue for line discipline wakeup on receive packet complete */
struct tq_struct receive_complete_tq;
int active; /* someone has this device open */
int writing; /* a packet write is in progress */
int open_count; /* number of times this port has been opened */
};
static struct usb_serial {
usbdev_state_t dev_state; // current state of device layer
struct usb_device_descriptor* dev_desc;
struct usb_config_descriptor* config_desc;
struct usb_interface_descriptor* if_desc;
struct usb_string_descriptor * str_desc[6];
void* str_desc_buf;
struct usb_serial_port port[NUM_PORTS];
} usbtty;
static int serial_refcount;
static struct tty_driver serial_tty_driver;
static struct tty_struct * serial_tty[NUM_PORTS];
static struct termios * serial_termios[NUM_PORTS];
static struct termios * serial_termios_locked[NUM_PORTS];
static struct usb_device_descriptor dev_desc = {
bLength:USB_DT_DEVICE_SIZE,
bDescriptorType:USB_DT_DEVICE,
bcdUSB:USBDEV_REV, //usb rev
bDeviceClass:USB_CLASS_PER_INTERFACE, //class (none)
bDeviceSubClass:0x00, //subclass (none)
bDeviceProtocol:0x00, //protocol (none)
bMaxPacketSize0:USBDEV_EP0_MAX_PACKET_SIZE, //max packet size for ep0
idVendor:0x6d04, //vendor id
idProduct:0x0bc0, //product id
bcdDevice:0x0001, //BCD rev 0.1
iManufacturer:0x01, //manufactuer string index
iProduct:0x02, //product string index
iSerialNumber:0x03, //serial# string index
bNumConfigurations:0x01 //num configurations
};
static struct usb_endpoint_descriptor ep_desc[] = {
{
// Bulk IN for Port 0
bLength:USB_DT_ENDPOINT_SIZE,
bDescriptorType:USB_DT_ENDPOINT,
bEndpointAddress:USB_DIR_IN,
bmAttributes:USB_ENDPOINT_XFER_BULK,
wMaxPacketSize:IN_MAX_PACKET_SIZE,
bInterval:0x00 // ignored for bulk
},
{
// Bulk OUT for Port 0
bLength:USB_DT_ENDPOINT_SIZE,
bDescriptorType:USB_DT_ENDPOINT,
bEndpointAddress:USB_DIR_OUT,
bmAttributes:USB_ENDPOINT_XFER_BULK,
wMaxPacketSize:OUT_MAX_PACKET_SIZE,
bInterval:0x00 // ignored for bulk
},
{
// Bulk IN for Port 1
bLength:USB_DT_ENDPOINT_SIZE,
bDescriptorType:USB_DT_ENDPOINT,
bEndpointAddress:USB_DIR_IN,
bmAttributes:USB_ENDPOINT_XFER_BULK,
wMaxPacketSize:IN_MAX_PACKET_SIZE,
bInterval:0x00 // ignored for bulk
},
{
// Bulk OUT for Port 1
bLength:USB_DT_ENDPOINT_SIZE,
bDescriptorType:USB_DT_ENDPOINT,
bEndpointAddress:USB_DIR_OUT,
bmAttributes:USB_ENDPOINT_XFER_BULK,
wMaxPacketSize:OUT_MAX_PACKET_SIZE,
bInterval:0x00 // ignored for bulk
}
};
static struct usb_interface_descriptor if_desc = {
bLength:USB_DT_INTERFACE_SIZE,
bDescriptorType:USB_DT_INTERFACE,
bInterfaceNumber:0x00,
bAlternateSetting:0x00,
bNumEndpoints:NUM_EP,
bInterfaceClass:0xff,
bInterfaceSubClass:0xab,
bInterfaceProtocol:0x00,
iInterface:0x05
};
static struct usb_config_descriptor config_desc = {
bLength:USB_DT_CONFIG_SIZE,
bDescriptorType:USB_DT_CONFIG,
wTotalLength:CONFIG_DESC_LEN,
bNumInterfaces:0x01,
bConfigurationValue:0x01,
iConfiguration:0x04, // configuration string
bmAttributes:0xc0, // self-powered
MaxPower:20 // 40 mA
};
// String[0] is a list of Language IDs supported by this device
static struct usb_string_descriptor string_desc0 = {
bLength:4,
bDescriptorType:USB_DT_STRING,
wData:{0x0409} // English, US
};
// These strings will be converted to Unicode in string_desc[]
static char *strings[5] = {
"Alchemy Semiconductor", // iManufacturer
"WutzAMattaU", // iProduct
"1.0.doh!", // iSerialNumber
"Au1000 TTY Config", // iConfiguration
"Au1000 TTY Interface" // iInterface
};
static inline int
port_paranoia_check(struct usb_serial_port *port, const char *function)
{
if (!port) {
err("%s: port is NULL", function);
return -1;
}
if (!port->tty) {
err("%s: port->tty is NULL", function);
return -1;
}
return 0;
}
static void
port_rx_callback(struct usb_serial_port *port)
{
dbg(__FUNCTION__ ": ep%d", port->out_ep_addr);
// mark a bh to push this data up to the tty
queue_task(&port->receive_complete_tq, &tq_immediate);
mark_bh(IMMEDIATE_BH);
}
static void
port_tx_callback(struct usb_serial_port *port, usbdev_pkt_t* pkt)
{
dbg(__FUNCTION__ ": ep%d", port->in_ep_addr);
// mark a bh to wakeup any tty write system call on the port.
queue_task(&port->send_complete_tq, &tq_immediate);
mark_bh(IMMEDIATE_BH);
/* free the returned packet */
kfree(pkt);
}
static void
usbtty_callback(usbdev_cb_type_t cb_type, unsigned long arg, void* data)
{
usbdev_pkt_t* pkt;
int i;
switch (cb_type) {
case CB_NEW_STATE:
dbg(__FUNCTION__ ": new dev_state=%d", (int)arg);
usbtty.dev_state = (usbdev_state_t)arg;
break;
case CB_PKT_COMPLETE:
pkt = (usbdev_pkt_t*)arg;
for (i=0; i<NUM_PORTS; i++) {
struct usb_serial_port *port = &usbtty.port[i];
if (pkt->ep_addr == port->in_ep_addr) {
port_tx_callback(port, pkt);
break;
} else if (pkt->ep_addr == port->out_ep_addr) {
port_rx_callback(port);
break;
}
}
break;
}
}
/*****************************************************************************
* Here begins the tty driver interface functions
*****************************************************************************/
static int serial_open(struct tty_struct *tty, struct file *filp)
{
int portNumber;
struct usb_serial_port *port;
unsigned long flags;
/* initialize the pointer incase something fails */
tty->driver_data = NULL;
MOD_INC_USE_COUNT;
/* set up our port structure making the tty driver remember
our port object, and us it */
portNumber = MINOR(tty->device);
port = &usbtty.port[portNumber];
tty->driver_data = port;
port->tty = tty;
if (usbtty.dev_state != CONFIGURED ||
port_paranoia_check(port, __FUNCTION__)) {
/*
* the device-layer must be in the configured state before
* the function layer can operate.
*/
MOD_DEC_USE_COUNT;
return -ENODEV;
}
dbg(__FUNCTION__ ": port %d", port->number);
spin_lock_irqsave(&port->port_lock, flags);
++port->open_count;
if (!port->active) {
port->active = 1;
/*
* force low_latency on so that our tty_push actually forces
* the data through, otherwise it is scheduled, and with high
* data rates (like with OHCI) data can get lost.
*/
port->tty->low_latency = 1;
}
spin_unlock_irqrestore(&port->port_lock, flags);
return 0;
}
static void serial_close(struct tty_struct *tty, struct file *filp)
{
struct usb_serial_port *port =
(struct usb_serial_port *) tty->driver_data;
unsigned long flags;
dbg(__FUNCTION__ ": port %d", port->number);
if (!port->active) {
err(__FUNCTION__ ": port not opened");
return;
}
spin_lock_irqsave(&port->port_lock, flags);
--port->open_count;
if (port->open_count <= 0) {
port->active = 0;
port->open_count = 0;
}
spin_unlock_irqrestore(&port->port_lock, flags);
MOD_DEC_USE_COUNT;
}
static int serial_write(struct tty_struct *tty, int from_user,
const unsigned char *buf, int count)
{
struct usb_serial_port *port =
(struct usb_serial_port *) tty->driver_data;
usbdev_pkt_t* pkt;
int max_pkt_sz, ret;
unsigned long flags;
/*
* the device-layer must be in the configured state before the
* function layer can operate.
*/
if (usbtty.dev_state != CONFIGURED)
return -ENODEV;
if (!port->active) {
err(__FUNCTION__ ": port not open");
return -EINVAL;
}
if (count == 0) {
dbg(__FUNCTION__ ": request of 0 bytes");
return (0);
}
#if 0
if (port->writing) {
dbg(__FUNCTION__ ": already writing");
return 0;
}
#endif
max_pkt_sz = port->in_desc->wMaxPacketSize;
count = (count > max_pkt_sz) ? max_pkt_sz : count;
if ((ret = usbdev_alloc_packet(port->in_ep_addr, count, &pkt)))
return ret;
if (from_user)
copy_from_user(pkt->payload, buf, count);
else
memcpy(pkt->payload, buf, count);
ret = usbdev_send_packet(port->in_ep_addr, pkt);
spin_lock_irqsave(&port->port_lock, flags);
port->writing = 1;
spin_unlock_irqrestore(&port->port_lock, flags);
return ret;
}
static int serial_write_room(struct tty_struct *tty)
{
struct usb_serial_port *port =
(struct usb_serial_port *) tty->driver_data;
int room = 0;
/*
* the device-layer must be in the configured state before the
* function layer can operate.
*/
if (usbtty.dev_state != CONFIGURED)
return -ENODEV;
if (!port->active) {
err(__FUNCTION__ ": port not open");
return -EINVAL;
}
//room = port->writing ? 0 : port->in_desc->wMaxPacketSize;
room = port->in_desc->wMaxPacketSize;
dbg(__FUNCTION__ ": %d", room);
return room;
}
static int serial_chars_in_buffer(struct tty_struct *tty)
{
struct usb_serial_port *port =
(struct usb_serial_port *) tty->driver_data;
int chars = 0;
/*
* the device-layer must be in the configured state before the
* function layer can operate.
*/
if (usbtty.dev_state != CONFIGURED)
return -ENODEV;
if (!port->active) {
err(__FUNCTION__ ": port not open");
return -EINVAL;
}
//chars = port->writing ? usbdev_get_byte_count(port->in_ep_addr) : 0;
chars = usbdev_get_byte_count(port->in_ep_addr);
dbg(__FUNCTION__ ": %d", chars);
return chars;
}
static void serial_throttle(struct tty_struct *tty)
{
struct usb_serial_port *port =
(struct usb_serial_port *) tty->driver_data;
if (!port->active || usbtty.dev_state != CONFIGURED) {
err(__FUNCTION__ ": port not open");
return;
}
// FIXME: anything to do?
dbg(__FUNCTION__);
}
static void serial_unthrottle(struct tty_struct *tty)
{
struct usb_serial_port *port =
(struct usb_serial_port *) tty->driver_data;
if (!port->active || usbtty.dev_state != CONFIGURED) {
err(__FUNCTION__ ": port not open");
return;
}
// FIXME: anything to do?
dbg(__FUNCTION__);
}
static int serial_ioctl(struct tty_struct *tty, struct file *file,
unsigned int cmd, unsigned long arg)
{
struct usb_serial_port *port =
(struct usb_serial_port *) tty->driver_data;
if (!port->active) {
err(__FUNCTION__ ": port not open");
return -ENODEV;
}
// FIXME: need any IOCTLs?
dbg(__FUNCTION__);
return -ENOIOCTLCMD;
}
static void serial_set_termios(struct tty_struct *tty, struct termios *old)
{
struct usb_serial_port *port =
(struct usb_serial_port *) tty->driver_data;
if (!port->active || usbtty.dev_state != CONFIGURED) {
err(__FUNCTION__ ": port not open");
return;
}
dbg(__FUNCTION__);
// FIXME: anything to do?
}
static void serial_break(struct tty_struct *tty, int break_state)
{
struct usb_serial_port *port =
(struct usb_serial_port *) tty->driver_data;
if (!port->active || usbtty.dev_state != CONFIGURED) {
err(__FUNCTION__ ": port not open");
return;
}
dbg(__FUNCTION__);
// FIXME: anything to do?
}
static void port_send_complete(void *private)
{
struct usb_serial_port *port = (struct usb_serial_port *) private;
struct tty_struct *tty;
unsigned long flags;
dbg(__FUNCTION__ ": port %d, ep%d", port->number, port->in_ep_addr);
tty = port->tty;
if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
tty->ldisc.write_wakeup) {
dbg(__FUNCTION__ ": write wakeup call.");
(tty->ldisc.write_wakeup) (tty);
}
wake_up_interruptible(&tty->write_wait);
spin_lock_irqsave(&port->port_lock, flags);
port->writing = usbdev_get_byte_count(port->in_ep_addr) <= 0 ? 0 : 1;
spin_unlock_irqrestore(&port->port_lock, flags);
}
static void port_receive_complete(void *private)
{
struct usb_serial_port *port = (struct usb_serial_port *) private;
struct tty_struct *tty = port->tty;
usbdev_pkt_t* pkt = NULL;
int i, count;
/* while there is a packet available */
while ((count = usbdev_receive_packet(port->out_ep_addr,
&pkt)) != -ENODATA) {
if (count < 0) {
if (pkt)
kfree(pkt);
break; /* exit if error other than ENODATA */
}
dbg(__FUNCTION__ ": port %d, ep%d, size=%d",
port->number, port->out_ep_addr, count);
for (i = 0; i < count; i++) {
/* if we insert more than TTY_FLIPBUF_SIZE characters,
we drop them. */
if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
tty_flip_buffer_push(tty);
}
/* this doesn't actually push the data through
unless tty->low_latency is set */
tty_insert_flip_char(tty, pkt->payload[i], 0);
}
tty_flip_buffer_push(tty);
kfree(pkt); /* make sure we free the packet */
}
}
static struct tty_driver serial_tty_driver = {
magic:TTY_DRIVER_MAGIC,
driver_name:"usbfn-tty",
name:"usb/ttsdev/%d",
major:SERIAL_TTY_MAJOR,
minor_start:0,
num:NUM_PORTS,
type:TTY_DRIVER_TYPE_SERIAL,
subtype:SERIAL_TYPE_NORMAL,
flags:TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS,
refcount:&serial_refcount,
table:serial_tty,
termios:serial_termios,
termios_locked:serial_termios_locked,
open:serial_open,
close:serial_close,
write:serial_write,
write_room:serial_write_room,
ioctl:serial_ioctl,
set_termios:serial_set_termios,
throttle:serial_throttle,
unthrottle:serial_unthrottle,
break_ctl:serial_break,
chars_in_buffer:serial_chars_in_buffer,
};
void usbfn_tty_exit(void)
{
int i;
/* kill the device layer */
usbdev_exit();
for (i=0; i < NUM_PORTS; i++) {
tty_unregister_devfs(&serial_tty_driver, i);
info("usb serial converter now disconnected from ttyUSBdev%d",
i);
}
tty_unregister_driver(&serial_tty_driver);
if (usbtty.str_desc_buf)
kfree(usbtty.str_desc_buf);
}
int usbfn_tty_init(void)
{
int ret = 0, i, str_desc_len;
/* register the tty driver */
serial_tty_driver.init_termios = tty_std_termios;
serial_tty_driver.init_termios.c_cflag =
B9600 | CS8 | CREAD | HUPCL | CLOCAL;
if (tty_register_driver(&serial_tty_driver)) {
err(__FUNCTION__ ": failed to register tty driver");
ret = -ENXIO;
goto out;
}
/*
* initialize pointers to descriptors
*/
usbtty.dev_desc = &dev_desc;
usbtty.config_desc = &config_desc;
usbtty.if_desc = &if_desc;
/*
* initialize the string descriptors
*/
/* alloc buffer big enough for all string descriptors */
str_desc_len = string_desc0.bLength;
for (i = 0; i < 5; i++)
str_desc_len += 2 + 2 * strlen(strings[i]);
usbtty.str_desc_buf = (void *) kmalloc(str_desc_len, GFP_KERNEL);
if (!usbtty.str_desc_buf) {
err(__FUNCTION__ ": failed to alloc string descriptors");
ret = -ENOMEM;
goto out;
}
usbtty.str_desc[0] =
(struct usb_string_descriptor *)usbtty.str_desc_buf;
memcpy(usbtty.str_desc[0], &string_desc0, string_desc0.bLength);
usbtty.str_desc[1] = (struct usb_string_descriptor *)
(usbtty.str_desc_buf + string_desc0.bLength);
for (i = 1; i < 6; i++) {
struct usb_string_descriptor *desc = usbtty.str_desc[i];
char *str = strings[i - 1];
int j, str_len = strlen(str);
desc->bLength = 2 + 2 * str_len;
desc->bDescriptorType = USB_DT_STRING;
for (j = 0; j < str_len; j++) {
desc->wData[j] = (u16) str[j];
}
if (i < 5)
usbtty.str_desc[i + 1] =
(struct usb_string_descriptor *)
((u8 *) desc + desc->bLength);
}
/*
* start the device layer. The device layer assigns us
* our endpoint addresses
*/
if ((ret = usbdev_init(&dev_desc, &config_desc, &if_desc, ep_desc,
usbtty.str_desc, usbtty_callback, NULL))) {
err(__FUNCTION__ ": device-layer init failed");
goto out;
}
/* initialize the devfs nodes for this device and let the user
know what ports we are bound to */
for (i = 0; i < NUM_PORTS; ++i) {
struct usb_serial_port *port;
tty_register_devfs(&serial_tty_driver, 0, i);
info("usbdev serial attached to ttyUSBdev%d "
"(or devfs usb/ttsdev/%d)", i, i);
port = &usbtty.port[i];
port->number = i;
port->in_desc = &ep_desc[NUM_PORTS*i];
port->out_desc = &ep_desc[NUM_PORTS*i + 1];
port->in_ep_addr = port->in_desc->bEndpointAddress & 0x0f;
port->out_ep_addr = port->out_desc->bEndpointAddress & 0x0f;
port->send_complete_tq.routine = port_send_complete;
port->send_complete_tq.data = port;
port->receive_complete_tq.routine = port_receive_complete;
port->receive_complete_tq.data = port;
spin_lock_init(&port->port_lock);
}
out:
if (ret)
usbfn_tty_exit();
return ret;
}
/* Module information */
MODULE_AUTHOR("Steve Longerbeam, st...@mv..., www.mvista.com");
MODULE_DESCRIPTION("Au1x00 USB Device-Side Serial TTY Driver");
MODULE_LICENSE("GPL");
module_init(usbfn_tty_init);
module_exit(usbfn_tty_exit);
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Config.in,v
retrieving revision 1.35
retrieving revision 1.36
diff -u -d -r1.35 -r1.36
--- Config.in 23 Apr 2002 13:14:29 -0000 1.35
+++ Config.in 29 May 2002 00:23:16 -0000 1.36
@@ -69,6 +69,10 @@
if [ "$CONFIG_AU1000_UART" = "y" ]; then
bool ' Enable Au1000 serial console' CONFIG_AU1000_SERIAL_CONSOLE
fi
+ dep_tristate ' Au1000 USB TTY Device support' CONFIG_AU1000_USB_TTY $CONFIG_AU1000_USB_DEVICE
+ if [ "$CONFIG_AU1000_USB_TTY" != "y" ]; then
+ dep_tristate ' Au1000 USB Raw Device support' CONFIG_AU1000_USB_RAW $CONFIG_AU1000_USB_DEVICE
+ fi
bool 'TXx927 SIO support' CONFIG_TXX927_SERIAL
if [ "$CONFIG_TXX927_SERIAL" = "y" ]; then
bool 'TXx927 SIO Console support' CONFIG_TXX927_SERIAL_CONSOLE
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Makefile,v
retrieving revision 1.29
retrieving revision 1.30
diff -u -d -r1.29 -r1.30
--- Makefile 9 May 2002 17:22:35 -0000 1.29
+++ Makefile 29 May 2002 00:23:16 -0000 1.30
@@ -221,6 +221,8 @@
obj-$(CONFIG_INTEL_RNG) += i810_rng.o
obj-$(CONFIG_ITE_GPIO) += ite_gpio.o
obj-$(CONFIG_AU1000_GPIO) += au1000_gpio.o
+obj-$(CONFIG_AU1000_USB_TTY) += au1000_usbtty.o
+obj-$(CONFIG_AU1000_USB_RAW) += au1000_usbraw.o
obj-$(CONFIG_COBALT_LCD) += lcd.o
obj-$(CONFIG_QIC02_TAPE) += tpqic02.o
|
|
From: Steve L. <slo...@us...> - 2002-05-29 00:23:19
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv21710/arch/mips/au1000/common
Modified Files:
Makefile dma.c irq.c usbdev.c
Log Message:
Updates to Au1x00 USB slave support. Split into device layer and two
function-layer drivers, a TTY driver and a raw bidirectional block
driver. Only one IN/OUT block endpoint pair is working correctly
now, so both function-layer drivers have only one bidirectional port.
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/Makefile,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- Makefile 22 Apr 2002 17:45:00 -0000 1.9
+++ Makefile 29 May 2002 00:23:16 -0000 1.10
@@ -19,12 +19,12 @@
O_TARGET := au1000.o
-export-objs = prom.o serial.o clocks.o power.o
+export-objs = prom.o serial.o clocks.o power.o usbdev.o
-obj-y := prom.o int-handler.o dma.o irq.o puts.o time.o reset.o clocks.o power.o
+obj-y := prom.o int-handler.o dma.o irq.o puts.o time.o reset.o \
+ clocks.o power.o usbdev.o
obj-$(CONFIG_AU1000_UART) += serial.o
-obj-$(CONFIG_AU1000_USB_DEVICE) += usbdev.o
obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
obj-$(CONFIG_RTC) += rtc.o
Index: dma.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/dma.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- dma.c 1 May 2002 18:00:29 -0000 1.9
+++ dma.c 29 May 2002 00:23:16 -0000 1.10
@@ -104,9 +104,8 @@
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
if ((chan = get_dma_chan(i)) != NULL) {
- len +=
- sprintf(buf + len, "%2d: %s\n", i,
- chan->dev_str);
+ len += sprintf(buf + len, "%2d: %s\n",
+ i, chan->dev_str);
}
}
@@ -150,11 +149,15 @@
/*
* Finds a free channel, and binds the requested device to it.
* Returns the allocated channel number, or negative on error.
+ * Requests the DMA done IRQ if irqhandler != NULL.
*/
-int request_au1000_dma(int dev_id, const char *dev_str)
+int request_au1000_dma(int dev_id, const char *dev_str,
+ void (*irqhandler)(int, void *, struct pt_regs *),
+ unsigned long irqflags,
+ void *irq_dev_id)
{
struct dma_chan *chan;
- int i;
+ int i, ret;
if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
return -EINVAL;
@@ -168,14 +171,30 @@
chan = &au1000_dma_table[i];
+ if (irqhandler) {
+ chan->irq = AU1000_DMA_INT_BASE + i;
+ chan->irq_dev = irq_dev_id;
+ if ((ret = request_irq(chan->irq, irqhandler, irqflags,
+ dev_str, chan->irq_dev))) {
+ chan->irq = 0;
+ chan->irq_dev = NULL;
+ return ret;
+ }
+ } else {
+ chan->irq = 0;
+ chan->irq_dev = NULL;
+ }
+
// fill it in
chan->io = DMA_CHANNEL_BASE + i * DMA_CHANNEL_LEN;
- chan->irq = AU1000_DMA_INT_BASE + i;
chan->dev_id = dev_id;
chan->dev_str = dev_str;
chan->fifo_addr = dma_dev_table[dev_id].fifo_addr;
chan->mode = dma_dev_table[dev_id].dma_mode;
+ /* initialize the channel before returning */
+ init_dma(i);
+
return i;
}
@@ -189,6 +208,10 @@
}
disable_dma(dmanr);
-
+ if (chan->irq)
+ free_irq(chan->irq, chan->irq_dev);
+
+ chan->irq = 0;
+ chan->irq_dev = NULL;
chan->dev_id = -1;
-} /* free_dma */
+}
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/irq.c,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -d -r1.18 -r1.19
--- irq.c 1 May 2002 18:00:29 -0000 1.18
+++ irq.c 29 May 2002 00:23:16 -0000 1.19
@@ -463,19 +463,18 @@
break;
case AU1000_ACSYNC_INT:
case AU1000_AC97C_INT:
- case AU1000_USB_DEV_REQ_INT:
- case AU1000_USB_DEV_SUS_INT:
case AU1000_TOY_INT:
case AU1000_TOY_MATCH0_INT:
case AU1000_TOY_MATCH1_INT:
+ case AU1000_USB_DEV_SUS_INT:
+ case AU1000_USB_DEV_REQ_INT:
case AU1000_RTC_INT:
case AU1000_RTC_MATCH0_INT:
case AU1000_RTC_MATCH1_INT:
case AU1000_RTC_MATCH2_INT:
setup_local_irq(i, INTC_INT_RISE_EDGE, 0);
- irq_desc[i].handler = &rise_edge_irq_type;
- break;
-
+ irq_desc[i].handler = &rise_edge_irq_type;
+ break;
// Careful if you change match 2 request!
// The interrupt handler is called directly
// from the low level dispatch code.
@@ -515,6 +514,17 @@
if (!intc0_req0) return;
+ /*
+ * Because of the tight timing of SETUP token to reply
+ * transactions, the USB devices-side packet complete
+ * interrupt needs the highest priority.
+ */
+ if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
+ intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
+ do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
+ return;
+ }
+
for (i=0; i<32; i++) {
if ((intc0_req0 & (1<<i))) {
intc0_req0 &= ~(1<<i);
Index: usbdev.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/usbdev.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- usbdev.c 1 May 2002 18:00:29 -0000 1.10
+++ usbdev.c 29 May 2002 00:23:16 -0000 1.11
@@ -1,8 +1,8 @@
/*
* BRIEF MODULE DESCRIPTION
- * Au1000 USB Device-Side Serial TTY Driver
+ * Au1000 USB Device-Side (device layer)
*
- * Copyright 2001 MontaVista Software Inc.
+ * Copyright 2001-2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* st...@mv... or so...@mv...
*
@@ -37,9 +37,6 @@
[...2770 lines suppressed...]
- return 0;
-
- err_out:
- usbdev_serial_exit();
- return -1;
+ out:
+ if (ret)
+ usbdev_exit();
+ return ret;
}
-
-module_init(usbdev_serial_init);
-module_exit(usbdev_serial_exit);
+EXPORT_SYMBOL(usbdev_init);
+EXPORT_SYMBOL(usbdev_exit);
+EXPORT_SYMBOL(usbdev_alloc_packet);
+EXPORT_SYMBOL(usbdev_receive_packet);
+EXPORT_SYMBOL(usbdev_send_packet);
+EXPORT_SYMBOL(usbdev_get_byte_count);
|
|
From: Steve L. <slo...@us...> - 2002-05-29 00:23:19
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv21710/arch/mips
Modified Files:
config.in
Log Message:
Updates to Au1x00 USB slave support. Split into device layer and two
function-layer drivers, a TTY driver and a raw bidirectional block
driver. Only one IN/OUT block endpoint pair is working correctly
now, so both function-layer drivers have only one bidirectional port.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.99
retrieving revision 1.100
diff -u -d -r1.99 -r1.100
--- config.in 28 May 2002 20:31:28 -0000 1.99
+++ config.in 29 May 2002 00:23:16 -0000 1.100
@@ -391,6 +391,7 @@
define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PC_KEYB y
define_bool CONFIG_SWAP_IO_SPACE y
+ define_bool CONFIG_AU1000_USB_DEVICE y
fi
if [ "$CONFIG_MIPS_PB1500" = "y" ]; then
define_bool CONFIG_MIPS_AU1000 y
@@ -400,6 +401,7 @@
define_bool CONFIG_PCI_AUTO y
define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PC_KEYB y
+ define_bool CONFIG_AU1000_USB_DEVICE y
fi
if [ "$CONFIG_MIPS_PB1100" = "y" ]; then
define_bool CONFIG_MIPS_AU1000 y
@@ -410,6 +412,7 @@
define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PC_KEYB y
define_bool CONFIG_SWAP_IO_SPACE y
+ define_bool CONFIG_AU1000_USB_DEVICE y
fi
if [ "$CONFIG_IDT_79S334" = "y" ]; then
define_bool CONFIG_MIPS_RC32334 y
|
|
From: Paul M. <le...@us...> - 2002-05-28 21:03:35
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv7798/arch/mips/mm
Modified Files:
c-r4k.c
Log Message:
Further OSS syncing.
Index: c-r4k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-r4k.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- c-r4k.c 21 Apr 2002 06:43:20 -0000 1.8
+++ c-r4k.c 28 May 2002 21:03:31 -0000 1.9
@@ -27,6 +27,7 @@
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
+#include <asm/war.h>
/* Primary cache parameters. */
static int icache_size, dcache_size; /* Size in bytes */
@@ -1001,11 +1002,16 @@
static void r4k_flush_page_to_ram_d32_r4600(struct page *page)
{
+#ifdef R4600_V1_HIT_DCACHE_WAR
unsigned long flags;
- __save_and_cli(flags); /* For R4600 v1.7 bug. */
+ __save_and_cli(flags);
+ __asm__ __volatile__("nop;nop;nop;nop");
+#endif
blast_dcache32_page((unsigned long)page_address(page));
+#ifdef R4600_V1_HIT_DCACHE_WAR
__restore_flags(flags);
+#endif
}
static void
@@ -1057,9 +1063,11 @@
if (size >= dcache_size) {
flush_cache_all();
} else {
- /* Workaround for R4600 bug. See comment above. */
+#ifdef R4600_V2_HIT_CACHEOP_WAR
+ /* Workaround for R4600 bug. See comment in <asm/war>. */
__save_and_cli(flags);
*(volatile unsigned long *)KSEG1;
+#endif
a = addr & ~(dc_lsize - 1);
end = (addr + size) & ~(dc_lsize - 1);
@@ -1068,7 +1076,9 @@
if (a == end) break;
a += dc_lsize;
}
+#ifdef R4600_V2_HIT_CACHEOP_WAR
__restore_flags(flags);
+#endif
}
bc_wback_inv(addr, size);
}
@@ -1101,9 +1111,11 @@
if (size >= dcache_size) {
flush_cache_all();
} else {
+#ifdef R4600_V2_HIT_CACHEOP_WAR
/* Workaround for R4600 bug. See comment above. */
__save_and_cli(flags);
*(volatile unsigned long *)KSEG1;
+#endif
a = addr & ~(dc_lsize - 1);
end = (addr + size) & ~(dc_lsize - 1);
@@ -1112,7 +1124,9 @@
if (a == end) break;
a += dc_lsize;
}
+#ifdef R4600_V2_HIT_CACHEOP_WAR
__restore_flags(flags);
+#endif
}
bc_inv(addr, size);
@@ -1152,24 +1166,36 @@
*/
static void r4k_flush_cache_sigtramp(unsigned long addr)
{
- __asm__ __volatile__("nop;nop;nop;nop"); /* R4600 V1.7 */
+#ifdef R4600_V1_HIT_DCACHE_WAR
+ unsigned long flags;
+
+ __save_and_cli(flags);
+ __asm__ __volatile__("nop;nop;nop;nop");
+#endif
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
protected_flush_icache_line(addr & ~(ic_lsize - 1));
+#ifdef R4600_V1_HIT_DCACHE_WAR
+ __restore_flags(flags);
+#endif
}
static void r4600v20k_flush_cache_sigtramp(unsigned long addr)
{
unsigned int flags;
+#ifdef R4600_V2_HIT_CACHEOP_WAR
__save_and_cli(flags);
/* Clear internal cache refill buffer */
*(volatile unsigned int *)KSEG1;
+#endif
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
protected_flush_icache_line(addr & ~(ic_lsize - 1));
+#ifdef R4600_V2_HIT_CACHEOP_WAR
__restore_flags(flags);
+#endif
}
/* Detect and size the various r4k caches. */
|
|
From: Paul M. <le...@us...> - 2002-05-28 20:57:31
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv3127/arch/mips/kernel
Modified Files:
setup.c
Log Message:
Further OSS syncing..
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.62
retrieving revision 1.63
diff -u -d -r1.62 -r1.63
--- setup.c 16 May 2002 18:40:06 -0000 1.62
+++ setup.c 28 May 2002 20:57:27 -0000 1.63
@@ -149,9 +149,12 @@
case CPU_NEVADA:
case CPU_RM7000:
case CPU_TX49XX:
-#ifdef CONFIG_MIPS_RC32355
case CPU_RC32300:
-#endif
+ case CPU_4KC:
+ case CPU_4KEC:
+ case CPU_4KSC:
+ case CPU_5KC:
+/* case CPU_20KC:*/
cpu_wait = r4k_wait;
printk(" available.\n");
break;
@@ -241,9 +244,26 @@
static inline void cpu_probe(void)
{
#ifdef CONFIG_CPU_MIPS32
+ unsigned long config0 = read_32bit_cp0_register(CP0_CONFIG);
unsigned long config1;
-#endif
+ if (config0 & (1 << 31)) {
+ /* MIPS32 compliant CPU. Read Config 1 register. */
+ mips_cpu.isa_level = MIPS_CPU_ISA_M32;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
+ MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC;
+ config1 = read_mips32_cp0_config1();
+ if (config1 & (1 << 3))
+ mips_cpu.options |= MIPS_CPU_WATCH;
+ if (config1 & (1 << 2))
+ mips_cpu.options |= MIPS_CPU_MIPS16;
+ if (config1 & (1 << 1))
+ mips_cpu.options |= MIPS_CPU_EJTAG;
+ if (config1 & 1)
+ mips_cpu.options |= MIPS_CPU_FPU;
+ mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
+ }
+#endif
mips_cpu.processor_id = read_32bit_cp0_register(CP0_PRID);
switch (mips_cpu.processor_id & 0xff0000) {
case PRID_COMP_LEGACY:
@@ -251,7 +271,7 @@
case PRID_IMP_R2000:
mips_cpu.cputype = CPU_R2000;
mips_cpu.isa_level = MIPS_CPU_ISA_I;
- mips_cpu.options = MIPS_CPU_TLB;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
if (cpu_has_fpu())
mips_cpu.options |= MIPS_CPU_FPU;
mips_cpu.tlbsize = 64;
@@ -265,7 +285,7 @@
else
mips_cpu.cputype = CPU_R3000;
mips_cpu.isa_level = MIPS_CPU_ISA_I;
- mips_cpu.options = MIPS_CPU_TLB;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
if (cpu_has_fpu())
mips_cpu.options |= MIPS_CPU_FPU;
mips_cpu.tlbsize = 64;
@@ -327,7 +347,7 @@
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
MIPS_CPU_32FPR | MIPS_CPU_WATCH |
- MIPS_CPU_VCE | MIPS_CPU_FPUEX;
+ MIPS_CPU_VCE;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_VR41XX:
@@ -344,14 +364,13 @@
mips_cpu.cputype = CPU_R4300;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR;
mips_cpu.tlbsize = 32;
break;
case PRID_IMP_R4600:
mips_cpu.cputype = CPU_R4600;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
mips_cpu.tlbsize = 48;
break;
#if 0
@@ -364,8 +383,7 @@
*/
mips_cpu.cputype = CPU_R4650;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
- mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
+ mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU;
mips_cpu.tlbsize = 48;
break;
#endif
@@ -399,14 +417,14 @@
mips_cpu.cputype = CPU_R4700;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_TX49:
mips_cpu.cputype = CPU_TX49XX;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 4;
mips_cpu.dcache.ways = 4;
@@ -415,31 +433,28 @@
mips_cpu.cputype = CPU_R5000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_R5432:
mips_cpu.cputype = CPU_R5432;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_WATCH |
- MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR | MIPS_CPU_WATCH;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_R5500:
mips_cpu.cputype = CPU_R5500;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_WATCH |
- MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR | MIPS_CPU_WATCH;
mips_cpu.tlbsize = 48;
break;
case PRID_IMP_NEVADA:
mips_cpu.cputype = CPU_NEVADA;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_DIVEC |
- MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR | MIPS_CPU_DIVEC;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
@@ -448,33 +463,28 @@
mips_cpu.cputype = CPU_R5900;
mips_cpu.isa_level = MIPS_CPU_ISA_III;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU |
- MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
- MIPS_CPU_FPUEX;
+ MIPS_CPU_COUNTER | MIPS_CPU_DIVEC;
mips_cpu.tlbsize = 48;
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
break;
-
-
case PRID_IMP_R6000:
mips_cpu.cputype = CPU_R6000;
mips_cpu.isa_level = MIPS_CPU_ISA_II;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU;
mips_cpu.tlbsize = 32;
break;
case PRID_IMP_R6000A:
mips_cpu.cputype = CPU_R6000A;
mips_cpu.isa_level = MIPS_CPU_ISA_II;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU;
mips_cpu.tlbsize = 32;
break;
case PRID_IMP_RM7000:
mips_cpu.cputype = CPU_RM7000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU |
- MIPS_CPU_32FPR | MIPS_CPU_FPUEX;
+ MIPS_CPU_32FPR;
/*
* Undocumented RM7000: Bit 29 in the info register of
* the RM7000 v2.0 indicates if the TLB has 48 or 64
@@ -489,8 +499,7 @@
mips_cpu.cputype = CPU_R8000;
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_FPU | MIPS_CPU_32FPR |
- MIPS_CPU_FPUEX;
+ MIPS_CPU_FPU | MIPS_CPU_32FPR;
mips_cpu.tlbsize = 384; /* has wierd TLB: 3-way x 128 */
break;
case PRID_IMP_R10000:
@@ -498,8 +507,7 @@
mips_cpu.isa_level = MIPS_CPU_ISA_IV;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
MIPS_CPU_FPU | MIPS_CPU_32FPR |
- MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
- MIPS_CPU_FPUEX;
+ MIPS_CPU_COUNTER | MIPS_CPU_WATCH;
mips_cpu.tlbsize = 64;
break;
case PRID_IMP_RC32334:
@@ -523,49 +531,20 @@
switch (mips_cpu.processor_id & 0xff00) {
case PRID_IMP_4KC:
mips_cpu.cputype = CPU_4KC;
- goto cpu_4kc;
+ break;
case PRID_IMP_4KEC:
mips_cpu.cputype = CPU_4KEC;
- goto cpu_4kc;
+ break;
case PRID_IMP_4KSC:
mips_cpu.cputype = CPU_4KSC;
-cpu_4kc:
- /*
- * Why do we set all these options by default, THEN
- * query them??
- */
- mips_cpu.isa_level = MIPS_CPU_ISA_M32;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
- MIPS_CPU_DIVEC | MIPS_CPU_WATCH |
- MIPS_CPU_MCHECK;
- config1 = read_mips32_cp0_config1();
- if (config1 & (1 << 3))
- mips_cpu.options |= MIPS_CPU_WATCH;
- if (config1 & (1 << 2))
- mips_cpu.options |= MIPS_CPU_MIPS16;
- if (config1 & 1)
- mips_cpu.options |= MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
- mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
break;
case PRID_IMP_5KC:
mips_cpu.cputype = CPU_5KC;
mips_cpu.isa_level = MIPS_CPU_ISA_M64;
- /* See comment above about querying options */
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
- MIPS_CPU_DIVEC | MIPS_CPU_WATCH |
- MIPS_CPU_MCHECK;
- config1 = read_mips32_cp0_config1();
- if (config1 & (1 << 3))
- mips_cpu.options |= MIPS_CPU_WATCH;
- if (config1 & (1 << 2))
- mips_cpu.options |= MIPS_CPU_MIPS16;
- if (config1 & 1)
- mips_cpu.options |= MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
- mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
+ break;
+ case PRID_IMP_20KC:
+ mips_cpu.cputype = CPU_20KC;
+ mips_cpu.isa_level = MIPS_CPU_ISA_M64;
break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
@@ -591,18 +570,6 @@
break;
}
mips_cpu.isa_level = MIPS_CPU_ISA_M32;
- mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_4KTLB | MIPS_CPU_COUNTER |
- MIPS_CPU_DIVEC | MIPS_CPU_WATCH;
- config1 = read_mips32_cp0_config1();
- if (config1 & (1 << 3))
- mips_cpu.options |= MIPS_CPU_WATCH;
- if (config1 & (1 << 2))
- mips_cpu.options |= MIPS_CPU_MIPS16;
- if (config1 & 1)
- mips_cpu.options |= MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
- mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT;
break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
@@ -620,8 +587,7 @@
MIPS_CPU_MCHECK;
#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
/* FPU in pass1 is known to have issues. */
- mips_cpu.options |= MIPS_CPU_FPU |
- MIPS_CPU_FPUEX;
+ mips_cpu.options |= MIPS_CPU_FPU;
#endif
break;
default:
@@ -680,11 +646,9 @@
*/
loadmmu();
- /* Disable coprocessors and set FPU for 16 FPRs */
- s = read_32bit_cp0_register(CP0_STATUS);
- s &= ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR);
- s |= ST0_CU0;
- write_32bit_cp0_register(CP0_STATUS, s);
+ /* Disable coprocessors and set FPU for 16/32 FPR register model */
+ clear_cp0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR);
+ set_cp0_status(ST0_CU0);
start_kernel();
}
@@ -712,7 +676,8 @@
for (i = 0; i < boot_mem_map.nr_map; i++) {
printk(" memory: %08Lx @ %08Lx ",
(u64) boot_mem_map.map[i].size,
- (u64) boot_mem_map.map[i].addr);
+ (u64) boot_mem_map.map[i].addr);
+
switch (boot_mem_map.map[i].type) {
case BOOT_MEM_RAM:
printk("(usable)\n");
|
|
From: Paul M. <le...@us...> - 2002-05-28 20:31:31
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv13848/arch/mips
Modified Files:
config.in
Log Message:
Partial sync with OSS.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.98
retrieving revision 1.99
diff -u -d -r1.98 -r1.99
--- config.in 9 May 2002 17:22:34 -0000 1.98
+++ config.in 28 May 2002 20:31:28 -0000 1.99
@@ -132,6 +132,8 @@
if [ "$CONFIG_SIBYTE_SB1250" = "y" ]; then
define_bool CONFIG_NEW_IRQ y
+ define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_DUMMY_KEYB y
define_bool CONFIG_SWAP_IO_SPACE y
fi
@@ -195,6 +197,7 @@
define_bool CONFIG_NEW_TIME_C y
define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_SWAP_IO_SPACE y
+ define_bool CONFIG_PC_KEYB y
fi
if [ "$CONFIG_MOMENCO_OCELOT" = "y" ]; then
define_bool CONFIG_PCI y
@@ -575,10 +578,12 @@
if [ "$CONFIG_CPU_MIPS32" = "y" ]; then
define_bool CONFIG_CPU_HAS_PREFETCH y
+ bool ' Support for Virtual Tagged I-cache' CONFIG_VTAG_ICACHE
fi
if [ "$CONFIG_CPU_MIPS64" = "y" ]; then
define_bool CONFIG_CPU_HAS_PREFETCH y
+ bool ' Support for Virtual Tagged I-cache' CONFIG_VTAG_ICACHE
fi
if [ "$CONFIG_CPU_RM7000" = "y" ]; then
|
|
From: Paul M. <le...@us...> - 2002-05-28 20:26:08
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv7651/arch/mips/configs Modified Files: defconfig-sb1250-swarm Log Message: Partial sync with OSS. Index: defconfig-sb1250-swarm =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-sb1250-swarm,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- defconfig-sb1250-swarm 18 Mar 2002 23:32:37 -0000 1.7 +++ defconfig-sb1250-swarm 28 May 2002 20:25:35 -0000 1.8 @@ -134,8 +134,7 @@ # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=9220 +# CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # @@ -161,10 +160,7 @@ CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set +# CONFIG_IP_PNP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set # CONFIG_ARPD is not set @@ -206,9 +202,49 @@ # # ATA/IDE/MFM/RLL support # -# CONFIG_IDE is not set -# CONFIG_BLK_DEV_IDE_MODES is not set +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD_IDE is not set # CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set +# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set +# CONFIG_BLK_DEV_IDEDISK_IBM is not set +# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set +# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set +# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set +# CONFIG_BLK_DEV_IDEDISK_WD is not set +# CONFIG_BLK_DEV_COMMERIAL is not set +# CONFIG_BLK_DEV_TIVO is not set +# CONFIG_BLK_DEV_IDECS is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_BLK_DEV_CMD640 is not set +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set +# CONFIG_BLK_DEV_ISAPNP is not set +CONFIG_BLK_DEV_IDE_SWARM=y +# CONFIG_IDE_CHIPSETS is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_DMA_NONPCI is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_ATARAID is not set +# CONFIG_BLK_DEV_ATARAID_PDC is not set +# CONFIG_BLK_DEV_ATARAID_HPT is not set # # SCSI support @@ -342,7 +378,8 @@ CONFIG_SERIAL_CONSOLE=y CONFIG_SB1250_DUART_OUTPUT_BUF_SIZE=1024 # CONFIG_SIBYTE_SB1250_DUART_NO_PORT_1 is not set -# CONFIG_UNIX98_PTYS is not set +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 # # I2C support @@ -406,8 +443,8 @@ # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set +CONFIG_EXT3_FS=y +CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set # CONFIG_FAT_FS is not set # CONFIG_MSDOS_FS is not set @@ -417,7 +454,7 @@ # CONFIG_JFFS_FS is not set # CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set +CONFIG_TMPFS=y # CONFIG_RAMFS is not set # CONFIG_ISO9660_FS is not set # CONFIG_JOLIET is not set @@ -431,11 +468,11 @@ # CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set -# CONFIG_DEVPTS_FS is not set +CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UDF_FS is not set # CONFIG_UDF_RW is not set @@ -449,7 +486,7 @@ # CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y +# CONFIG_ROOT_NFS is not set # CONFIG_NFSD is not set # CONFIG_NFSD_V3 is not set CONFIG_SUNRPC=y |
|
From: Paul M. <le...@us...> - 2002-05-28 20:26:07
|
Update of /cvsroot/linux-mips/linux/arch/mips/cobalt
In directory usw-pr-cvs1:/tmp/cvs-serv7651/arch/mips/cobalt
Modified Files:
irq.c pci.c
Log Message:
Partial sync with OSS.
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/irq.c,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- irq.c 21 Apr 2002 20:56:23 -0000 1.14
+++ irq.c 28 May 2002 20:25:34 -0000 1.15
@@ -64,7 +64,7 @@
static unsigned short irqnr_to_type[COBALT_IRQS] =
{ CPUINT_LINE(0), NOINT_LINE, VIAINT_LINE, NOINT_LINE,
CPUINT_LINE(1), NOINT_LINE, NOINT_LINE, CPUINT_LINE(3),
- VIAINT_LINE, CPUINT_LINE(5), NOINT_LINE, NOINT_LINE,
+ VIAINT_LINE, VIAINT_LINE, NOINT_LINE, NOINT_LINE,
NOINT_LINE, CPUINT_LINE(2), VIAINT_LINE, VIAINT_LINE };
/*
@@ -98,7 +98,7 @@
#define shutdown_cpu_irq disable_cpu_irq
#define mask_and_ack_cpu_irq disable_cpu_irq
-
+
static void end_cpu_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -185,7 +185,7 @@
int i;
/* Initialise all of the IRQ descriptors */
- init_generic_irq();
+ init_generic_irq();
/* Map the irqnr to the type int we have */
for (i=0; i < COBALT_IRQS; i++) {
Index: pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/pci.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- pci.c 21 Apr 2002 20:56:23 -0000 1.8
+++ pci.c 28 May 2002 20:25:34 -0000 1.9
@@ -19,116 +19,122 @@
#include <asm/cobalt/cobalt.h>
#include <asm/pci.h>
#include <asm/io.h>
-
+
#ifdef CONFIG_PCI
-static void qube_expansion_slot_bist(void)
+static void qube_expansion_slot_bist(struct pci_dev *dev)
{
- unsigned char ctrl;
- int timeout = 100000;
+ unsigned char ctrl;
+ int timeout = 100000;
- pcibios_read_config_byte(0, (0x0a<<3), PCI_BIST, &ctrl);
- if(!(ctrl & PCI_BIST_CAPABLE))
- return;
+ pci_read_config_byte(dev, PCI_BIST, &ctrl);
+ if(!(ctrl & PCI_BIST_CAPABLE))
+ return;
- pcibios_write_config_byte(0, (0x0a<<3), PCI_BIST, ctrl|PCI_BIST_START);
- do {
- pcibios_read_config_byte(0, (0x0a<<3), PCI_BIST, &ctrl);
- if(!(ctrl & PCI_BIST_START))
- break;
- } while(--timeout > 0);
- if((timeout <= 0) || (ctrl & PCI_BIST_CODE_MASK))
- printk("PCI: Expansion slot card failed BIST with code %x\n",
- (ctrl & PCI_BIST_CODE_MASK));
+ pci_write_config_byte(dev, PCI_BIST, ctrl|PCI_BIST_START);
+ do {
+ pci_read_config_byte(dev, PCI_BIST, &ctrl);
+ if(!(ctrl & PCI_BIST_START))
+ break;
+ } while(--timeout > 0);
+ if((timeout <= 0) || (ctrl & PCI_BIST_CODE_MASK))
+ printk("PCI: Expansion slot card failed BIST with code %x\n",
+ (ctrl & PCI_BIST_CODE_MASK));
}
-static void qube_expansion_slot_fixup(void)
+static void qube_expansion_slot_fixup(struct pci_dev *dev)
{
unsigned short pci_cmd;
- unsigned long ioaddr_base = 0x108000; /* It's magic, ask Doug. */
- unsigned long memaddr_base = 0x12000000;
- int i;
+ unsigned long ioaddr_base = 0x10108000; /* It's magic, ask Doug. */
+ unsigned long memaddr_base = 0x12000000;
+ int i;
- /* Enable bits in COMMAND so driver can talk to it. */
- pcibios_read_config_word(0, (0x0a<<3), PCI_COMMAND, &pci_cmd);
- pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- pcibios_write_config_word(0, (0x0a<<3), PCI_COMMAND, pci_cmd);
+ /* Enable bits in COMMAND so driver can talk to it. */
+ pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
+ pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
- /* Give it a working IRQ. */
- pcibios_write_config_byte(0, (0x0a<<3), PCI_INTERRUPT_LINE, 9);
+ /* Give it a working IRQ. */
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_QUBE_SLOT_IRQ);
- /* Fixup base addresses, we only support I/O at the moment. */
- for(i = 0; i <= 5; i++) {
- unsigned int regaddr = (PCI_BASE_ADDRESS_0 + (i * 4));
- unsigned int rval, mask, size, alignme, aspace;
- unsigned long *basep = &ioaddr_base;
+ /* Fixup base addresses, we only support I/O at the moment. */
+ for(i = 0; i <= 5; i++) {
+ unsigned int regaddr = (PCI_BASE_ADDRESS_0 + (i * 4));
+ unsigned int rval, mask, size, alignme, aspace;
+ unsigned long *basep = &ioaddr_base;
- /* Check type first, punt if non-IO. */
- pcibios_read_config_dword(0, (0x0a<<3), regaddr, &rval);
- aspace = (rval & PCI_BASE_ADDRESS_SPACE);
- if(aspace != PCI_BASE_ADDRESS_SPACE_IO)
- basep = &memaddr_base;
+ /* Check type first, punt if non-IO. */
+ pci_read_config_dword(dev, regaddr, &rval);
+ aspace = (rval & PCI_BASE_ADDRESS_SPACE);
+ if(aspace != PCI_BASE_ADDRESS_SPACE_IO)
+ basep = &memaddr_base;
- /* Figure out how much it wants, if anything. */
- pcibios_write_config_dword(0, (0x0a<<3), regaddr, 0xffffffff);
- pcibios_read_config_dword(0, (0x0a<<3), regaddr, &rval);
+ /* Figure out how much it wants, if anything. */
+ pci_write_config_dword(dev, regaddr, 0xffffffff);
+ pci_read_config_dword(dev, regaddr, &rval);
- /* Unused? */
- if(rval == 0)
- continue;
+ /* Unused? */
+ if(rval == 0)
+ continue;
- rval &= PCI_BASE_ADDRESS_IO_MASK;
- mask = (~rval << 1) | 0x1;
- size = (mask & rval) & 0xffffffff;
- alignme = size;
- if(alignme < 0x400)
- alignme = 0x400;
- rval = ((*basep + (alignme - 1)) & ~(alignme - 1));
- *basep = (rval + size);
- pcibios_write_config_dword(0, (0x0a<<3), regaddr, rval | aspace);
- }
- qube_expansion_slot_bist();
+ rval &= PCI_BASE_ADDRESS_IO_MASK;
+ mask = (~rval << 1) | 0x1;
+ size = (mask & rval) & 0xffffffff;
+ alignme = size;
+ if(alignme < 0x400)
+ alignme = 0x400;
+ rval = ((*basep + (alignme - 1)) & ~(alignme - 1));
+ *basep = (rval + size);
+ pci_write_config_dword(dev, regaddr, rval | aspace);
+ dev->resource[i].start = rval;
+ dev->resource[i].end = *basep - 1;
+ if(aspace == PCI_BASE_ADDRESS_SPACE_IO) {
+ dev->resource[i].start -= 0x10000000;
+ dev->resource[i].end -= 0x10000000;
+ }
+ }
+ qube_expansion_slot_bist(dev);
}
static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
{
- unsigned short cfgword;
- unsigned char lt;
+ unsigned short cfgword;
+ unsigned char lt;
- /* Enable Bus Mastering and fast back to back. */
- pci_read_config_word(dev, PCI_COMMAND, &cfgword);
- cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
- pci_write_config_word(dev, PCI_COMMAND, cfgword);
+ /* Enable Bus Mastering and fast back to back. */
+ pci_read_config_word(dev, PCI_COMMAND, &cfgword);
+ cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
+ pci_write_config_word(dev, PCI_COMMAND, cfgword);
/* Enable both ide interfaces. ROM only enables primary one. */
pci_write_config_byte(dev, 0x40, 0xb);
- /* Set latency timer to reasonable value. */
- pci_read_config_byte(dev, PCI_LATENCY_TIMER, <);
+ /* Set latency timer to reasonable value. */
+ pci_read_config_byte(dev, PCI_LATENCY_TIMER, <);
if(lt < 64)
- pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
}
static void qube_raq_tulip_fixup(struct pci_dev *dev)
{
- unsigned short pci_cmd;
- extern int cobalt_is_raq;
+ unsigned short pci_cmd;
+ extern int cobalt_is_raq;
- /* Fixup the first tulip located at device PCICONF_ETH0 */
+ /* Fixup the first tulip located at device PCICONF_ETH0 */
if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH0) {
- /*
- * Now tell the Ethernet device that we expect an interrupt at
- * IRQ 13 and not the default 189.
- *
- * The IRQ of the first Tulip is different on Qube and RaQ
- */
+ /*
+ * Now tell the Ethernet device that we expect an interrupt at
+ * IRQ 13 and not the default 189.
+ *
+ * The IRQ of the first Tulip is different on Qube and RaQ
+ */
if (!cobalt_is_raq) {
- /* All Qube's route this the same way. */
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+ /* All Qube's route this the same way. */
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
COBALT_QUBE_ETH_IRQ);
- } else {
- /* Setup the first Tulip on the RAQ */
+ } else {
+ /* Setup the first Tulip on the RAQ */
pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
COBALT_RAQ_ETH0_IRQ);
}
@@ -138,126 +144,127 @@
dev->resource[1].start = 0xe9ffec00;
dev->resource[1].end = 0xe9ffefff;
pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0xe9ffec00);
- }
- /* Fixup the second tulip located at device PCICONF_ETH1 */
+ }
+ /* Fixup the second tulip located at device PCICONF_ETH1 */
} else if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH1) {
- /* Enable the second Tulip device. */
- pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
- pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MASTER);
- pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
+ /* Enable the second Tulip device. */
+ pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
+ pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MASTER);
+ pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
- /* Give it it's IRQ. */
+ /* Give it it's IRQ. */
pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
COBALT_RAQ_ETH1_IRQ);
- /* And finally, a usable I/O space allocation, right after what
- * the first Tulip uses.
- */
+ /* And finally, a usable I/O space allocation, right after what
+ * the first Tulip uses.
+ */
dev->resource[0].start = 0x101000;
dev->resource[0].end = 0x10107f;
- }
+ }
}
static void qube_raq_scsi_fixup(struct pci_dev *dev)
{
- unsigned short pci_cmd;
- extern int cobalt_is_raq;
+ unsigned short pci_cmd;
+ extern int cobalt_is_raq;
/*
* Tell the SCSI device that we expect an interrupt at
* IRQ 7 and not the default 0.
*/
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_SCSI_IRQ);
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_SCSI_IRQ);
- if (cobalt_is_raq) {
+ if (cobalt_is_raq) {
- /* Enable the device. */
- pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
+ /* Enable the device. */
+ pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
| PCI_COMMAND_INVALIDATE);
- pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
+ pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
/* Give it it's RAQ IRQ. */
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 4);
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 4);
- /* And finally, a usable I/O space allocation, right after what
- * the second Tulip uses.
- */
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x10102001);
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0x00002000);
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0x00100000);
- }
+ /* And finally, a usable I/O space allocation, right after what
+ * the second Tulip uses.
+ */
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x10102001);
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0x00002000);
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0x00100000);
+ }
}
static void qube_raq_galileo_fixup(struct pci_dev *dev)
{
- unsigned short galileo_id;
+ unsigned short galileo_id;
- /* Fix PCI latency-timer and cache-line-size values in Galileo
- * host bridge.
- */
- pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+ /* Fix PCI latency-timer and cache-line-size values in Galileo
+ * host bridge.
+ */
+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
- /* On all machines prior to Q2, we had the STOP line disconnected
- * from Galileo to VIA on PCI. The new Galileo does not function
- * correctly unless we have it connected.
- *
- * Therefore we must set the disconnect/retry cycle values to
- * something sensible when using the new Galileo.
- */
- pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
- galileo_id &= 0xff; /* mask off class info */
- if (galileo_id == 0x10) {
- /* New Galileo, assumes PCI stop line to VIA is connected. */
- *((volatile unsigned int *)0xb4000c04) = 0x00004020;
- } else if (galileo_id == 0x1 || galileo_id == 0x2) {
+ /* On all machines prior to Q2, we had the STOP line disconnected
+ * from Galileo to VIA on PCI. The new Galileo does not function
+ * correctly unless we have it connected.
+ *
+ * Therefore we must set the disconnect/retry cycle values to
+ * something sensible when using the new Galileo.
+ */
+ pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
+ galileo_id &= 0xff; /* mask off class info */
+ if (galileo_id == 0x10) {
+ /* New Galileo, assumes PCI stop line to VIA is connected. */
+ *((volatile unsigned int *)0xb4000c04) = 0x00004020;
+ } else if (galileo_id == 0x1 || galileo_id == 0x2) {
signed int timeo;
- /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
- timeo = *((volatile unsigned int *)0xb4000c04);
- /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
- *((volatile unsigned int *)0xb4000c04) = 0x0000ffff;
- }
+ /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
+ timeo = *((volatile unsigned int *)0xb4000c04);
+ /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
+ *((volatile unsigned int *)0xb4000c04) = 0x0000ffff;
+ }
}
static void
qube_pcibios_fixup(struct pci_dev *dev)
{
- unsigned int tmp;
+ if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_PCISLOT) {
+ unsigned int tmp;
- /* See if there is a device in the expansion slot, if so
- * fixup IRQ, fix base addresses, and enable master +
- * I/O + memory accesses in config space.
- */
- pcibios_read_config_dword(0, 0x0a<<3, PCI_VENDOR_ID, &tmp);
- if(tmp != 0xffffffff && tmp != 0x00000000)
- qube_expansion_slot_fixup();
+ /* See if there is a device in the expansion slot, if so
+ * discover its resources and fixup whatever we need to
+ */
+ pci_read_config_dword(dev, PCI_VENDOR_ID, &tmp);
+ if(tmp != 0xffffffff && tmp != 0x00000000)
+ qube_expansion_slot_fixup(dev);
+ }
}
struct pci_fixup pcibios_fixups[] = {
- { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, qube_raq_via_bmIDE_fixup },
- { PCI_FIXUP_HEADER, PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, qube_raq_tulip_fixup },
- { PCI_FIXUP_HEADER, PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, qube_raq_galileo_fixup },
- { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, qube_raq_scsi_fixup },
- { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, qube_pcibios_fixup }
+ { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, qube_raq_via_bmIDE_fixup },
+ { PCI_FIXUP_HEADER, PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, qube_raq_tulip_fixup },
+ { PCI_FIXUP_HEADER, PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, qube_raq_galileo_fixup },
+ { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, qube_raq_scsi_fixup },
+ { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, qube_pcibios_fixup }
};
-static __inline__ int pci_range_ck(struct pci_dev *dev)
+static __inline__ int pci_range_ck(struct pci_dev *dev)
{
- if ((dev->bus->number == 0)
- && ((PCI_SLOT (dev->devfn) == 0)
- || ((PCI_SLOT (dev->devfn) > 6)
- && (PCI_SLOT (dev->devfn) <= 12))))
- return 0; /* OK device number */
+ if ((dev->bus->number == 0)
+ && ((PCI_SLOT (dev->devfn) == 0)
+ || ((PCI_SLOT (dev->devfn) > 6)
+ && (PCI_SLOT (dev->devfn) <= 12))))
+ return 0; /* OK device number */
- return -1; /* NOT ok device number */
+ return -1; /* NOT ok device number */
}
-#define PCI_CFG_DATA ((volatile unsigned long *)0xb4000cfc)
-#define PCI_CFG_CTRL ((volatile unsigned long *)0xb4000cf8)
+#define PCI_CFG_DATA ((volatile unsigned long *)0xb4000cfc)
+#define PCI_CFG_CTRL ((volatile unsigned long *)0xb4000cf8)
#define PCI_CFG_SET(dev,where) \
((*PCI_CFG_CTRL) = (0x80000000 | (PCI_SLOT ((dev)->devfn) << 11) | \
@@ -268,14 +275,14 @@
u32 *val)
{
if (where & 0x3)
- return PCIBIOS_BAD_REGISTER_NUMBER;
- if (pci_range_ck (dev)) {
- *val = 0xFFFFFFFF;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
- PCI_CFG_SET(dev, where);
- *val = *PCI_CFG_DATA;
- return PCIBIOS_SUCCESSFUL;
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ if (pci_range_ck (dev)) {
+ *val = 0xFFFFFFFF;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+ PCI_CFG_SET(dev, where);
+ *val = *PCI_CFG_DATA;
+ return PCIBIOS_SUCCESSFUL;
}
static int qube_pci_read_config_word (struct pci_dev *dev,
@@ -283,27 +290,27 @@
u16 *val)
{
if (where & 0x1)
- return PCIBIOS_BAD_REGISTER_NUMBER;
- if (pci_range_ck (dev)) {
- *val = 0xffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
- PCI_CFG_SET(dev, (where & ~0x3));
- *val = *PCI_CFG_DATA >> ((where & 3) * 8);
- return PCIBIOS_SUCCESSFUL;
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ if (pci_range_ck (dev)) {
+ *val = 0xffff;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+ PCI_CFG_SET(dev, (where & ~0x3));
+ *val = *PCI_CFG_DATA >> ((where & 3) * 8);
+ return PCIBIOS_SUCCESSFUL;
}
static int qube_pci_read_config_byte (struct pci_dev *dev,
int where,
u8 *val)
{
- if (pci_range_ck (dev)) {
- *val = 0xff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
- PCI_CFG_SET(dev, (where & ~0x3));
- *val = *PCI_CFG_DATA >> ((where & 3) * 8);
- return PCIBIOS_SUCCESSFUL;
+ if (pci_range_ck (dev)) {
+ *val = 0xff;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+ PCI_CFG_SET(dev, (where & ~0x3));
+ *val = *PCI_CFG_DATA >> ((where & 3) * 8);
+ return PCIBIOS_SUCCESSFUL;
}
static int qube_pci_write_config_dword (struct pci_dev *dev,
@@ -311,12 +318,12 @@
u32 val)
{
if(where & 0x3)
- return PCIBIOS_BAD_REGISTER_NUMBER;
- if (pci_range_ck (dev))
- return PCIBIOS_DEVICE_NOT_FOUND;
- PCI_CFG_SET(dev, where);
- *PCI_CFG_DATA = val;
- return PCIBIOS_SUCCESSFUL;
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ if (pci_range_ck (dev))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ PCI_CFG_SET(dev, where);
+ *PCI_CFG_DATA = val;
+ return PCIBIOS_SUCCESSFUL;
}
static int
@@ -326,16 +333,16 @@
{
unsigned long tmp;
- if (where & 0x1)
- return PCIBIOS_BAD_REGISTER_NUMBER;
- if (pci_range_ck (dev))
- return PCIBIOS_DEVICE_NOT_FOUND;
- PCI_CFG_SET(dev, (where & ~0x3));
- tmp = *PCI_CFG_DATA;
- tmp &= ~(0xffff << ((where & 0x3) * 8));
- tmp |= (val << ((where & 0x3) * 8));
- *PCI_CFG_DATA = tmp;
- return PCIBIOS_SUCCESSFUL;
+ if (where & 0x1)
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ if (pci_range_ck (dev))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ PCI_CFG_SET(dev, (where & ~0x3));
+ tmp = *PCI_CFG_DATA;
+ tmp &= ~(0xffff << ((where & 0x3) * 8));
+ tmp |= (val << ((where & 0x3) * 8));
+ *PCI_CFG_DATA = tmp;
+ return PCIBIOS_SUCCESSFUL;
}
static int
@@ -345,52 +352,52 @@
{
unsigned long tmp;
- if (pci_range_ck (dev))
- return PCIBIOS_DEVICE_NOT_FOUND;
- PCI_CFG_SET(dev, (where & ~0x3));
- tmp = *PCI_CFG_DATA;
- tmp &= ~(0xff << ((where & 0x3) * 8));
- tmp |= (val << ((where & 0x3) * 8));
- *PCI_CFG_DATA = tmp;
- return PCIBIOS_SUCCESSFUL;
+ if (pci_range_ck (dev))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ PCI_CFG_SET(dev, (where & ~0x3));
+ tmp = *PCI_CFG_DATA;
+ tmp &= ~(0xff << ((where & 0x3) * 8));
+ tmp |= (val << ((where & 0x3) * 8));
+ *PCI_CFG_DATA = tmp;
+ return PCIBIOS_SUCCESSFUL;
}
struct pci_ops qube_pci_ops = {
- qube_pci_read_config_byte,
- qube_pci_read_config_word,
- qube_pci_read_config_dword,
- qube_pci_write_config_byte,
- qube_pci_write_config_word,
- qube_pci_write_config_dword
+ qube_pci_read_config_byte,
+ qube_pci_read_config_word,
+ qube_pci_read_config_dword,
+ qube_pci_write_config_byte,
+ qube_pci_write_config_word,
+ qube_pci_write_config_dword
};
void __init pcibios_init(void)
{
- printk("PCI: Probing PCI hardware\n");
+ printk("PCI: Probing PCI hardware\n");
- ioport_resource.start = 0x00000000;
+ ioport_resource.start = 0x00000000;
ioport_resource.end = 0x0fffffff;
iomem_resource.start = 0x01000000;
iomem_resource.end = 0xffffffff;
- pci_scan_bus(0, &qube_pci_ops, NULL);
+ pci_scan_bus(0, &qube_pci_ops, NULL);
}
char *pcibios_setup(char *str)
{
- return str;
+ return str;
}
int pcibios_enable_device(struct pci_dev *dev)
{
- u16 cmd, status;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- pci_read_config_word(dev, PCI_STATUS, &status);
+ u16 cmd, status;
+
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ pci_read_config_word(dev, PCI_STATUS, &status);
printk("PCI: Enabling device %s (%04x %04x)\n", dev->slot_name, cmd, status);
- /* We'll sort this out when we know it isn't enabled ;) */
+ /* We'll sort this out when we know it isn't enabled ;) */
return 0;
}
@@ -402,8 +409,8 @@
panic("Uhhoh called pcibios_align_resource\n");
}
-void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
- struct resource *res, int resource)
+void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
+ struct resource *res, int resource)
{
panic("Uhhoh called pcibios_update_resource\n");
@@ -416,7 +423,7 @@
unsigned int __init pcibios_assign_all_busses(void)
{
- return 1;
+ return 1;
}
#endif /* CONFIG_PCI */
|
|
From: Paul M. <le...@us...> - 2002-05-28 20:25:41
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv7651/include/asm-mips64
Modified Files:
bitops.h pgtable.h system.h
Added Files:
atomic.h
Log Message:
Partial sync with OSS.
Index: bitops.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/bitops.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- bitops.h 5 Feb 2002 17:07:49 -0000 1.7
+++ bitops.h 28 May 2002 20:25:38 -0000 1.8
@@ -9,6 +9,7 @@
#ifndef _ASM_BITOPS_H
#define _ASM_BITOPS_H
+#include <linux/config.h>
#include <linux/types.h>
#include <linux/byteorder/swab.h> /* sigh ... */
@@ -84,8 +85,8 @@
: "ir" (~(1UL << (nr & 0x3f))), "m" (*m));
}
-#define smp_mb__before_clear_bit() barrier()
-#define smp_mb__after_clear_bit() barrier()
+#define smp_mb__before_clear_bit() smp_mb()
+#define smp_mb__after_clear_bit() smp_mb()
/*
* change_bit - Toggle a bit in memory
@@ -147,6 +148,9 @@
"scd\t%2, %1\n\t"
"beqz\t%2, 1b\n\t"
" and\t%2, %0, %3\n\t"
+#ifdef CONFIG_SMP
+ "sync\n\t"
+#endif
".set\treorder"
: "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << (nr & 0x3f)), "m" (*m)
@@ -199,6 +203,9 @@
"scd\t%2, %1\n\t"
"beqz\t%2, 1b\n\t"
" and\t%2, %0, %3\n\t"
+#ifdef CONFIG_SMP
+ "sync\n\t"
+#endif
".set\treorder"
: "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << (nr & 0x3f)), "m" (*m)
@@ -250,6 +257,9 @@
"scd\t%2, %1\n\t"
"beqz\t%2, 1b\n\t"
" and\t%2, %0, %3\n\t"
+#ifdef CONFIG_SMP
+ "sync\n\t"
+#endif
".set\treorder"
: "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << (nr & 0x3f)), "m" (*m)
Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/pgtable.h,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- pgtable.h 18 Mar 2002 22:47:15 -0000 1.13
+++ pgtable.h 28 May 2002 20:25:38 -0000 1.14
@@ -74,12 +74,22 @@
#else
+extern void (*_flush_icache_all)(void);
+extern void (*_flush_icache_range)(unsigned long start, unsigned long end);
+extern void (*_flush_icache_page)(struct vm_area_struct *vma, struct page *page);
+
#define flush_cache_mm(mm) _flush_cache_mm(mm)
#define flush_cache_range(mm,start,end) _flush_cache_range(mm,start,end)
#define flush_cache_page(vma,page) _flush_cache_page(vma, page)
#define flush_page_to_ram(page) _flush_page_to_ram(page)
#define flush_icache_range(start, end) _flush_icache_range(start, end)
#define flush_icache_page(vma, page) _flush_icache_page(vma, page)
+#ifdef CONFIG_VTAG_ICACHE
+#define flush_icache_all() _flush_icache_all()
+#else
+#define flush_icache_all() do { } while(0)
+#endif
+
#endif /* !CONFIG_CPU_R10000 */
@@ -566,6 +576,12 @@
#define pgtable_cache_init() do { } while (0)
#include <asm-generic/pgtable.h>
+
+/*
+ * We provide our own get_unmapped area to cope with the virtual aliasing
+ * constraints placed on us by the cache architecture.
+ */
+#define HAVE_ARCH_UNMAPPED_AREA
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
Index: system.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/system.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- system.h 5 Feb 2002 17:22:20 -0000 1.9
+++ system.h 28 May 2002 20:25:38 -0000 1.10
@@ -11,10 +11,8 @@
#define _ASM_SYSTEM_H
#include <linux/config.h>
-
#include <asm/sgidefs.h>
#include <asm/ptrace.h>
-
#include <linux/kernel.h>
__asm__ (
@@ -117,9 +115,9 @@
"xori\t$1, 1\n\t"
"or\t\\flags, $1\n\t"
"mtc0\t\\flags, $12\n\t"
- "nop\n\t"
- "nop\n\t"
- "nop\n\t"
+ "sll\t$0, $0, 1\t\t\t# nop\n\t"
+ "sll\t$0, $0, 1\t\t\t# nop\n\t"
+ "sll\t$0, $0, 1\t\t\t# nop\n\t"
".set\tat\n\t"
".set\treorder\n\t"
".endm");
@@ -194,19 +192,18 @@
#define set_wmb(var, value) \
do { var = value; wmb(); } while (0)
-#if !defined (_LANGUAGE_ASSEMBLY)
/*
* switch_to(n) should switch tasks to task nr n, first
* checking that n isn't the current task, in which case it does nothing.
*/
extern asmlinkage void *resume(void *last, void *next);
-#endif /* !defined (_LANGUAGE_ASSEMBLY) */
#define prepare_to_switch() do { } while(0)
extern asmlinkage void lazy_fpu_switch(void *, void *);
extern asmlinkage void init_fpu(void);
-extern asmlinkage void save_fp(void *);
+extern asmlinkage void save_fp(struct task_struct *);
+extern asmlinkage void restore_fp(struct task_struct *);
#ifdef CONFIG_SMP
#define SWITCH_DO_LAZY_FPU \
|
|
From: Paul M. <le...@us...> - 2002-05-28 20:25:41
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/cobalt In directory usw-pr-cvs1:/tmp/cvs-serv7651/include/asm-mips/cobalt Modified Files: cobalt.h Log Message: Partial sync with OSS. Index: cobalt.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cobalt/cobalt.h,v retrieving revision 1.4 retrieving revision 1.5 diff -u -d -r1.4 -r1.5 --- cobalt.h 21 Apr 2002 20:01:15 -0000 1.4 +++ cobalt.h 28 May 2002 20:25:37 -0000 1.5 @@ -38,6 +38,7 @@ #define COBALT_TIMER_IRQ 0 #define COBALT_KEYBOARD_IRQ 1 #define COBALT_QUBE_ETH_IRQ 13 +#define COBALT_QUBE_SLOT_IRQ 9 #define COBALT_RAQ_ETH0_IRQ 4 #define COBALT_RAQ_ETH1_IRQ 13 #define COBALT_SCC_IRQ 4 |
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