linux-mips-commits — CVS Commit Patches

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/vr4111/casio-e15 setup.c,1.6,1.7

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4111/casio-e15
In directory usw-pr-cvs1:/tmp/cvs-serv20226/arch/mips/vr41xx/vr4111/casio-e15

Modified Files:
	setup.c 
Log Message:
Kill off the need for platform specific vr41xx_board_irq_init(). Calling
vr41xx_board_irq_init() will be a nop on platforms that don't specifically
assign a value to board_irq_init. See eagle for an example.



Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4111/casio-e15/setup.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- setup.c	13 Jun 2002 07:45:19 -0000	1.6
+++ setup.c	14 Jun 2002 15:02:15 -0000	1.7
@@ -51,11 +51,6 @@
 
 struct semaphore vr41xx_dma_sem;
 
-
-void __init vr41xx_board_irq_init(void)
-{
-}
-
 #ifdef CONFIG_PM_SUSPEND_WAKEUP
 #include <asm/gdb-stub.h>
 

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/vr4122/eagle irq.c,1.1,1.2 setup.c,1.1,1.2

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4122/eagle
In directory usw-pr-cvs1:/tmp/cvs-serv20226/arch/mips/vr41xx/vr4122/eagle

Modified Files:
	irq.c setup.c 
Log Message:
Kill off the need for platform specific vr41xx_board_irq_init(). Calling
vr41xx_board_irq_init() will be a nop on platforms that don't specifically
assign a value to board_irq_init. See eagle for an example.



Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4122/eagle/irq.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- irq.c	7 Mar 2002 03:16:54 -0000	1.1
+++ irq.c	14 Jun 2002 15:02:15 -0000	1.2
@@ -102,7 +102,7 @@
 	return -1;
 }
 
-void __init vr41xx_board_irq_init(void)
+void __init eagle_board_irq_init(void)
 {
 	int i;
 

Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4122/eagle/setup.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- setup.c	7 Mar 2002 03:16:54 -0000	1.1
+++ setup.c	14 Jun 2002 15:02:15 -0000	1.2
@@ -72,6 +72,8 @@
 	_machine_halt = vr41xx_halt;
 	_machine_power_off = vr41xx_power_off;
 
+	board_irq_init = eagle_board_irq_init;
+
 	board_time_init = vr41xx_time_init;
 	board_timer_setup = vr41xx_timer_setup;
 

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/vr4131/casio-be300 Makefile,1.2,1.3 irq.c,1.1,NONE

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4131/casio-be300
In directory usw-pr-cvs1:/tmp/cvs-serv20226/arch/mips/vr41xx/vr4131/casio-be300

Modified Files:
	Makefile 
Removed Files:
	irq.c 
Log Message:
Kill off the need for platform specific vr41xx_board_irq_init(). Calling
vr41xx_board_irq_init() will be a nop on platforms that don't specifically
assign a value to board_irq_init. See eagle for an example.



Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4131/casio-be300/Makefile,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- Makefile	9 Mar 2002 07:47:19 -0000	1.2
+++ Makefile	14 Jun 2002 15:02:15 -0000	1.3
@@ -13,7 +13,7 @@
 
 O_TARGET := casio-be300.o
 
-obj-y	 := prom.o setup.o irq.o
+obj-y	 := prom.o setup.o
 
 obj-$(CONFIG_PCI) += pci_fixup.o
 

--- irq.c DELETED ---

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/common irq.c,1.3,1.4 Makefile,1.7,1.8

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/common
In directory usw-pr-cvs1:/tmp/cvs-serv20226/arch/mips/vr41xx/common

Modified Files:
	Makefile 
Added Files:
	irq.c 
Log Message:
Kill off the need for platform specific vr41xx_board_irq_init(). Calling
vr41xx_board_irq_init() will be a nop on platforms that don't specifically
assign a value to board_irq_init. See eagle for an example.




Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/common/Makefile,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- Makefile	13 Jun 2002 12:57:33 -0000	1.7
+++ Makefile	14 Jun 2002 15:02:14 -0000	1.8
@@ -15,7 +15,7 @@
 
 O_TARGET := vr41xx.o
 
-obj-y		:= int-handler.o reset.o
+obj-y		:= int-handler.o reset.o irq.o
 
 obj-$(CONFIG_VR41XX_TIME_C)	+= time.o
 

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/vr4181/osprey setup.c,1.3,1.4

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv3865

Modified Files:
	setup.c 
Log Message:
Ack. Make sure we use reset functions that actually exist.



Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/osprey/setup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- setup.c	14 Jun 2002 14:12:19 -0000	1.3
+++ setup.c	14 Jun 2002 14:16:21 -0000	1.4
@@ -43,9 +43,9 @@
 	conswitchp = &dummy_con;
 #endif
  
-	_machine_restart = nec_vr41xx_restart;
-	_machine_halt = nec_vr41xx_halt;
-	_machine_power_off = nec_vr41xx_power_off;
+	_machine_restart = vr41xx_restart;
+	_machine_halt = vr41xx_halt;
+	_machine_power_off = vr41xx_power_off;
 
 	/* setup resource limit */
 	ioport_resource.end = 0xffffffff;

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/vr4181/osprey irq.c,NONE,1.1 Makefile,1.1,1.2 setup.c,1.2,1.3 reset.c,1.1,NONE

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv2451

Modified Files:
	Makefile setup.c 
Added Files:
	irq.c 
Removed Files:
	reset.c 
Log Message:
Use the generic reset routines.



--- NEW FILE: irq.c ---
/*
 * arch/mips/vr41xx/vr4181/osprey/irq.c
 *
 * Interrupt routines for the NEC Osprey
 *
 * Copyright (C) 2002 Paul Mundt <le...@ch...>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 */
#include <linux/init.h>

void __init vr41xx_board_irq_init(void)
{
}


Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/osprey/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- Makefile	14 Jun 2002 13:55:59 -0000	1.1
+++ Makefile	14 Jun 2002 14:12:19 -0000	1.2
@@ -13,7 +13,7 @@
 
 O_TARGET := osprey.o
 
-obj-y	 := setup.o prom.o reset.o
+obj-y	 := setup.o prom.o irq.o
 
 obj-$(CONFIG_REMOTE_DEBUG)	+= dbg_io.o
 

Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/osprey/setup.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- setup.c	14 Jun 2002 14:01:52 -0000	1.2
+++ setup.c	14 Jun 2002 14:12:19 -0000	1.3
@@ -21,14 +21,9 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <asm/reboot.h>
-#include <asm/vr4181/vr4181.h>
+#include <asm/vr41xx.h>
 #include <asm/io.h>
 
-
-extern void nec_osprey_restart(char* c);
-extern void nec_osprey_halt(void);
-extern void nec_osprey_power_off(void);
-
 extern void vr4181_init_serial(void);
 extern void vr4181_init_time(void);
 
@@ -48,9 +43,9 @@
 	conswitchp = &dummy_con;
 #endif
  
-	_machine_restart = nec_osprey_restart;
-	_machine_halt = nec_osprey_halt;
-	_machine_power_off = nec_osprey_power_off;
+	_machine_restart = nec_vr41xx_restart;
+	_machine_halt = nec_vr41xx_halt;
+	_machine_power_off = nec_vr41xx_power_off;
 
 	/* setup resource limit */
 	ioport_resource.end = 0xffffffff;

--- reset.c DELETED ---

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/vr4181/common icu.c,1.1,1.2 icu.h,1.1,1.2

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/common
In directory usw-pr-cvs1:/tmp/cvs-serv1408

Modified Files:
	icu.c icu.h 
Log Message:
Vr4111 -> Vr4181 ICU changes.



Index: icu.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/common/icu.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- icu.c	14 Jun 2002 14:06:46 -0000	1.1
+++ icu.c	14 Jun 2002 14:09:25 -0000	1.2
@@ -1,9 +1,9 @@
 /*
  * FILE NAME
- *	arch/mips/vr41xx/vr4111/common/icu.c
+ *	arch/mips/vr41xx/vr4181/common/icu.c
  *
  * BRIEF MODULE DESCRIPTION
- *	Interrupt Control Unit routines for the NEC VR4111.
+ *	Interrupt Control Unit routines for the NEC VR4181.
  *
  * Author: Yoichi Yuasa
  *         yy...@mv... or so...@mv...
@@ -33,6 +33,7 @@
 /*
  * Changes:
  *  Paul Mundt <le...@ch...>
+ *  - Modified this code for VR4181 support.
  *  - kgdb support.
  *
  *  MontaVista Software Inc. <yy...@mv...> or <so...@mv...>

Index: icu.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/common/icu.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- icu.h	14 Jun 2002 14:06:46 -0000	1.1
+++ icu.h	14 Jun 2002 14:09:25 -0000	1.2
@@ -1,9 +1,9 @@
 /*
  * FILE NAME
- *	arch/mips/vr41xx/vr4111/common/icu.h
+ *	arch/mips/vr41xx/vr4181/common/icu.h
  *
  * BRIEF MODULE DESCRIPTION
- *	Include file for Interrupt Control Unit of the NEC VR4111.
+ *	Include file for Interrupt Control Unit of the NEC VR4181.
  *
  * Author: Yoichi Yuasa
  *         yy...@mv... or so...@mv...
@@ -32,6 +32,9 @@
  */
 /*
  * Changes:
+ *  Paul Mundt <le...@ch...>
+ *  - Modified this code for VR4181 support.
+ *
  *  MontaVista Software Inc. <yy...@mv...> or <so...@mv...>
  *  - New creation, NEC VR4122 and VR4131 are supported.
  *
@@ -48,18 +51,18 @@
 #include <linux/config.h>
 #include <asm/addrspace.h>
 
-#define SYSINT1REG	KSEG1ADDR(0x0b000080)
-#define GIUINTLREG	KSEG1ADDR(0x0b000088)
-#define MSYSINT1REG	KSEG1ADDR(0x0b00008c)
-#define MGIUINTLREG	KSEG1ADDR(0x0b000094)
+#define SYSINT1REG	KSEG1ADDR(0x0a000080)
+#define GIUINTLREG	KSEG1ADDR(0x0a000088)
+#define MSYSINT1REG	KSEG1ADDR(0x0a00008c)
+#define MGIUINTLREG	KSEG1ADDR(0x0a000094)
 
-#define NMIREG		KSEG1ADDR(0x0b000098)
-#define SOFTINTREG	KSEG1ADDR(0x0b00009a)
+#define NMIREG		KSEG1ADDR(0x0a000098)
+#define SOFTINTREG	KSEG1ADDR(0x0a00009a)
 
-#define SYSINT2REG	KSEG1ADDR(0x0b000200)
-#define GIUINTHREG	KSEG1ADDR(0x0b000202)
-#define MSYSINT2REG	KSEG1ADDR(0x0b000206)
-#define MGIUINTHREG	KSEG1ADDR(0x0b000208)
+#define SYSINT2REG	KSEG1ADDR(0x0a000200)
+#define GIUINTHREG	KSEG1ADDR(0x0a000202)
+#define MSYSINT2REG	KSEG1ADDR(0x0a000206)
+#define MGIUINTHREG	KSEG1ADDR(0x0a000208)
 
 #define GIUINTSTATL	KSEG1ADDR(0x0b000108)
 #define GIUINTSTATH	KSEG1ADDR(0x0b00010a)

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/vr4181/common icu.c,NONE,1.1 icu.h,NONE,1.1 Makefile,1.1,1.2 int_handler.S,1.1,NONE irq.c,1.1,NONE

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/common
In directory usw-pr-cvs1:/tmp/cvs-serv334

Modified Files:
	Makefile 
Added Files:
	icu.c icu.h 
Removed Files:
	int_handler.S irq.c 
Log Message:
Nuke the old interrupt handling code, use the new common interface.



--- NEW FILE: icu.c ---
/*
 * FILE NAME
 *	arch/mips/vr41xx/vr4111/common/icu.c
 *
 * BRIEF MODULE DESCRIPTION
 *	Interrupt Control Unit routines for the NEC VR4111.
 *
 * Author: Yoichi Yuasa
 *         yy...@mv... or so...@mv...
 *
 * Copyright 2001,2002 MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
/*
 * Changes:
 *  Paul Mundt <le...@ch...>
 *  - kgdb support.
 *
 *  MontaVista Software Inc. <yy...@mv...> or <so...@mv...>
 *  - New creation, NEC VR4122 and VR4131 are supported.
 *
 *  Yoichi Yuasa <yu...@hh...>  Tue,  5 Mar 2002
 *  - This file was copied from arch/mips/vr41xx/vr4122/common/icu.c.
 *    Only FILE NAME and BRIEF MODULE DESCRIPTION modified this file.
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/types.h>

#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/vr41xx.h>
#include <asm/gdb-stub.h>

#include "icu.h"

extern asmlinkage void vr41xx_handle_interrupt(void);
extern void __init init_generic_irq(void);
extern void mips_cpu_irq_init(u32 irq_base);
extern unsigned int do_IRQ(int irq, struct pt_regs *regs);

/*=======================================================================*/

static void enable_sysint1_irq(unsigned int irq)
{
	u16 val;

	val = readw(MSYSINT1REG);
	val |= (u16)1 << (irq - SYSINT1_IRQ_BASE);
	writew(val, MSYSINT1REG);
}

static void disable_sysint1_irq(unsigned int irq)
{
	u16 val;

	val = readw(MSYSINT1REG);
	val &= ~((u16)1 << (irq - SYSINT1_IRQ_BASE));
	writew(val, MSYSINT1REG);
}

static unsigned int startup_sysint1_irq(unsigned int irq)
{ 
	enable_sysint1_irq(irq);
	return 0; /* never anything pending */
}

#define shutdown_sysint1_irq	disable_sysint1_irq
#define ack_sysint1_irq		disable_sysint1_irq

static void end_sysint1_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_sysint1_irq(irq);
}

static struct hw_interrupt_type sysint1_irq_type = {
	"SYSINT1",
	startup_sysint1_irq,
	shutdown_sysint1_irq,
	enable_sysint1_irq,
	disable_sysint1_irq,
	ack_sysint1_irq,
	end_sysint1_irq,
	NULL
};

/*=======================================================================*/

static void enable_sysint2_irq(unsigned int irq)
{
	u16 val;

	val = readw(MSYSINT2REG);
	val |= (u16)1 << (irq - SYSINT2_IRQ_BASE);
	writew(val, MSYSINT2REG);
}

static void disable_sysint2_irq(unsigned int irq)
{
	u16 val;

	val = readw(MSYSINT2REG);
	val &= ~((u16)1 << (irq - SYSINT2_IRQ_BASE));
	writew(val, MSYSINT2REG);
}

static unsigned int startup_sysint2_irq(unsigned int irq)
{ 
	enable_sysint2_irq(irq);
	return 0; /* never anything pending */
}

#define shutdown_sysint2_irq	disable_sysint2_irq
#define ack_sysint2_irq		disable_sysint2_irq

static void end_sysint2_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_sysint2_irq(irq);
}

static struct hw_interrupt_type sysint2_irq_type = {
	"SYSINT2",
	startup_sysint2_irq,
	shutdown_sysint2_irq,
	enable_sysint2_irq,
	disable_sysint2_irq,
	ack_sysint2_irq,
	end_sysint2_irq,
	NULL
};

/*=======================================================================*/

static void enable_giuintl_irq(unsigned int irq)
{
	u16 val, mask;

	mask = (u16)1 << (irq - GIUINTL_IRQ_BASE);
	writew(mask, GIUINTSTATL);

	val = readw(MGIUINTLREG);
	val |= mask;
	writew(val, MGIUINTLREG);

	val = readw(GIUINTENL);
	val |= mask;
	writew(val, GIUINTENL);
}

static void disable_giuintl_irq(unsigned int irq)
{
	u16 val, mask;

	mask = (u16)1 << (irq - GIUINTL_IRQ_BASE);
	val = readw(GIUINTENL);
	val &= ~mask;
	writew(val, GIUINTENL);

	val = readw(MGIUINTLREG);
	val &= ~mask;
	writew(val, MGIUINTLREG);

	writew(mask, GIUINTSTATL);
}

static unsigned int startup_giuintl_irq(unsigned int irq)
{ 
	enable_giuintl_irq(irq);
	return 0; /* never anything pending */
}

#define shutdown_giuintl_irq	disable_giuintl_irq
#define ack_giuintl_irq		disable_giuintl_irq

static void end_giuintl_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_giuintl_irq(irq);
}

static struct hw_interrupt_type giuintl_irq_type = {
	"GIUINTL",
	startup_giuintl_irq,
	shutdown_giuintl_irq,
	enable_giuintl_irq,
	disable_giuintl_irq,
	ack_giuintl_irq,
	end_giuintl_irq,
	NULL
};

/*=======================================================================*/

static void enable_giuinth_irq(unsigned int irq)
{
	unsigned short val, mask;

	mask = (u16)1 << (irq - GIUINTH_IRQ_BASE);
	writew(mask, GIUINTSTATH);

	val = readw(MGIUINTHREG);
	val |= mask;
	writew(val, MGIUINTHREG);

	val = readw(GIUINTENH);
	val |= mask;
	writew(val, GIUINTENH);
}

static void disable_giuinth_irq(unsigned int irq)
{
	unsigned short val, mask;

	mask = (u16)1 << (irq - GIUINTH_IRQ_BASE);
	val= readw(GIUINTENH);
	val &= ~mask;
	writew(val, GIUINTENH);

	val = readw(MGIUINTHREG);
	val &= ~mask;
	writew(val, MGIUINTHREG);

	writew(mask, GIUINTSTATH);
}

static unsigned int startup_giuinth_irq(unsigned int irq)
{ 
	enable_giuinth_irq(irq);
	return 0; /* never anything pending */
}

#define shutdown_giuinth_irq	disable_giuinth_irq
#define ack_giuinth_irq		disable_giuinth_irq

static void end_giuinth_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_giuinth_irq(irq);
}

static struct hw_interrupt_type giuinth_irq_type = {
	"GIUINTH",
	startup_giuinth_irq,
	shutdown_giuinth_irq,
	enable_giuinth_irq,
	disable_giuinth_irq,
	ack_giuinth_irq,
	end_giuinth_irq,
	NULL
};

/*=======================================================================*/

static struct irqcascade vr41xx_irqcascade[32];

static struct irqaction cascade = {no_action, 0, 0, "cascade", NULL, NULL};
static int no_cascade_get_irq_number(int irq) { return -1; }

void vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq))
{
	if (GIUINTL_IRQ_BASE <= irq < GIUINTH_IRQ_LAST) {
		vr41xx_irqcascade[irq - GIUINTL_IRQ_BASE].cascade = 1;
		vr41xx_irqcascade[irq - GIUINTL_IRQ_BASE].get_irq_number = get_irq_number;
		setup_irq(irq, &cascade);
	}
}


static void __init vr41xx_icu_irq_init(void)
{
	int i;

	writew(0, MSYSINT1REG);
	writew(0, MSYSINT2REG);
	writew(0, MGIUINTLREG);
	writew(0, MGIUINTHREG);

	writew(0, GIUINTENL);
	writew(0, GIUINTENH);
	writew(0xffff, GIUINTSTATL);
	writew(0xffff, GIUINTSTATH);

	for (i = SYSINT1_IRQ_BASE; i <= GIUINTH_IRQ_LAST; i++) {
		if (i >= SYSINT1_IRQ_BASE && i <= SYSINT1_IRQ_LAST)
			irq_desc[i].handler = &sysint1_irq_type;
		else if (i >= SYSINT2_IRQ_BASE && i <= SYSINT2_IRQ_LAST)
			irq_desc[i].handler = &sysint2_irq_type;
		else if (i >= GIUINTL_IRQ_BASE && i <= GIUINTL_IRQ_LAST)
			irq_desc[i].handler = &giuintl_irq_type;
		else if (i >= GIUINTH_IRQ_BASE && i <= GIUINTH_IRQ_LAST)
			irq_desc[i].handler = &giuinth_irq_type;
	}

	for (i = 0; i < 32; i++) {
		vr41xx_irqcascade[i].cascade = 0;
		vr41xx_irqcascade[i].get_irq_number = no_cascade_get_irq_number;
	}

}

void __init init_IRQ(void)
{

	memset(irq_desc, 0, sizeof(irq_desc));

	init_generic_irq();
	mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
	vr41xx_icu_irq_init();
	vr41xx_board_irq_init();

	setup_irq(ICU_IRQ, &cascade);
	setup_irq(GIU_IRQ, &cascade);

	set_except_vector(0, vr41xx_handle_interrupt);

#ifdef CONFIG_REMOTE_DEBUG
	printk("Setting debug traps - please connect the remote debugger.\n");
	set_debug_traps();
	breakpoint();
#endif
}

/*=======================================================================*/

static void giuint_do_IRQ(int giuint_irq, struct pt_regs *regs)
{
	struct irqcascade *irq;
	int cascade_irq;

	irq = &vr41xx_irqcascade[giuint_irq - GIUINTL_IRQ_BASE];
	if (irq->cascade) {
		cascade_irq = irq->get_irq_number(giuint_irq);
		disable_irq(giuint_irq);
		if (cascade_irq > 0)
			do_IRQ(cascade_irq, regs);
		enable_irq(giuint_irq);
	}
	else
		do_IRQ(giuint_irq, regs);
}

static inline void giuint_irqdispatch(u16 pendl, u16 pendh, struct pt_regs *regs)
{
	int i;

	if (pendl) {
		for (i = 0; i < 16; i++) {
			if (pendl & (0x0001 << i)) {
				giuint_do_IRQ(GIUINTL_IRQ_BASE + i, regs);
				return;
			}
		}
	}
	else if (pendh) {
		for (i = 0; i < 16; i++) {
			if (pendh & (0x0001 << i)) {
				giuint_do_IRQ(GIUINTH_IRQ_BASE + i, regs);
				return;
			}
		}
	}
}

asmlinkage void icu_irqdispatch(struct pt_regs *regs)
{
	u16 pend1, pend2, pendl, pendh;
	u16 mask1, mask2, maskl, maskh;
	int i;

	pend1 = readw(SYSINT1REG);
	mask1 = readw(MSYSINT1REG);

	pend2 = readw(SYSINT2REG);
	mask2 = readw(MSYSINT2REG);

	pendl = readw(GIUINTLREG);
	maskl = readw(MGIUINTLREG);

	pendh = readw(GIUINTHREG);
	maskh = readw(MGIUINTHREG);

	pend1 &= mask1;
	pend2 &= mask2;
	pendl &= maskl;
	pendh &= maskh;

	if (pend1) {
		if ((pend1 & 0x01ff) == 0x0100) {
			giuint_irqdispatch(pendl, pendh, regs);
		}
		else {
			for (i = 0; i < 16; i++) {
				if (pend1 & (0x0001 << i)) {
					do_IRQ(SYSINT1_IRQ_BASE + i, regs);
					break;
				}
			}
		}
		return;
	}
	else if (pend2) {
		for (i = 0; i < 16; i++) {
			if (pend2 & (0x0001 << i)) {
				do_IRQ(SYSINT2_IRQ_BASE + i, regs);
				break;
			}
		}
	}
}

--- NEW FILE: icu.h ---
/*
 * FILE NAME
 *	arch/mips/vr41xx/vr4111/common/icu.h
 *
 * BRIEF MODULE DESCRIPTION
 *	Include file for Interrupt Control Unit of the NEC VR4111.
 *
 * Author: Yoichi Yuasa
 *         yy...@mv... or so...@mv...
 *
 * Copyright 2002 MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
/*
 * Changes:
 *  MontaVista Software Inc. <yy...@mv...> or <so...@mv...>
 *  - New creation, NEC VR4122 and VR4131 are supported.
 *
 *  Yoichi Yuasa <yu...@hh...>  Tue,  5 Mar 2002
 *  -  Modified this code for VR4121 support.
 *
 *  Yoichi Yuasa <yu...@hh...>  Tue,  5 Mar 2002
 *  - This file was copied from arch/mips/vr41xx/vr4121/common/icu.h.
 *    Only FILE NAME and BRIEF MODULE DESCRIPTION modified this file.
 */
#ifndef __VR41XX_ICU_H
#define __VR41XX_ICU_H

#include <linux/config.h>
#include <asm/addrspace.h>

#define SYSINT1REG	KSEG1ADDR(0x0b000080)
#define GIUINTLREG	KSEG1ADDR(0x0b000088)
#define MSYSINT1REG	KSEG1ADDR(0x0b00008c)
#define MGIUINTLREG	KSEG1ADDR(0x0b000094)

#define NMIREG		KSEG1ADDR(0x0b000098)
#define SOFTINTREG	KSEG1ADDR(0x0b00009a)

#define SYSINT2REG	KSEG1ADDR(0x0b000200)
#define GIUINTHREG	KSEG1ADDR(0x0b000202)
#define MSYSINT2REG	KSEG1ADDR(0x0b000206)
#define MGIUINTHREG	KSEG1ADDR(0x0b000208)

#define GIUINTSTATL	KSEG1ADDR(0x0b000108)
#define GIUINTSTATH	KSEG1ADDR(0x0b00010a)
#define GIUINTENL	KSEG1ADDR(0x0b00010c)
#define GIUINTENH	KSEG1ADDR(0x0b00010e)
#define GIUINTTYPL	KSEG1ADDR(0x0b000110)
#define GIUINTTYPH	KSEG1ADDR(0x0b000112)
#define GIUINTALSELL	KSEG1ADDR(0x0b000114)
#define GIUINTALSELH	KSEG1ADDR(0x0b000116)
#define GIUINTHTSELL	KSEG1ADDR(0x0b000118)
#define GIUINTHTSELH	KSEG1ADDR(0x0b00011a)

#define MIPS_CPU_IRQ_BASE	0
#define SYSINT1_IRQ_BASE	8
#define SYSINT1_IRQ_LAST	23
#define SYSINT2_IRQ_BASE	24
#define SYSINT2_IRQ_LAST	39
#define GIUINTL_IRQ_BASE	40
#define GIUINTL_IRQ_LAST	55
#define GIUINTH_IRQ_BASE	56
#define GIUINTH_IRQ_LAST	71

#define ICU_IRQ			2
#define GIU_IRQ			(SYSINT1_IRQ_BASE + 8)

#endif /* __VR41XX_ICU_H */

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/common/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- Makefile	14 Jun 2002 13:54:59 -0000	1.1
+++ Makefile	14 Jun 2002 14:06:46 -0000	1.2
@@ -13,6 +13,6 @@
 
 O_TARGET:= vr4181.o
 
-obj-y	 := irq.o int_handler.o serial.o time.o
+obj-y	 := icu.o serial.o time.o
 
 include $(TOPDIR)/Rules.make

--- int_handler.S DELETED ---

--- irq.c DELETED ---

[Linux-mips-commits]CVS: linux/arch/mips Makefile,1.50,1.51

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv31807

Modified Files:
	Makefile 
Log Message:
Update Osprey locations.



Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/Makefile,v
retrieving revision 1.50
retrieving revision 1.51
diff -u -d -r1.50 -r1.51
--- Makefile	13 Jun 2002 13:35:49 -0000	1.50
+++ Makefile	14 Jun 2002 14:03:08 -0000	1.51
@@ -241,9 +241,12 @@
 # NEC Osprey (vr4181) board
 #
 ifdef CONFIG_NEC_OSPREY
-SUBDIRS       += arch/mips/vr4181/common arch/mips/vr4181/osprey
-LIBS          += arch/mips/vr4181/common/vr4181.o \
-                 arch/mips/vr4181/osprey/osprey.o
+SUBDIRS       += arch/mips/vr41xx/common \
+                 arch/mips/vr41xx/vr4181/common \
+                 arch/mips/vr41xx/vr4181/osprey
+LIBS          += arch/mips/vr41xx/common/vr41xx.o \
+                 arch/mips/vr41xx/vr4181/common/vr4181.o \
+                 arch/mips/vr41xx/vr4181/osprey/osprey.o
 LOADADDR      += 0x80002000
 endif
 

[Linux-mips-commits]CVS: linux/arch/mips/kernel setup.c,1.64,1.65

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv31187/kernel

Modified Files:
	setup.c 
Log Message:
nec_osprey_setup() -> nec_vr41xx_setup().



Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.64
retrieving revision 1.65
diff -u -d -r1.64 -r1.65
--- setup.c	29 May 2002 18:19:58 -0000	1.64
+++ setup.c	14 Jun 2002 14:01:52 -0000	1.65
@@ -762,7 +762,6 @@
 	void ikos_setup(void);
 	void momenco_ocelot_setup(void);
 	void nino_setup(void);
-	void nec_osprey_setup(void);
 	void ps2_setup(void);
 	void jmr3927_setup(void);
  	void it8172_setup(void);
@@ -861,11 +860,6 @@
        case MACH_GROUP_NEC_DDB:
                ddb_setup();
                break;
-#endif
-#ifdef CONFIG_NEC_OSPREY
-	case MACH_GROUP_NEC_VR41XX:
-		nec_osprey_setup();
-		break;
 #endif
 #ifdef CONFIG_CPU_VR41XX
 	case MACH_GROUP_NEC_VR41XX:

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/vr4181/osprey setup.c,1.1,1.2

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv31187/vr41xx/vr4181/osprey

Modified Files:
	setup.c 
Log Message:
nec_osprey_setup() -> nec_vr41xx_setup().



Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/osprey/setup.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- setup.c	14 Jun 2002 13:55:59 -0000	1.1
+++ setup.c	14 Jun 2002 14:01:52 -0000	1.2
@@ -36,7 +36,7 @@
 {
 }
 
-void __init nec_osprey_setup(void)
+void __init nec_vr41xx_setup(void)
 {
 	set_io_port_base(VR4181_PORT_BASE);
 	isa_slot_offset = VR4181_ISAMEM_BASE;

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/vr4181/osprey Makefile,NONE,1.1 dbg_io.c,NONE,1.1 prom.c,NONE,1.1 reset.c,NONE,1.1 setup.c,NONE,1.1

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv28603

Added Files:
	Makefile dbg_io.c prom.c reset.c setup.c 
Log Message:
Re-add Osprey specific bits.



--- NEW FILE: Makefile ---
#
# Makefile for common code of NEC Osprey board
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#

.S.s:
	$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
	$(CC) $(CFLAGS) -c $< -o $*.o

O_TARGET := osprey.o

obj-y	 := setup.o prom.o reset.o

obj-$(CONFIG_REMOTE_DEBUG)	+= dbg_io.o

include $(TOPDIR)/Rules.make

--- NEW FILE: dbg_io.c ---
/*
 * kgdb io functions for osprey.  We use the serial port on debug board.
 *
 * Copyright (C) 2001 MontaVista Software Inc.
 * Author: js...@mv... or js...@ju...
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

/* ======================= CONFIG ======================== */

/* [jsun] we use the second serial port for kdb */
#define         BASE                    0xb7fffff0
#define         MAX_BAUD                115200

/* distance in bytes between two serial registers */
#define         REG_OFFSET              1

/*
 * 0 - kgdb does serial init
 * 1 - kgdb skip serial init
 */
static int remoteDebugInitialized = 1;

/*
 * the default baud rate *if* kgdb does serial init
 */
#define		BAUD_DEFAULT		UART16550_BAUD_38400

/* ======================= END OF CONFIG ======================== */

typedef unsigned char uint8;
typedef unsigned int uint32;

#define         UART16550_BAUD_2400             2400
#define         UART16550_BAUD_4800             4800
#define         UART16550_BAUD_9600             9600
#define         UART16550_BAUD_19200            19200
#define         UART16550_BAUD_38400            38400
#define         UART16550_BAUD_57600            57600
#define         UART16550_BAUD_115200           115200

#define         UART16550_PARITY_NONE           0
#define         UART16550_PARITY_ODD            0x08
#define         UART16550_PARITY_EVEN           0x18
#define         UART16550_PARITY_MARK           0x28
#define         UART16550_PARITY_SPACE          0x38

#define         UART16550_DATA_5BIT             0x0
#define         UART16550_DATA_6BIT             0x1
#define         UART16550_DATA_7BIT             0x2
#define         UART16550_DATA_8BIT             0x3

#define         UART16550_STOP_1BIT             0x0
#define         UART16550_STOP_2BIT             0x4

/* register offset */
#define         OFS_RCV_BUFFER          0
#define         OFS_TRANS_HOLD          0
#define         OFS_SEND_BUFFER         0
#define         OFS_INTR_ENABLE         (1*REG_OFFSET)
#define         OFS_INTR_ID             (2*REG_OFFSET)
#define         OFS_DATA_FORMAT         (3*REG_OFFSET)
#define         OFS_LINE_CONTROL        (3*REG_OFFSET)
#define         OFS_MODEM_CONTROL       (4*REG_OFFSET)
#define         OFS_RS232_OUTPUT        (4*REG_OFFSET)
#define         OFS_LINE_STATUS         (5*REG_OFFSET)
#define         OFS_MODEM_STATUS        (6*REG_OFFSET)
#define         OFS_RS232_INPUT         (6*REG_OFFSET)
#define         OFS_SCRATCH_PAD         (7*REG_OFFSET)

#define         OFS_DIVISOR_LSB         (0*REG_OFFSET)
#define         OFS_DIVISOR_MSB         (1*REG_OFFSET)


/* memory-mapped read/write of the port */
#define         UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
#define         UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)

void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
        /* disable interrupts */
        UART16550_WRITE(OFS_INTR_ENABLE, 0);

        /* set up buad rate */
        {
                uint32 divisor;

                /* set DIAB bit */
                UART16550_WRITE(OFS_LINE_CONTROL, 0x80);

                /* set divisor */
                divisor = MAX_BAUD / baud;
                UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
                UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);

                /* clear DIAB bit */
                UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
        }

        /* set data format */
        UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
}


uint8 getDebugChar(void)
{
        if (!remoteDebugInitialized) {
                remoteDebugInitialized = 1;
                debugInit(BAUD_DEFAULT,
                          UART16550_DATA_8BIT,
                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
        }

        while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
        return UART16550_READ(OFS_RCV_BUFFER);
}


int putDebugChar(uint8 byte)
{
        if (!remoteDebugInitialized) {
                remoteDebugInitialized = 1;
                debugInit(BAUD_DEFAULT,
                          UART16550_DATA_8BIT,
                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
        }

        while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
        UART16550_WRITE(OFS_SEND_BUFFER, byte);
        return 1;
}

--- NEW FILE: prom.c ---
/*
 * Copyright 2001 MontaVista Software Inc.
 * Author: js...@mv... or js...@ju...
 *
 * arch/mips/vr4181/osprey/prom.c
 *     prom code for osprey.
 *
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

#include <linux/init.h>
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <asm/bootinfo.h>
#include <asm/addrspace.h>

char arcs_cmdline[CL_SIZE];

const char *get_system_type(void)
{
	return "NEC_Vr41xx Osprey";
}

/* 
 * [jsun] right now we assume it is the nec debug monitor, which does
 * not pass any arguments.
 */
void __init prom_init()
{
	strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 ");
	// strcpy(arcs_cmdline, "ether=0,0x0300,eth0 "
	// strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 ");

	mips_machgroup = MACH_GROUP_NEC_VR41XX;
	mips_machtype = MACH_NEC_OSPREY;

	/* 16MB fixed */
	add_memory_region(0, 16 << 20, BOOT_MEM_RAM);
}

void __init prom_free_prom_memory(void)
{
}

void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
{
}


--- NEW FILE: reset.c ---
/*
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Copyright (C) 1997, 2001 Ralf Baechle
 * Copyright 2001 MontaVista Software Inc.
 * Author: js...@mv... or js...@ju...
 */
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>

void nec_osprey_restart(char *command)
{
	set_cp0_status(ST0_ERL);
	change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
	flush_cache_all();
	write_32bit_cp0_register(CP0_WIRED, 0);
	__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
}

void nec_osprey_halt(void)
{
	printk(KERN_NOTICE "\n** You can safely turn off the power\n");
	while (1)
		__asm__(".set\tmips3\n\t"
			"wait\n\t"
			".set\tmips0");
}

void nec_osprey_power_off(void)
{
	nec_osprey_halt();
}

--- NEW FILE: setup.c ---
/*
 * linux/arch/mips/vr4181/setup.c
 *
 * VR41xx setup routines
 *
 * Copyright (C) 1999 Bradley D. LaRonde
 * Copyright (C) 1999, 2000 Michael Klar
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: js...@mv... or js...@ju...
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 */

#include <linux/config.h>
#include <linux/console.h>
#include <linux/ide.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <asm/reboot.h>
#include <asm/vr4181/vr4181.h>
#include <asm/io.h>


extern void nec_osprey_restart(char* c);
extern void nec_osprey_halt(void);
extern void nec_osprey_power_off(void);

extern void vr4181_init_serial(void);
extern void vr4181_init_time(void);

void __init bus_error_init(void)
{
}

void __init nec_osprey_setup(void)
{
	set_io_port_base(VR4181_PORT_BASE);
	isa_slot_offset = VR4181_ISAMEM_BASE;

	vr4181_init_serial();
	vr4181_init_time();

#ifdef CONFIG_FB
	conswitchp = &dummy_con;
#endif
 
	_machine_restart = nec_osprey_restart;
	_machine_halt = nec_osprey_halt;
	_machine_power_off = nec_osprey_power_off;

	/* setup resource limit */
	ioport_resource.end = 0xffffffff;
	iomem_resource.end = 0xffffffff;

	/* [jsun] hack */
	/*
	printk("[jsun] hack to change external ISA control register, %x -> %x\n",
		(*VR4181_XISACTL),
		(*VR4181_XISACTL) | 0x2);
	*VR4181_XISACTL |= 0x2;
	*/

	// *VR4181_GPHIBSTH = 0x2000;
	// *VR4181_GPMD0REG = 0x00c0;
	// *VR4181_GPINTEN	 = 1<<6;

	/* [jsun] I believe this will get the interrupt type right 
	 * for the ether port.
	 */
	*VR4181_GPINTTYPL = 0x3000;
}

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/vr4181/common Makefile,NONE,1.1 int_handler.S,NONE,1.1 irq.c,NONE,1.1 serial.c,NONE,1.1 time.c,NONE,1.1

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/common
In directory usw-pr-cvs1:/tmp/cvs-serv28233

Added Files:
	Makefile int_handler.S irq.c serial.c time.c 
Log Message:
Re-add Vr4181 common.



--- NEW FILE: Makefile ---
#
# Makefile for common code of NEC vr4181 based boards
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#

.S.s:
	$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
	$(CC) $(CFLAGS) -c $< -o $*.o

O_TARGET:= vr4181.o

obj-y	 := irq.o int_handler.o serial.o time.o

include $(TOPDIR)/Rules.make

--- NEW FILE: int_handler.S ---
/*
 * arch/mips/vr4181/common/int_handler.S
 *
 * Adapted to the VR4181 and almost entirely rewritten:
 * Copyright (C) 1999 Bradley D. LaRonde and Michael Klar
 *
 * Clean up to conform to the new IRQ
 * Copyright (C) 2001 MontaVista Software Inc.
 * Author: Jun Sun, js...@mv... or js...@ju...
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 */

#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>

#include <asm/vr4181/vr4181.h>

/*
 * [jsun]
 * See include/asm/vr4181/irq.h for IRQ assignment and strategy.
 */

	.text
	.set	noreorder

	.align	5
	NESTED(vr4181_handle_irq, PT_SIZE, ra)

	.set	noat
	SAVE_ALL
	CLI

	.set	at
	.set	noreorder

	mfc0	t0, CP0_CAUSE
	mfc0	t2, CP0_STATUS

	and	t0, t2

	/* we check IP3 first; it happens most frequently */
	andi	t1, t0, STATUSF_IP3
	bnez	t1, ll_cpu_ip3
	andi	t1, t0, STATUSF_IP2
	bnez	t1, ll_cpu_ip2
	andi	t1, t0, STATUSF_IP7	/* cpu timer */
	bnez	t1, ll_cputimer_irq
	andi	t1, t0, STATUSF_IP4
	bnez	t1, ll_cpu_ip4
	andi	t1, t0, STATUSF_IP5
	bnez	t1, ll_cpu_ip5
	andi	t1, t0, STATUSF_IP6
	bnez	t1, ll_cpu_ip6
	andi	t1, t0, STATUSF_IP0	/* software int 0 */
	bnez	t1, ll_cpu_ip0
	andi	t1, t0, STATUSF_IP1	/* software int 1 */
	bnez	t1, ll_cpu_ip1
	nop

	.set	reorder
do_spurious:
	j	spurious_interrupt

/*
 * regular CPU irqs
 */
ll_cputimer_irq:
	li	a0, VR4181_IRQ_TIMER
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq


ll_cpu_ip0:
	li	a0, VR4181_IRQ_SW1
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq

ll_cpu_ip1:
	li	a0, VR4181_IRQ_SW2
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq

ll_cpu_ip3:
	li	a0, VR4181_IRQ_INT1
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq

ll_cpu_ip4:
	li	a0, VR4181_IRQ_INT2
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq

ll_cpu_ip5:
	li	a0, VR4181_IRQ_INT3
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq

ll_cpu_ip6:
	li	a0, VR4181_IRQ_INT4
	move	a1, sp
	jal	do_IRQ
	j	ret_from_irq

/*
 *  One of the sys irq has happend.
 *
 *  In the interest of speed, we first determine in the following order
 *  which 16-irq block have pending interrupts:
 *	sysint1 (16 sources, including cascading intrs from GPIO)
 *	sysint2
 *	gpio (16 intr sources)
 *
 *  Then we do binary search to find the exact interrupt source.
 */
ll_cpu_ip2:

	lui	t3,%hi(VR4181_SYSINT1REG)
	lhu	t0,%lo(VR4181_SYSINT1REG)(t3)
	lhu	t2,%lo(VR4181_MSYSINT1REG)(t3)
	and	t0, 0xfffb		/* hack - remove RTC Long 1 intr */
	and	t0, t2
	beqz	t0, check_sysint2

	/* check for GPIO interrupts */
	andi	t1, t0, 0x0100
	bnez	t1, check_gpio_int

	/* so we have an interrupt in sysint1 which is not gpio int */
	li	a0, VR4181_SYS_IRQ_BASE - 1
	j	check_16

check_sysint2:

	lhu	t0,%lo(VR4181_SYSINT2REG)(t3)
	lhu	t2,%lo(VR4181_MSYSINT2REG)(t3)
	and	t0, 0xfffe		/* hack - remove RTC Long 2 intr */
	and	t0, t2
	li	a0, VR4181_SYS_IRQ_BASE + 16 - 1
	j	check_16

check_gpio_int:
	lui	t3,%hi(VR4181_GPINTMSK)
	lhu	t0,%lo(VR4181_GPINTMSK)(t3)
	lhu	t2,%lo(VR4181_GPINTSTAT)(t3)
	xori	t0, 0xffff			/* why? reverse logic? */
	and	t0, t2
	li	a0, VR4181_GPIO_IRQ_BASE - 1
	j	check_16

/*
 *  When we reach check_16, we have 16-bit status in t0 and base irq number
 *  in a0.
 */
check_16:
	andi	t1, t0, 0xff
	bnez	t1, check_8

	srl	t0, 8
	addi	a0, 8
	j	check_8

/*
 *  When we reach check_8, we have 8-bit status in t0 and base irq number
 *  in a0.
 */
check_8:
	andi	t1, t0, 0xf
	bnez	t1, check_4

	srl	t0, 4
	addi	a0, 4
	j	check_4

/*
 *  When we reach check_4, we have 4-bit status in t0 and base irq number
 *  in a0.
 */
check_4:
	andi	t0, t0, 0xf
	beqz	t0, do_spurious

loop:
	andi	t2, t0, 0x1
	srl	t0, 1
	addi	a0, 1
	beqz	t2, loop

found_it:
	move	a1, sp
	jal	do_IRQ

	j	ret_from_irq

	END(vr4181_handle_irq)

--- NEW FILE: irq.c ---
/*
 * Copyright (C) 2001 MontaVista Software Inc.
 * Author: Jun Sun, js...@mv... or js...@ju...
 *
 * linux/arch/mips/vr4181/common/irq.c
 *	Completely re-written to use the new irq.c
 *
 * Credits to Bradley D. LaRonde and Michael Klar for writing the original
 * irq.c file which was derived from the common irq.c file.
 *	
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 */
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/random.h>

#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/gdb-stub.h>

#include <asm/vr4181/vr4181.h>

/*
 * Strategy:
 *
 * We essentially have three irq controllers, CPU, system, and gpio.
 *
 * CPU irq controller is taken care by arch/mips/kernel/irq_cpu.c and
 * CONFIG_IRQ_CPU config option.
 *
 * We here provide sys_irq and gpio_irq controller code.
 */

static int sys_irq_base;
static int gpio_irq_base;

/* ---------------------- sys irq ------------------------ */
static void
sys_irq_enable(unsigned int irq)
{
	irq -= sys_irq_base;
	if (irq < 16) {
		*VR4181_MSYSINT1REG |= (u16)(1 << irq);
	} else {
		irq -= 16;
		*VR4181_MSYSINT2REG |= (u16)(1 << irq);
	}
}

static void
sys_irq_disable(unsigned int irq)
{
	irq -= sys_irq_base;
	if (irq < 16) {
		*VR4181_MSYSINT1REG &= ~((u16)(1 << irq));
	} else {
		irq -= 16;
		*VR4181_MSYSINT2REG &= ~((u16)(1 << irq));
	}

}

static unsigned int
sys_irq_startup(unsigned int irq)
{
	sys_irq_enable(irq);
	return 0;
}

#define sys_irq_shutdown	sys_irq_disable
#define sys_irq_ack		sys_irq_disable

static void
sys_irq_end(unsigned int irq)
{
	if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		sys_irq_enable(irq);
}

static hw_irq_controller sys_irq_controller = {
	"vr4181_sys_irq",
	sys_irq_startup,
	sys_irq_shutdown,
	sys_irq_enable,
	sys_irq_disable,
	sys_irq_ack,
	sys_irq_end,
	NULL			/* no affinity stuff for UP */
};

/* ---------------------- gpio irq ------------------------ */
/* gpio irq lines use reverse logic */
static void
gpio_irq_enable(unsigned int irq)
{
	irq -= gpio_irq_base;
	*VR4181_GPINTMSK &= ~((u16)(1 << irq));
}

static void
gpio_irq_disable(unsigned int irq)
{
	irq -= gpio_irq_base;
	*VR4181_GPINTMSK |= (u16)(1 << irq);
}

static unsigned int
gpio_irq_startup(unsigned int irq)
{
	gpio_irq_enable(irq);

	irq -= gpio_irq_base;
	*VR4181_GPINTEN |= (u16)(1 << irq );

	return 0;
}

static void
gpio_irq_shutdown(unsigned int irq)
{
	gpio_irq_disable(irq);

	irq -= gpio_irq_base;
	*VR4181_GPINTEN &= ~((u16)(1 << irq ));
}

static void
gpio_irq_ack(unsigned int irq)
{
	u16 irqtype;
	u16 irqshift;

	gpio_irq_disable(irq);

	/* we clear interrupt if it is edge triggered */
	irq -= gpio_irq_base;
	if (irq < 8) {
		irqtype = *VR4181_GPINTTYPL;
		irqshift = 2 << (irq*2);
	} else {
		irqtype = *VR4181_GPINTTYPH;
		irqshift = 2 << ((irq-8)*2);
	}
	if ( ! (irqtype & irqshift) ) {
		*VR4181_GPINTSTAT = (u16) (1 << irq);
	}
}

static void
gpio_irq_end(unsigned int irq)
{
	if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		gpio_irq_enable(irq);
}

static hw_irq_controller gpio_irq_controller = {
	"vr4181_gpio_irq",
	gpio_irq_startup,
	gpio_irq_shutdown,
	gpio_irq_enable,
	gpio_irq_disable,
	gpio_irq_ack,
	gpio_irq_end,
	NULL			/* no affinity stuff for UP */
};

/* ---------------------  IRQ init stuff ---------------------- */

extern asmlinkage void vr4181_handle_irq(void);
extern void breakpoint(void);
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
extern void mips_cpu_irq_init(u32 irq_base);

static struct irqaction cascade = 
	{ no_action, SA_INTERRUPT, 0, "cascade", NULL, NULL };
static struct irqaction reserved = 
	{ no_action, SA_INTERRUPT, 0, "cascade", NULL, NULL };

void __init init_IRQ(void)
{
	int i;
	extern irq_desc_t irq_desc[];

	set_except_vector(0, vr4181_handle_irq);

	/* init CPU irqs */
	mips_cpu_irq_init(VR4181_CPU_IRQ_BASE);

	/* init sys irqs */
	sys_irq_base = VR4181_SYS_IRQ_BASE;
	for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) {
		irq_desc[i].status = IRQ_DISABLED;
		irq_desc[i].action = NULL;
		irq_desc[i].depth = 1;
		irq_desc[i].handler = &sys_irq_controller;
	}

	/* init gpio irqs */
	gpio_irq_base = VR4181_GPIO_IRQ_BASE;
	for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) {
		irq_desc[i].status = IRQ_DISABLED;
		irq_desc[i].action = NULL;
		irq_desc[i].depth = 1;
		irq_desc[i].handler = &gpio_irq_controller;
	}

	/* Default all ICU IRQs to off ... */
	*VR4181_MSYSINT1REG = 0;
	*VR4181_MSYSINT2REG = 0;
 
	/* We initialize the level 2 ICU registers to all bits disabled. */
	*VR4181_MPIUINTREG = 0;
	*VR4181_MAIUINTREG = 0;
	*VR4181_MKIUINTREG = 0;

	/* disable all GPIO intrs */
	*VR4181_GPINTMSK = 0xffff;

	/* vector handler.  What these do is register the IRQ as non-sharable */
	setup_irq(VR4181_IRQ_INT0, &cascade);
	setup_irq(VR4181_IRQ_GIU, &cascade);

	/* 
	 * RTC interrupts are interesting.  They have two destinations.
	 * One is at sys irq controller, and the other is at CPU IP3 and IP4.
	 * RTC timer is used as system timer.
	 * We enable them here, but timer routine will register later
	 * with CPU IP3/IP4.
	 */
	setup_irq(VR4181_IRQ_RTCL1, &reserved);
	setup_irq(VR4181_IRQ_RTCL2, &reserved);

#ifdef CONFIG_REMOTE_DEBUG
	printk("Setting debug traps - please connect the remote debugger.\n");

	set_debug_traps();

	// you may move this line to whereever you want
	breakpoint();
#endif
}

--- NEW FILE: serial.c ---
/*
 * Copyright 2001 MontaVista Software Inc.
 * Author: Jun Sun, js...@mv... or js...@ju...
 *
 * arch/mips/vr4181/common/serial.c
 *     initialize serial port on vr4181.
 *
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

/*
 * [jsun, 010925]
 * You need to make sure rs_table has at least one element in 
 * drivers/char/serial.c file.	There is no good way to do it right
 * now.	 A workaround is to include CONFIG_SERIAL_MANY_PORTS in your
 * configure file, which would gives you 64 ports and wastes 11K ram.
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/serial.h>

#include <asm/vr4181/vr4181.h>

void __init vr4181_init_serial(void)
{
	struct serial_struct s;

	/* turn on UART clock */
	*VR4181_CMUCLKMSK |= VR4181_CMUCLKMSK_MSKSIU;

	/* clear memory */
	memset(&s, 0, sizeof(s));

	s.line = 0;			/* we set the first one */
	s.baud_base = 1152000;
	s.irq = VR4181_IRQ_SIU;
	s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */
	s.iomem_base = (u8*)VR4181_SIURB;
	s.iomem_reg_shift = 0;
	s.io_type = SERIAL_IO_MEM;
	if (early_serial_setup(&s) != 0) {
		panic("vr4181_init_serial() failed!");
	}
}


--- NEW FILE: time.c ---
/*
 * Copyright 2001 MontaVista Software Inc.
 * Author: js...@mv... or js...@ju...
 *
 * rtc and time ops for vr4181.	 Part of code is drived from 
 * linux-vr, originally written	 by Bradley D. LaRonde & Michael Klar.
 *
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/param.h>			/* for HZ */
#include <linux/time.h>
#include <linux/interrupt.h>

#include <asm/system.h>
#include <asm/time.h>

#include <asm/vr4181/vr4181.h>

#define COUNTS_PER_JIFFY ((32768 + HZ/2) / HZ)

/*
 * RTC ops
 */

spinlock_t rtc_lock = SPIN_LOCK_UNLOCKED;

/* per VR41xx docs, bad data can be read if between 2 counts */
static inline unsigned short 
read_time_reg(volatile unsigned short *reg)
{
	unsigned short value;
	do {
		value = *reg;
		barrier();
	} while (value != *reg);
	return value;
}

static unsigned long 
vr4181_rtc_get_time(void)
{
	unsigned short regh, regm, regl;

	// why this crazy order, you ask?  to guarantee that neither m
	// nor l wrap before all 3 read
	do {
		regm = read_time_reg(VR4181_ETIMEMREG);
		barrier();
		regh = read_time_reg(VR4181_ETIMEHREG);
		barrier();
		regl = read_time_reg(VR4181_ETIMELREG);
	} while (regm != read_time_reg(VR4181_ETIMEMREG));
	return ((regh << 17) | (regm << 1) | (regl >> 15));
}

static int 
vr4181_rtc_set_time(unsigned long timeval)
{
	unsigned short intreg;
	unsigned long flags;

	spin_lock_irqsave(&rtc_lock, flags);
	intreg = *VR4181_RTCINTREG & 0x05;
	barrier();
	*VR4181_ETIMELREG = timeval << 15;
	*VR4181_ETIMEMREG = timeval >> 1;
	*VR4181_ETIMEHREG = timeval >> 17;
	barrier();
	// assume that any ints that just triggered are invalid, since the
	// time value is written non-atomically in 3 separate regs
	*VR4181_RTCINTREG = 0x05 ^ intreg;
	spin_unlock_irqrestore(&rtc_lock, flags);

	return 0;
}


/* 
 * timer interrupt routine (wrapper)
 *
 * we need our own interrupt routine because we need to clear
 * RTC1 interrupt.
 */
static void 
vr4181_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	/* Clear the interrupt. */
	*VR4181_RTCINTREG = 0x2;

	/* call the generic one */
	timer_interrupt(irq, dev_id, regs);
}


/*
 * vr4181_time_init:
 *
 * We pick the following choices:
 *   . we use elapsed timer as the RTC.	 We set some reasonable init data since
 *     it does not persist across reset
 *   . we use RTC1 as the system timer interrupt source.
 *   . we use CPU counter for fast_gettimeoffset and we calivrate the cpu
 *     frequency.  In other words, we use calibrate_div64_gettimeoffset().
 *   . we use our own timer interrupt routine which clears the interrupt
 *     and then calls the generic high-level timer interrupt routine.
 *
 */

extern int setup_irq(unsigned int irq, struct irqaction *irqaction);

static void 
vr4181_timer_setup(struct irqaction *irq)
{
	/* over-write the handler to be our own one */
	irq->handler = vr4181_timer_interrupt;

	/* sets up the frequency */
	*VR4181_RTCL1LREG = COUNTS_PER_JIFFY;
	*VR4181_RTCL1HREG = 0;

	/* and ack any pending ints */
	*VR4181_RTCINTREG = 0x2;

	/* setup irqaction */
	setup_irq(VR4181_IRQ_INT1, irq);

}

void
vr4181_init_time(void)
{
	/* setup hookup functions */
	rtc_get_time = vr4181_rtc_get_time;
	rtc_set_time = vr4181_rtc_set_time;

	board_timer_setup = vr4181_timer_setup;
}

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/vr4181/osprey - New directory

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv27049/vr4181/osprey

Log Message:
Directory /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/osprey added to the repository

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/vr4181/common - New directory

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/common
In directory usw-pr-cvs1:/tmp/cvs-serv26982/vr4181/common

Log Message:
Directory /cvsroot/linux-mips/linux/arch/mips/vr41xx/vr4181/common added to the repository

[Linux-mips-commits]CVS: linux/arch/mips/vr4181/osprey Makefile,1.4,NONE dbg_io.c,1.3,NONE prom.c,1.6,NONE reset.c,1.4,NONE setup.c,1.6,NONE

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv26449/vr4181/osprey

Removed Files:
	Makefile dbg_io.c prom.c reset.c setup.c 
Log Message:
Send Osprey to a better place.



--- Makefile DELETED ---

--- dbg_io.c DELETED ---

--- prom.c DELETED ---

--- reset.c DELETED ---

--- setup.c DELETED ---

[Linux-mips-commits]CVS: linux/arch/mips/vr4181/common Makefile,1.3,NONE int_handler.S,1.3,NONE irq.c,1.9,NONE serial.c,1.4,NONE time.c,1.5,NONE

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/common
In directory usw-pr-cvs1:/tmp/cvs-serv26449/vr4181/common

Removed Files:
	Makefile int_handler.S irq.c serial.c time.c 
Log Message:
Send Osprey to a better place.



--- Makefile DELETED ---

--- int_handler.S DELETED ---

--- irq.c DELETED ---

--- serial.c DELETED ---

--- time.c DELETED ---

[Linux-mips-commits]CVS: linux/arch/mips/au1000/common usbdev.c,1.11,1.12

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv31034

Modified Files:
	usbdev.c 
Log Message:
Allow the device state to remain in the CONFIGURED state when a set
address request is received but the requested address hasn't changed.


Index: usbdev.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/usbdev.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- usbdev.c	29 May 2002 00:23:16 -0000	1.11
+++ usbdev.c	13 Jun 2002 18:42:22 -0000	1.12
@@ -449,10 +449,10 @@
 	dma_cache_wback_inv((unsigned long)pkt->payload, pkt->size);
 
 	/*
-	 * The write fifo should already be drained if things are
-	 * working right, but flush it anyway just in case.
+	 * make sure FIFO is empty
 	 */
 	flush_write_fifo(ep);
+
 	cs = au_readl(ep->reg->ctrl_stat) & USBDEV_CS_STALL;
 	cs |= (pkt->size << USBDEV_CS_TSIZE_BIT);
 	au_writel(cs, ep->reg->ctrl_stat);
@@ -491,6 +491,12 @@
 		     "NAK" : "ACK", pkt, ep->inlist.count);
 	}
 	
+	/*
+	 * The write fifo should already be drained if things are
+	 * working right, but flush it anyway just in case.
+	 */
+	flush_write_fifo(ep);
+
 	// begin transmitting next packet in the inlist
 	if (ep->inlist.count) {
 		kickstart_send_packet(ep);
@@ -555,11 +561,6 @@
 		return;
 	}
 
-	/*
-	 * The read fifo should already be drained if things are
-	 * working right, but flush it anyway just in case.
-	 */
-	flush_read_fifo(ep);
 	if (get_dma_active_buffer(ep->outdma) == 1) {
 		clear_dma_done1(ep->outdma);
 		set_dma_count1(ep->outdma, ep->max_pkt_size);
@@ -607,6 +608,10 @@
 	 * need to pull out any remaining bytes in the FIFO.
 	 */
 	endpoint_fifo_read(ep);
+	/*
+	 * should be drained now, but flush anyway just in case.
+	 */
+	flush_read_fifo(ep);
 	
 	pkt->status = (cs & USBDEV_CS_NAK) ? PKT_STATUS_NAK : PKT_STATUS_ACK;
 	if (ep->address == 0 && (cs & USBDEV_CS_SU))
@@ -648,7 +653,7 @@
 		break;
 	}
 
-	return SETUP_STAGE; // FIXME: must be status stage!
+	return STATUS_STAGE;
 }
 
 static ep0_stage_t
@@ -713,20 +718,26 @@
 static ep0_stage_t
 do_set_address(struct usb_dev* dev, devrequest* setup)
 {
-	dev->address = le16_to_cpu(setup->value);
-	dbg(__FUNCTION__ ": our address=%d", dev->address);
-	if (dev->address > 127 || dev->state == CONFIGURED) {
+	int new_state = dev->state;
+	int new_addr = le16_to_cpu(setup->value);
+	
+	dbg(__FUNCTION__ ": our address=%d", new_addr);
+
+	if (new_addr > 127) {
 		// usb spec doesn't tell us what to do, so just go to
 		// default state
-		dev->state = DEFAULT;
+		new_state = DEFAULT;
 		dev->address = 0;
-	} else if (dev->address)
-		dev->state = ADDRESS;
-	else
-		dev->state = DEFAULT;
-
-	/* inform function layer of usbdev state change */
-	dev->func_cb(CB_NEW_STATE, dev->state, dev->cb_data);
+	} else if (dev->address != new_addr) {
+		dev->address = new_addr;
+		new_state = ADDRESS;
+	}
+	
+	if (dev->state != new_state) {
+		dev->state = new_state;
+		/* inform function layer of usbdev state change */
+		dev->func_cb(CB_NEW_STATE, dev->state, dev->cb_data);
+	}
 	
 	return SETUP_STAGE;
 }
@@ -931,7 +942,7 @@
 }
 
 /*
- * A complete packet (SETUP, DATA0, or DATA1) has been received
+ * A SETUP, DATA0, or DATA1 packet has been received
  * on the default control endpoint's fifo.
  */
 static void
@@ -959,6 +970,9 @@
 	
 	switch (dev->ep0_stage) {
 	case SETUP_STAGE:
+		vdbg("SU bit is %s in setup stage",
+		     (pkt->status & PKT_STATUS_SU) ? "set" : "not set");
+		
 		if (pkt->size == sizeof(devrequest)) {
 #ifdef VDEBUG
 			if (pkt->status & PKT_STATUS_ACK)
@@ -978,7 +992,7 @@
 		 * now, set_descriptor not implemented.
 		 *
 		 * Need to place a byte in the write FIFO here, to prepare
-		 * to send a zero-length ACK packet to the host in the
+		 * to send a zero-length DATA ack packet to the host in the
 		 * STATUS stage.
 		 */
 		au_writel(0, ep0->reg->write_fifo);
@@ -1005,7 +1019,7 @@
 
 
 /*
- * A complete packet has been received on one of the OUT endpoints (4 or 5)
+ * A DATA0/1 packet has been received on one of the OUT endpoints (4 or 5)
  */
 static void
 process_ep_receive (struct usb_dev* dev, endpoint_t *ep)

[Linux-mips-commits]CVS: linux/include/asm-mips cpu.h,1.28,1.29

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv22884

Modified Files:
	cpu.h 
Log Message:
Brought in PRID_IMP_20KC from OSS.


Index: cpu.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cpu.h,v
retrieving revision 1.28
retrieving revision 1.29
diff -u -d -r1.28 -r1.29
--- cpu.h	11 Jun 2002 15:43:54 -0000	1.28
+++ cpu.h	13 Jun 2002 18:26:04 -0000	1.29
@@ -66,6 +66,7 @@
 #define PRID_IMP_R5500		0x5500
 #define PRID_IMP_4KC		0x8000
 #define PRID_IMP_5KC		0x8100
+#define PRID_IMP_20KC           0x8200
 #define PRID_IMP_4KEC		0x8400
 #define PRID_IMP_4KSC		0x8600
 

[Linux-mips-commits]CVS: linux/Documentation Configure.help,1.12,1.13

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/Documentation
In directory usw-pr-cvs1:/tmp/cvs-serv16356/Documentation

Modified Files:
	Configure.help 
Log Message:
CONFIG_COBALT_MICRO_SERVER -> CONFIG_MIPS_COBALT



Index: Configure.help
===================================================================
RCS file: /cvsroot/linux-mips/linux/Documentation/Configure.help,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- Configure.help	31 May 2002 20:12:20 -0000	1.12
+++ Configure.help	13 Jun 2002 13:35:48 -0000	1.13
@@ -1877,7 +1877,7 @@
   otherwise choose R3000.
 
 Support for Cobalt Micro Server
-CONFIG_COBALT_MICRO_SERVER
+CONFIG_MIPS_COBALT
   Support for MIPS-based Cobalt boxes (they have been bought by Sun
   and are now the "Server Appliance Business Unit") including the 2700
   series -- versions 1 of the Qube and Raq.  To compile a Linux kernel

[Linux-mips-commits]CVS: linux/arch/mips Makefile,1.49,1.50

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv16356/arch/mips

Modified Files:
	Makefile 
Log Message:
CONFIG_COBALT_MICRO_SERVER -> CONFIG_MIPS_COBALT



Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/Makefile,v
retrieving revision 1.49
retrieving revision 1.50
diff -u -d -r1.49 -r1.50
--- Makefile	5 Jun 2002 14:19:57 -0000	1.49
+++ Makefile	13 Jun 2002 13:35:49 -0000	1.50
@@ -172,7 +172,7 @@
 LOADADDR      += 0x80080000
 endif
 
-ifdef CONFIG_COBALT_MICRO_SERVER
+ifdef CONFIG_MIPS_COBALT
 SUBDIRS       += arch/mips/cobalt
 CORE_FILES    += arch/mips/cobalt/cobalt.o
 LOADADDR      += 0x80080000

[Linux-mips-commits]CVS: linux/arch/mips config.in,1.101,1.102

[Leblanc f. <fle...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv2868/arch/mips

Modified Files:
	config.in 
Log Message:
Correct CONFIG_PM conflict in config.in and move misplaced files.


Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.101
retrieving revision 1.102
diff -u -d -r1.101 -r1.102
--- config.in	30 May 2002 20:42:08 -0000	1.101
+++ config.in	13 Jun 2002 12:57:33 -0000	1.102
@@ -693,9 +693,9 @@
 define_bool CONFIG_BINFMT_AOUT n
 define_bool CONFIG_BINFMT_ELF y
 tristate 'Kernel support for MISC binaries' CONFIG_BINFMT_MISC
+dep_bool 'Power Management support (EXPERIMENTAL)' CONFIG_PM $CONFIG_EXPERIMENTAL
 
 if [ "$CONFIG_CASIO_E15" = "y" ]; then
-   bool 'Power Management support (experimental)' CONFIG_PM
    if [ "$CONFIG_PM" = "y" ]; then
       bool ' Support suspend/wakeup (VR41xx hibernate)' CONFIG_PM_SUSPEND_WAKEUP
       bool ' Support non-volatile suspend (VR41xx suspend)' CONFIG_PM_POWERED_SUSPEND
@@ -707,7 +707,6 @@
    fi
 fi
 dep_bool 'Support CPU clock change (EXPERIMENTAL)' CONFIG_CPU_FREQ $CONFIG_EXPERIMENTAL
-dep_bool 'Power Management support (EXPERIMENTAL)' CONFIG_PM $CONFIG_EXPERIMENTAL $CONFIG_MIPS_AU1000
 endmenu
 
 source drivers/mtd/Config.in

[Linux-mips-commits]CVS: linux/arch/mips/configs defconfig-casio-e15,1.5,1.6

[Leblanc f. <fle...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/configs
In directory usw-pr-cvs1:/tmp/cvs-serv2868/arch/mips/configs

Modified Files:
	defconfig-casio-e15 
Log Message:
Correct CONFIG_PM conflict in config.in and move misplaced files.


Index: defconfig-casio-e15
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-casio-e15,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- defconfig-casio-e15	13 Jun 2002 07:45:19 -0000	1.5
+++ defconfig-casio-e15	13 Jun 2002 12:57:33 -0000	1.6
@@ -10,22 +10,40 @@
 CONFIG_EXPERIMENTAL=y
 
 #
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
 # Machine selection
 #
 # CONFIG_ACER_PICA_61 is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1500 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_DECSTATION is not set
-# CONFIG_DDB5074 is not set
-# CONFIG_NEC_EAGLE is not set
-# CONFIG_NEC_KORVA is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
 # CONFIG_MIPS_MALTA is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_NEC_EAGLE is not set
+# CONFIG_NEC_KORVA is not set
+# CONFIG_OLIVETTI_M700 is not set
 # CONFIG_NINO is not set
-# CONFIG_SIBYTE_SB1250 is not set
 # CONFIG_PS2 is not set
 # CONFIG_CASIO_BE300 is not set
 CONFIG_CASIO_E15=y
@@ -36,26 +54,14 @@
 # CONFIG_IBM_WORKPAD is not set
 # CONFIG_CASIO_E55 is not set
 # CONFIG_VICTOR_MPC303 is not set
-# CONFIG_MIPS_MAGNUM_4000 is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_DDB5476 is not set
-# CONFIG_DDB5477 is not set
-# CONFIG_NEC_OSPREY is not set
-# CONFIG_OLIVETTI_M700 is not set
 # CONFIG_SGI_IP22 is not set
+# CONFIG_SIBYTE_SB1250 is not set
 # CONFIG_SNI_RM200_PCI is not set
-# CONFIG_MIPS_ITE8172 is not set
-# CONFIG_MIPS_IVR is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1100 is not set
 # CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_HP_LASERJET is not set
+# CONFIG_MIPS_LXPB20K is not set
 # CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-# CONFIG_MCA is not set
-# CONFIG_SBUS is not set
 CONFIG_CPU_VR41XX=y
 CONFIG_VR4111=y
 CONFIG_NEW_IRQ=y
@@ -70,19 +76,13 @@
 CONFIG_VR41XX_LED=y
 CONFIG_GPIO_LCD=y
 CONFIG_VR41XX_EXTEND_HIBERNATE=y
-CONFIG_EISA=y
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODVERSIONS is not set
-CONFIG_KMOD=y
+# CONFIG_MIPS_AU1000 is not set
 
 #
 # CPU selection
 #
 # CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_LX45XXX is not set
 # CONFIG_CPU_TX39XX is not set
 # CONFIG_CPU_R6000 is not set
 CONFIG_CPU_VR41XX=y
@@ -112,8 +112,20 @@
 # CONFIG_CPU_R5900_CONTEXT is not set
 # CONFIG_VR4131_CACHE_FIX is not set
 # CONFIG_VR4122_CLKSPEEDREG_FIX is not set
+CONFIG_NET=y
+# CONFIG_PCI is not set
+CONFIG_EISA=y
+# CONFIG_TC is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+# CONFIG_HOTPLUG_PCI is not set
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_SYSCTL=y
 CONFIG_KCORE_ELF=y
-CONFIG_ELF_KERNEL=y
+# CONFIG_KCORE_AOUT is not set
 # CONFIG_BINFMT_AOUT is not set
 CONFIG_BINFMT_ELF=y
 CONFIG_BINFMT_MISC=y
@@ -124,19 +136,6 @@
 CONFIG_PROC_GIUINFO=y
 # CONFIG_MOUNT_PROC is not set
 # CONFIG_CPU_FREQ is not set
-CONFIG_NET=y
-# CONFIG_HOTPLUG is not set
-# CONFIG_PCMCIA is not set
-# CONFIG_HOTPLUG_PCI is not set
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_SYSCTL=y
-
-#
-# Plug and Play configuration
-#
-# CONFIG_PNP is not set
-# CONFIG_ISAPNP is not set
 
 #
 # Memory Technology Devices (MTD)
@@ -149,6 +148,12 @@
 # CONFIG_PARPORT is not set
 
 #
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
 # Block devices
 #
 # CONFIG_BLK_DEV_FD is not set
@@ -275,15 +280,6 @@
 # CONFIG_SCSI is not set
 
 #
-# I2O device support
-#
-# CONFIG_I2O is not set
-# CONFIG_I2O_BLOCK is not set
-# CONFIG_I2O_LAN is not set
-# CONFIG_I2O_SCSI is not set
-# CONFIG_I2O_PROC is not set
-
-#
 # Network device support
 #
 CONFIG_NETDEVICES=y
@@ -615,15 +611,6 @@
 # CONFIG_FB_CYBER2000 is not set
 # CONFIG_FB_E1355 is not set
 # CONFIG_FB_MQ200 is not set
-# CONFIG_FB_MATROX is not set
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_RADEON is not set
-# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_SIS is not set
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-# CONFIG_FB_TRIDENT is not set
-# CONFIG_FB_E1356 is not set
 # CONFIG_FB_IT8181 is not set
 # CONFIG_FB_SIMPLE is not set
 CONFIG_FB_HPCSFB=y

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/common Makefile,1.6,1.7 adif.c,1.1,NONE gpiolcd.c,1.1,NONE

[Leblanc f. <fle...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/common
In directory usw-pr-cvs1:/tmp/cvs-serv2868/arch/mips/vr41xx/common

Modified Files:
	Makefile 
Removed Files:
	adif.c gpiolcd.c 
Log Message:
Correct CONFIG_PM conflict in config.in and move misplaced files.


Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/common/Makefile,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- Makefile	7 Mar 2002 09:15:16 -0000	1.6
+++ Makefile	13 Jun 2002 12:57:33 -0000	1.7
@@ -19,12 +19,8 @@
 
 obj-$(CONFIG_VR41XX_TIME_C)	+= time.o
 
-obj-$(CONFIG_ADIF) += adif.o
 obj-$(CONFIG_VR41XX_LED) += led.o
 obj-$(CONFIG_PROC_GIUINFO) += giuinfo.o
 obj-$(CONFIG_PM) += power.o
-obj-$(CONFIG_GPIO_LCD) += gpiolcd.o
-
-#obj-$(CONFIG_BLK_DEV_IDE) += ide-vr41xx.o
 
 include $(TOPDIR)/Rules.make

--- adif.c DELETED ---

--- gpiolcd.c DELETED ---

[Linux-mips-commits]CVS: linux/drivers/char adif.c,NONE,1.1 Makefile,1.31,1.32

[Leblanc f. <fle...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv2868/drivers/char

Modified Files:
	Makefile 
Added Files:
	adif.c 
Log Message:
Correct CONFIG_PM conflict in config.in and move misplaced files.


--- NEW FILE: adif.c ---
/*
 * linux/arch/mips/vr41xx/adif.c
 *
 * VR41xx Lvl A/D driver
 *
 * Parts Copyright (C) 2001 Chris AtLee <ca...@ca...>
 * Parts Copyright (C) 2001 Paul Jimenez <pj...@ag...>
 * Parts Copyright (C) 2001 Alexandre d'Alton <ale...@ya...>
 * 
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/miscdevice.h>
#include <linux/fs.h>
#include <linux/major.h>
#include <linux/sched.h>

#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/irq.h>
#include <asm/vr41xx.h>

#define VR41XX_ADIF_MINOR 15

static wait_queue_head_t wait;

static void
adif_irq_handler (int irq, void *dev_id, struct pt_regs *regs)
{
  wake_up_interruptible (&wait);
}


static int
adif_open (struct inode *inode, struct file *file)
{
  /* Readonly, sure they can all be open */
  return 0;
}


static int
adif_close (struct inode *inode, struct file *file)
{
  return 0;
}

static ssize_t
adif_read (struct file *file, char *buf, size_t count, loff_t * offset)
{
  int original_stable;
  unsigned short adin[4];
  ssize_t retval;
  unsigned long flags;
  unsigned int j;

  if (count < 4 * sizeof (short))
	{
	  printk ("adif: Invalid count(%d) specified (must be at least %d)\n",
			  count, 4 * sizeof (short));
	  return 0;
	}

	/*** get battery readings here */
	/** wait til we get into one of Standby, WaitPenTouch, or Interval state per
           VR4181.pdf 19.4 */
  /* If the pen is down, we can't use the PIU, so we wait. */
  cli();
  while(*VR41XX_PIUCNTREG & 0x2000){
    sti();
    j = jiffies + 100;
    while(jiffies < j)
      schedule();
  }
  
  save_and_cli (flags);
  /* We need to activate the PIU clocks. */
  *VR41XX_CMUCLKMSK |= (VR41XX_CMUCLKMSK_MSKKIU|
						VR41XX_CMUCLKMSK_MSKSIU);
  barrier ();

  /* All these step are probably not needed, but they were for debugging */
  *VR41XX_PIUCNTREG = 1;

  *VR41XX_PIUCNTREG = 0x2;		/* Power up the PIU */

#define PIU_IN_STANDBY ((*VR41XX_PIUCNTREG & 0x1c00) == 0x0400)

  while (!PIU_IN_STANDBY)
	*VR41XX_PIUCNTREG &= ~0x2;	/* Go in standby state */
  barrier ();
  *VR41XX_PIUAMSKREG = 0xFF0F;	/* Mask ADIN[0-2] & MIC pins */
  barrier ();

  restore_flags (flags);

  /* set irq */
  /* When we share IRQ we have to differentiate between two handlers
     for the same IRQ, that's why we put the address ow the wait queue
     as last argument to request_irq. */
  if (retval = request_irq (VR41XX_IRQ_PIU, adif_irq_handler, SA_SHIRQ,
							"vr41xx_battery_level", &wait))
	{
	  /* restore PIUSTBLREG */
//                *VR41XX_PIUSTBLREG = original_stable;
	  printk ("adif: unable to request_irq (%d)\n", retval);
	  return -retval;
	}
  barrier ();

  save_and_cli (flags);
  /* start the process */
  *VR41XX_PIUASCNREG = 0x1;
  barrier ();
  *VR41XX_PIUCNTREG |= 0x0004;
  barrier ();
  restore_flags (flags);

  /* sleep until the value is ready */
  interruptible_sleep_on (&wait);

  save_and_cli (flags);
  *VR41XX_PIUAMSKREG = 0xFFF0;
  *VR41XX_PIUASCNREG = 0x2;
  barrier ();

  /* read values */
  adin[0] = *VR41XX_PIUAB0REG;
  adin[1] = *VR41XX_PIUAB1REG;
  adin[2] = *VR41XX_PIUAB2REG;
  adin[3] = *VR41XX_PIUAB3REG;

  /* Reset the PIU Controler in its default state */
  *VR41XX_PIUCNTREG = 1;
  barrier();
  *VR41XX_PIUCNTREG = 0x2;		/* Power up the PIU */
  barrier();
  while (!PIU_IN_STANDBY)
	*VR41XX_PIUCNTREG &= ~0x2;	/* Go in standby state */
  *VR41XX_PIUCNTREG = 0x0322;
  barrier ();
  *VR41XX_PIUSIVLREG = 333;		// set interval to .01 sec default
  *VR41XX_PIUSTBLREG = 0x10;
  barrier ();
  *VR41XX_MPIUINTREG = 0x007d;
  barrier ();
  *VR41XX_PIUCNTREG = 0x0326;	// resume autoscan
  barrier ();
  /* Shut down the clocks. */
  *VR41XX_CMUCLKMSK &= ~(VR41XX_CMUCLKMSK_MSKKIU |
						 VR41XX_CMUCLKMSK_MSKSIU);
  restore_flags (flags);

  free_irq (VR41XX_IRQ_PIU, &wait);

//  printk ("adif: returning %d, %d, %d, %d\n", adin[0], adin[1], adin[2],
//		  adin[3]);
  if (!access_ok(VERIFY_WRITE, buf, 8))
    return -EFAULT;

  __put_user (adin[0], (short *) (buf));
  __put_user (adin[1], (short *) (buf + 2));
  __put_user (adin[2], (short *) (buf + 4));
  __put_user (adin[3], (short *) (buf + 6));


  return 4 * sizeof (short);
}


static struct file_operations adif_fops;
static struct miscdevice adif_device;


static int
adif_init (void)
{
  int retval;

  init_waitqueue_head (&wait);
  /* NULL out the data structure before filling it */
  memset (&adif_fops, 0, sizeof (struct file_operations));
  adif_fops.read = adif_read;
  adif_fops.open = adif_open;
  adif_fops.release = adif_close;

  /* NULL out the data structure before filling it */
  memset (&adif_device, 0, sizeof (struct miscdevice));
  adif_device.minor = VR41XX_ADIF_MINOR;
  adif_device.name = "adif";
  adif_device.fops = &adif_fops;

  /* register it */
  retval = misc_register (&adif_device);

  if (retval < 0)
	{
	  printk ("Failed to register A/D interface driver\n");
	  return retval;
	}
  printk ("A/D interface driver registered on %i,%i\n", MISC_MAJOR,
		  VR41XX_ADIF_MINOR);

  return 0;
}


static void
adif_exit (void)
{
  if (0 > misc_deregister (&adif_device))
	printk ("Error unregistering A/D interface driver\n");
}

module_init (adif_init);
module_exit (adif_exit);

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Makefile,v
retrieving revision 1.31
retrieving revision 1.32
diff -u -d -r1.31 -r1.32
--- Makefile	31 May 2002 20:12:20 -0000	1.31
+++ Makefile	13 Jun 2002 12:57:33 -0000	1.32
@@ -270,6 +270,7 @@
 obj-$(CONFIG_VR41XX_GPIO_BUTTONS) += gpiobtns.o
 obj-$(CONFIG_VR41XX_E105_BUTTONS) += e105btns.o
 obj-$(CONFIG_TOUCH_PANEL) += tpanel.o
+obj-$(CONFIG_ADIF) += adif.o
 
 subdir-$(CONFIG_MWAVE) += mwave
 ifeq ($(CONFIG_MWAVE),y)